JPH01245553A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the integration degree of the title device by a method wherein a region ranging from a well region provided with the collectors and emitters of a MISFET to the collector or emitter of a bipolar transistor is constituted of one continuous semiconductor region without providing an element isolation region between the collectors or the emitters and a prescribed potential is applied to this semiconductor region through a high-impurity concentration semiconductor region to execute an element isolation. CONSTITUTION:A region ranging from a well region 3A provided with a MISFET Qp1 to a collector or an emitter 3B of a bipolar transistor BiP1 is constituted of one continuous first semiconductor region and a second semiconductor region 8A; which has the same conductivity type as that of the first semiconductor region, has an impurity concentration higher than that of the first semiconductor region and moreover, is deep in a depth ranging from the surface of the first semiconductor region to nearly its bottom part; is provided between the transistor BiP1 and the MISFET Qp1 of the first semiconductor region. The electrical isolation between the transistor BiP1 and the region 3A is conducted by applying a prescribed potential to the high-impurity concentration second semiconductor region 8A provided between the transistor BiP1 and the MISFET Qp1.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device in which a bipolar transistor and a MISFET are provided on one semiconductor substrate, and particularly relates to a semiconductor integrated circuit device in which a bipolar transistor and a MISFET are provided in a semiconductor integrated circuit device. The present invention relates to a technology that is effective when applied to element isolation technology between the two regions.

[Conventional technology]

Some semiconductor integrated circuit devices include a bipolar transistor, a P-channel MISFE'1', and an N-channel MISFET provided on one semiconductor substrate.

As the bipolar transistor, an NPN bipolar transistor is usually used. Therefore, p-
type semiconductor substrate is used. N 1' N bipolar 1
From the bottom, the helangistor consists of an n-type buried layer, an rfπ
It is constructed with a p-type collector, a p-type base, and an n°-type emitter. On the other hand, the P-channel MISFET is
The n-type well region is provided in the π-type well region, and the n-type well region is provided on an n-type buried layer provided in the semiconductor substrate separately from the n-type buried layer of the bipolar transistor. Also, N-F-Yarnel M I S F E T is p
This p- type well region is provided on a p° type semiconductor region (p' type buried layer). And these bipolar! - The transistor, P-channel MTSFET, and N-channel MISFET must be electrically isolated so that their electrical operations do not affect each other. here.

The collector of a bipolar transistor is of the rc type, and the buried layer under the π-type collector is of the n-type, whereas the well region in which the N-channel MISFET is provided is of the p-type. Since the buried layer below is of the p° type, the bipolar transistors and the N-channel MISFET are naturally electrically isolated from each other. However, bipolar 1 to transistor ■]
In the channel MISFET, the collector of the bipolar transistor and the π-type well region in which the P-channel MISFET is provided are of the same conductivity type, and the bottoms of the collector and 1-type well region are both of the n° type. Since it is a buried layer, a P-type semiconductor region is interposed between the n-type collector and the π-type well region, and a P-type semiconductor region is interposed between the n-type buried layer and the P
Electrical isolation is achieved by interposing a p° type semiconductor region (p' type buried layer) between the n° type buried layers of the channel MISFET.

[Problem to be solved by the invention]

The inventor of the present invention discovered the following problem as a result of studying the element isolation region made of the p-type semiconductor region.

Some bipolar transistors provided on a semiconductor substrate constantly supply power supply potential Vcc to the π-type collector and the n'-type buried layer below it, keeping them in an electrically fixed state. -0 while P channel M
In order to operate the P-channel MISFET stably, the r)-type well region where the ISFET is provided and the ri''-type buried layer below it are always supplied with a power supply potential V.
cc is applied. Therefore, this collector and the buried layer below it are bipolar 1 whose collector is fixed to the power supply potential.
~The electrical operations between the transistor and the P-channel MISFET do not affect each other.

However, in the conventional semiconductor integrated circuit device, as described above, the bipolar transistor 1 to the transistor whose n-type collector and the Ir-type buried layer thereunder are fixed to the power supply potential Vcc,
P channel M I S l? Electrical isolation is also provided between the n-type well region where ET is provided and the ri'' type buried layer below, and the p-type well region and the p°-type semiconductor region below. In other words, bipolar transistors whose electrical operations do not affect each other,
Since a p-type well region and a p°-type semiconductor region for element isolation were provided between the ri-type well region where the P-channel MISFET is provided and the n-type buried layer, the semiconductor integrated circuit This has been a problem in that it becomes an obstacle when trying to improve the degree of integration of the device.

An object of the present invention is to provide a technique that can improve the degree of integration of a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique that can reduce the occurrence of latch-up.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

That is, a bipolar transistor is provided on a semiconductor substrate, a well region of a conductivity type opposite to that of the semiconductor substrate is provided in a portion of the semiconductor substrate remote from the bipolar transistors 1 to transistors, and an M I S FET is provided on the surface of the well region.
In the semiconductor integrated circuit device provided with the MISFE
One continuous first layer extends from the well region where T is provided to the collector or emitter of the bipolar transistor.
between the bipolar transistor and the MISFET in the first semiconductor region, a semiconductor region having the same conductivity type as the first semiconductor region and having a higher impurity concentration than the first semiconductor region; A second semiconductor region having a deep depth reaching the bottom is provided.

[Effect]

According to the above-mentioned means, in a bipolar transistor in which the collector or emitter is always applied with the same potential as the well region, the M I S FE from the collector or emitter is
The bipolar transistor and the well region are electrically isolated from each other by providing electrical isolation between the bipolar transistor and the MISFET. This is performed by applying a predetermined potential to the second semiconductor region having a high impurity concentration. That is, electrical isolation between the bipolar transistor and the well region in which the MI S FET is provided is performed without intervening the collector or emitter of the bipolar transistor or a semiconductor region of a conductivity type opposite to that of the well region. It will be done. In this way, since no semiconductor region for electrical isolation is provided between the collector or emitter and the well region to which the same potential is applied, the degree of integration of the semiconductor integrated circuit device can be improved.

Further, the base of the bipolar transistor is the collector, the first and second semiconductor regions are the bases, and the source of the MISFET provided in the well region;
In a parasitic bipolar transistor with a drain as an emitter, since the impurity concentration in the second semiconductor region, which is a part of the base of the parasitic piebola transistor, is high, the minority carriers of the parasitic bipolar transistor can be removed in a short time. It can be made to disappear. As a result, the parasitic bipolar transistor does not operate, so that the occurrence of latch-up can be reduced.6 [Embodiment of the Invention] Hereinafter, a semiconductor integrated circuit device according to an embodiment of the present invention will be described in detail based on the drawings. explain.

FIG. 1 is a plan view of the main parts of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a plan view of the main parts of the semiconductor integrated circuit device shown in FIG. 1, excluding the wiring on the semiconductor substrate. FIG. 3 is a cross-sectional view of the main part of the semiconductor integrated circuit device shown in FIG. 1 taken along cutting line I■-1■, and FIG. FIG.

5 is a sectional view taken along the cutting line ■--■ of the main part of the semiconductor integrated circuit device shown in FIG. 1, and FIG. 6 is a sectional view of the main part of the semiconductor integrated circuit device shown in FIG. FIG. 7, which is a sectional view taken along the cutting line, is an equivalent circuit diagram of a main part of the semiconductor integrated circuit device shown in FIG.

Note that the IV views of FIGS. 1 and 2 do not show any insulating films other than the field insulating film in order to make it easier to understand the structure of the semi-quadram element on the semiconductor substrate. An outline of the configuration of each semiconductor element provided on a semiconductor substrate will be explained using FIGS. 7 to 7.

As shown in FIGS. 1 to 7, the semiconductor substrate 1 includes:
NPN bipolar transistor (hereinafter simply referred to as 1-transistor) BiPl, BiF3, P channel MIS
FETQpl, N-channel MISFETQn 1. Qn
2. Qn3 is provided. Semiconductor substrate 1 is made of p-type single crystal silicon. Said P channel MIS
FETQpl is provided in the n-type well region 3A and serves as a source.

A p-type semiconductor region 9 that becomes a drain, a gate insulating film 10 made of a silicon oxide film, and a two-layer film in which a high melting point metal silicide film 11B such as tungsten silicide is laminated on a polycrystalline silicon film 11A. The gate electrode 11 is composed of a gate electrode 11 and a gate electrode 11. 12 is a side wall made of a silicon oxide film.

■) Channel M I S [” of p-type well region 3A
Near E T Qpl, there is a U-shaped plane pattern n.

A type semiconductor region 8A is provided. Next, the one transistor BiP1 includes an n-type buried layer 2A, an ri-type collector 3B, an n-type collector extraction layer 8B, and a p-type buried layer 2A.
It is composed of a type base 13A and an n-type emitter 14A. The transistor BiP2 has an n° type buried layer 2B.
, an n-type collector 3C, two II'-type collector extraction layers 8C provided at both ends of this n-type collector 3C, a p-type base 13B, and an r1'-type emitter 14B.
It is made up of. The N-channel MISFET Qnl is provided in the p-well region 5 and is composed of an l-type semiconductor region 16A and an n°-type semiconductor region 15A, which serve as a source and drain, a gate insulating film 10, and a gate electrode 11. ing. The above-mentioned type semiconductor region 16A is p″
It is provided along the edge of the gate electrode 11 on the surface of the mold well region 5 . N-channel MISFETQn2 is the source.

It is composed of an r type semiconductor region 16B and an n''M semiconductor region 15B, which serve as a train, an insulating film 10, and a gate electrode 11.N channel MISFETQn
3 is a π-type semiconductor region 16C which becomes a source and a drain.
and an n° type semiconductor region 15C, a gate insulating film 10,
It is composed of a gate electrode 11. These transistors BiP1. BiP2. P-channel MISFETQP1
．． N-channel M I S F E T Q n l .

Qn2. Qn3 is connected by a first layer of wiring made of aluminum film, but this first layer of wiring is 1
It is shown with a code in the 00 series.

The symbol with an X in the mouth represents a connection hole for connecting the wiring made of the first layer of aluminum film to each semiconductor element, and this connection hole is numbered 21. It is shown as follows. Moreover, a second layer of wiring made of an aluminum film is provided on the wiring made of the first layer of aluminum film, and this second layer of wiring is given a code in the 200s. It is shown as follows. A connection hole for connecting the second layer wiring and the first layer wiring is indicated by an O symbol and is designated by the reference numeral 23.

p° which becomes the source of the P-channel MISFET Qpl
type semiconductor region 9 and this P-channel MISFE'rQp
It is connected to the n° type semiconductor region 8A provided around l by a wiring 102. In addition, the ri-type semiconductor region 8A
and n° type collector extraction layer 8 of transistor BiP1.
B is connected by a wiring 101. These wirings 101 and 102 have a power supply potential Vcc of, for example, 5.
A second layer wiring 201 for supplying power is connected. Therefore, the p°-type semiconductor region 9, which becomes the source of the P-channel MISFET Qpl, the n°-type semiconductor region 8A, and the n°-type collector extraction layer 8B of the l-transistor BiP1 are constantly applied with the g-type g potential Vcc. Ru.

Next, P channel) IiM I S FETQp 1 (
1) A P° type semiconductor region 9 serving as a drain, a transistor B i P 1 (1) I) type base 13A, and an N channel M I S ! ” The n-type semiconductor region 15A, which becomes a part of the train of E'rQn1, and the N-channel M
A wiring 104 is connected between the goo 1 and the electrode 11 of ISFETQn3.

A second-layer wiring 202 for supplying a ground potential Vss, for example, Ov, is connected to the +i'-type semiconductor region 15A, which becomes a part of the source of the N-channel MISFETQnl, through a first-layer aluminum film 109. It is connected.

Therefore, the ground potential VsS is always applied to the II" type semiconductor region 15A and the rl- type semiconductor region 16A, which are the sources of the N-channel MTSFETQnl. Next, the n° type emitter 14A of the transistor Bi'PL and ,
It is connected to one of the two n° type collector lead-out layers 8C of the transistor BiP2 through a wiring IA105. This wiring [105 is the transistor BiP1. B
iP2, P channel MISFET QPI, N channel M
I S F E T Q nl, Qn2. This is the output terminal of the circuit made up of Qn3. The other n° type collector extraction layer 8C of the transistor BiP2, which is different from the above, is connected to the N channel M I by the wiring 108.
It is connected to the n° type semiconductor region 15B which becomes the source or drain of S F E TQ n 2. p-type base 13B of transistor BiP2 and N-channel MISF
Another n-type semiconductor region 1 different from the above of ETQn2
It is connected to 5B by a wiring 107. n° type emitter 14B of transistor BiP2 and N channel MIS
The n° type semiconductor region 15C of FETQ n 3 is connected to the wiring 1
It is connected with 06. N channel M I S F E
Gate electrode 11 of T Q n 1 and N channel M
The gate electrode 11 of I S F E T Q t12 is
The ends are integrated. A wiring 103 is connected to the gate electrode 11 of the two N-channel MISFETs Qn2 and Qn3 and the gate electrode 11 of the P-channel MISFET Qp1. This wiring 103
are transistors B i Pl, BiF3, and P-channel MISFET Qpl.

N-channel MI 5FETQn l, Qn 2. Qn
This is the input terminal of the circuit consisting of 3.

Under the first layer wirings 101 to 109, a first layer passivation film 2 made of, for example, a silicon oxide film is provided.
0 is set. In addition, the first layer wiring 101 to 1
09 and the second layer wirings 201 to 202, for example, phosphosilicate glass (PSG) is placed on the silicon oxide film.
) A second layer passivation film 22 is provided which is formed by laminating films.

Next, transistors BiPl, BiP2 . P channel M
I S FETQp 1, N channel MISFETQn
l, QnP2. Element isolation between each of Qn3 will be explained.

First, transistor BiPl and P channel MISF
Element isolation between E T Q p 1 will be explained.

As shown in FIGS. 1 to 3, P channel MI
n-type well region 3A where SFETQpl is provided
Around the P-channel MISFET Qpl, there is a U-shaped n-type transistor with high impurity concentration and low resistance value.
A ° type semiconductor region 8A is provided, and a power supply potential Vcc is constantly applied through this n ° type semiconductor region 8A. Further, an n° type buried layer 2A with a small resistance value, which forms a part of the collector of the transistor BiP1, extends below the π type well region 3A and the n° type semiconductor region 8A, and extends under the ri type well region 3A. and n° type semiconductor region 8A. in this way,
By providing the n° type buried layer 2A under the π type well region 3A, the potential of the n− type well region 3A is n°.
Even in a portion far from the n-type semiconductor region 8A, the power supply potential Vcc is well supplied from the n-type semiconductor region 8A through the r1-type buried layer 2A, so that the transistor Bi
Power supply potential V c c without being affected by the operation of Pl
Fixed. That is, the n-type well region 3 is isolated from transistors 1 to BiPl by the n-type semiconductor region 8A and the n-type buried layer 2A. On the other hand, the r" type collector 3B of the transistor BiP1 has an n" type collector extraction layer 8B and an n° type buried layer 2.
Since the power supply potential Vcc is always supplied through A and is in an electrically fixed state, the P-channel MISFET
without being affected by the operation of Qpl.

electrically isolated.

The π-type well region 3A and the n-type collector 3B of the transistor BiP1 are one continuous n-type well region when the n-type semiconductor region 8A is not provided, and this one continuous n-type well region The n-type semiconductor region 8A is provided and divided into two parts: an n-type well region 3A and an n-type collector 3B.

Next, transistor BiP1 and P channel MI S
FET Q p l and transistor B i P
2 is a p° type semiconductor region (
p" type buried layer) 4, p- type well region 5 provided in the same pattern on this P° type semiconductor region 4, and p-
It is electrically isolated from a p-type channel stopper region 6 formed on the surface of the type well region 5. Similarly, between transistor BiP2 and N-channel MISFETQnl, 1-transistor BiP2 and N-channel MISFETQ
n2 or Qn3, and between N-channel MISFETQnl and N-channel MISFETQn2 or Qn3, respectively.

The p'' type semiconductor region 4, the p'' type well region 5, and the p'' type semiconductor region 4, the p'' type well region 5,
It is electrically isolated from the mold channel stopper region 6. N channel M I S F E T Q n 2 and Q
Since the gate electrodes 113 share the n° type semiconductor region 15B between the gate electrodes 11, they are not isolated.

Next, a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described.

8 to 19 are diagrams for explaining the manufacturing method of the semiconductor integrated circuit device, in which region A is a cross-sectional view of a portion where transistor t3 i P l is formed, and region B is a cross-sectional view of a portion where a P-channel MIsFET Qpl is formed. A cross-sectional view of the formed portion, region C is an N-channel MISFETQn lr Qn
For example, N channel M I S of 2r Qn 3
FIG. 3 is a cross-sectional view of a portion where FETQn1 is formed. Note that the manufacturing method of the transistor BiP2 is the same as that of the transistor B i P l, and the N-channel M I S F E 'L' Q n 2 , Q n
The manufacturing method of No. 3 is an N-channel MISFET.
Since it is Q n l, the explanation will be omitted.

The method for manufacturing the semiconductor integrated circuit device of this embodiment starts with p
The entire surface of the - type semiconductor substrate 1 is thermally oxidized to form a thin silicon oxide film 30 (FIG. 8). next.

A silicon nitride film 31 (FIG. 8) is formed on the silicon oxide film 30 by, for example, CVD. Then, these silicon nitride film 31 and silicon oxide film 30 are selectively removed by etching using a resist film.

The surfaces of region A and region B of semiconductor substrate 1 are exposed.

Next, an n-type impurity such as As is diffused into the surfaces of the exposed regions A and B of the semiconductor substrate 1 by thermal diffusion to form an n°-type buried layer 2A, as shown in FIG. next,
The exposed surface of the n° type buried Wj2A is thermally oxidized to form a silicon oxide film 32 slightly thicker than the silicon oxide film 30, as shown in FIG. Next, the silicon nitride film 31 is removed, and p-type impurities such as boron are introduced into the surface of the semiconductor substrate 1 other than the n-type buried layer 2A by ion implantation using the silicon oxide film 32 as a mask. Then, by thermally diffusing this p-type impurity, the 10th
As shown in the figure, a p' type semiconductor region 4 is formed.

Next, the silicon oxide films 30 and 32 are removed, and after that, n
An epitaxial layer 36 (FIG. 11) is formed on the ° type buried layer 2A and the p' type semiconductor region 4. Although this epitaxial layer 36 is formed on the semiconductor substrate 1, it substantially functions as a part of the semiconductor substrate 1. Next, the surface of this epitaxial layer 36 is thermally oxidized to form a thin silicon oxide film 33, and then a thin silicon oxide film 33 is formed.
A silicon nitride film 34 (FIG. 11) is formed on the silicon nitride film 34 by, for example, CVD. After removing the portions above the regions A and B of the silicon nitride film 34 by etching using the resists 1 to 35 (FIG. 11), the regions of the epitaxial layer 36 are removed as shown in FIG. An n-type impurity 37 such as phosphorus or arsenic is introduced into regions A and B by ion implantation. Next, a portion of the surface of the epitaxial layer 36 exposed from the silicon nitride film 34 is thermally oxidized to form a silicon oxide film 38 (FIG. 12) that is slightly thicker than the silicon oxide film 33. When forming this silicon oxide film 38, the n-type impurity 37 introduced earlier (FIG. 11)
is slightly diffused into epitaxial layer 36. After forming the silicon oxide film 38, as shown in FIG. 12, an n-type impurity 39, for example, is added to the portion of the epitaxial layer 36 where the silicon oxide film 38 is not provided for forming the P-type well region 5. Boron is introduced by ion implantation. Next, for example, CV
A silicon nitride film 40 (FIG. 13) is formed in step D, and this silicon nitride film 40 is selectively removed by etching using a resist film (FIG. 13), and later a field I/insulating film 7 is formed. Form the mask of time. The heat generated when forming the silicon nitride film 40 by the CVD causes the previously introduced n-type impurity 39 to be slightly diffused, forming a shallow p-type well region 5. Next, as shown in FIG. 13, using the silicon nitride film 40 and the silicon oxide film 38 as masks for ion implantation, ions are implanted into the portion exposed from the silicon nitride film 40 on the surface of the p- type well region 5. n-type impurity 4 for forming type channel stopper region 6
1 will be introduced. Next, the portions of the surfaces of the n-type well region 3 and the p-type well region 5 exposed from the silicon nitride film 40 are thermally oxidized to form a field insulating film 7, as shown in FIG. The heat generated when forming the field insulating film 7 diffuses each of the shallow n-type well region 3 and the p-type well region 5, and the 1-type well region 3 becomes an n-type well region.
The p-type well region 5 reaches the p-type semiconductor region 4. Further, the p-type impurity introduced earlier to form the P channel stopper region 6 is diffused by the heat generated when forming the field insulating film 7,
A mold channel stopper region 6 is formed. After that, the silicon nitride ml y film 4o is removed, and then the silicon oxide film 3
A. The portions of the RI-type well region 3 and the P-type well region 5 that are not covered with the field insulating film 7 are exposed. After this, the ri-mi type well 3 and the p-
The surface portion of the mold well region 5 exposed from the field insulating film 7 is thermally oxidized to form a thin silicon oxide film (gate insulating film) 10. Next, a polycrystalline silicon film 11A (FIG. 15) is formed by, for example, CVD, and a high melting point metal silicide film 11B, such as a tungsten silicide film (FIG. 15), is further formed thereon. 11B and the polycrystalline silicon film 11A are patterned by etching using a resist film.
As shown in the figure, a gate electrode 11 is formed. After this,
Remove the resist film used for patterning. next.

n° type semiconductor region 8A and n° type collector extraction layer 8
After forming a resist film 42 (FIG. 16) as a mask for ion implantation to form B, an n-type impurity such as phosphorus or arsenic is introduced into a predetermined portion of the surface of the π-type well region 3 by ion implantation. , as shown in FIG. 16, n' type semiconductor regions 8A and n.

A mold collector drawing layer 8B is formed. After this, the resist film 42 is removed. At this stage, the r+7 type semiconductor region 8A and the n' type collector extraction layer 8B are shallow and n
It does not reach the ° type buried layer 2A. Thereafter, each of the n° type semiconductor region 8A and the 11" type collector extraction layer 8B is thermally diffused to reach the n° type buried layer 2A. The n° type semiconductor region 8A reaches the n" type buried layer 2A. As a result, the n-type well region 3, which was provided continuously from region A to region B, is now connected to the a-type well region 3A and n-type well region 3
- type well region 3B. Next, area C
After covering the exposed portion with a resist film, the N-channel MI
In order to form a π-type semiconductor region 16A that is part of the source and drain of S F E TQnl, an n-type impurity such as arsenic is introduced by ion implantation. Next, after removing the resist film, a new resist film is formed to cover a portion of region A other than the portion where the base 13A is formed, and then an n-type impurity such as boron is added to form the base region 13A. will be introduced. Thereafter, the resist film is removed, and then annealing is performed to diffuse the n-type impurity and the n-type impurity, thereby forming a p-type base region 13A in region A, as shown in FIG. , the source is in area C,
A π-type semiconductor region 16A, which is a part of the drain, is formed. next.

For example, a silicon oxide film is formed by CVD, and this is etched back by reactive ion etching to form the sidewall 1.
2 (Fig. 18). Next, emitter 1 of area A
4A and a resist covering the parts other than the region C] - form a film, and then ion implant an n-type impurity, such as arsenic, to the part of the base 13A of the region A where the emitter 14A is to be formed; It is introduced into the portion where the n' type semiconductor region 15A, which is part of the source and drain of region C, is provided. Thereafter, the resist film is removed and annealed to form an n'' type emitter 14A in region A, as shown in FIG.
is formed, and in region C there is n, which is part of the source and drain.
A type semiconductor region 15A is formed. After this, as shown in FIG. 19, the first layer passivation film 20, the connection hole 21. Wiring 10 made of the first layer of aluminum 11 film
0. Second layer passivation film 22. Wires 200 each made of a second layer aluminum film are formed.

Note that each of the n° type semiconductor region 8B, the ri' type buried layer 2A, and the ri-type collector 3B of the bipolar transistor BiP1, and the P channel MISFET Qpl
The π-type well region 3A in which the π-type well region 3A is provided and the n°-type buried layer 2A thereunder need only be kept at the power supply potential V ca , so they are bipolar!・The transistor BiP1 is n
°-type collector pull-out layer 8B.

By applying a power supply potential Vcc to each of the n-type buried layer 2A and the n-type collector 3B, and applying a potential higher than the power supply potential Vcc to the n-type emitter 14A, the n-type collector extraction layer 8B, Ni type embedded viewing layer 2A
, it is also possible to operate the n-type collector 3B as an emitter and the n-type emitter 14A as a collector.

As described above, according to this embodiment, the bipolar transistor BiP1 is provided on the semiconductor substrate 1, and the bipolar transistor 13 i P of the semiconductor substrate 1
In a semiconductor integrated circuit device in which a well region 3A of a conductivity type opposite to that of the semiconductor substrate 1 is provided in a portion away from the semiconductor substrate 1, A continuous first semiconductor region (n-type well region 3) extends from the provided well region 3A to the collector 3B or emitter (3B) of the bipolar transistor BiP, and the bipolar transistor BiP of the first semiconductor region Between the transistor BiPl and the MISFET Qpl, a first semiconductor region having the same conductivity type as the first semiconductor region (n-type well region 3) and
By providing the second semiconductor region 8A, which has a higher impurity concentration than the semiconductor region and is deep enough to reach almost the bottom of the first semiconductor region, the collector 3B or emitter (3B) is always at the same potential as the well region 3A. In the bipolar transistor BiP1 to which the voltage is applied, electrical isolation between the bipolar transistor BiPl and the well region 3A is provided in a second semiconductor region 8A with a high impurity concentration provided between the bipolar transistor BiP1 and the MISFETQpl. This is done by applying the potential (Vcc). That is, the collector 3B or emitter (3B) of the bipolar transistor BiPl or the semiconductor region (n
' type semiconductor region 4 and p- type well region 5)-S- are carried out without intervening. In this way, since no semiconductor region for electrical isolation is provided between the collector or emitter and the well region to which the same potential is applied, the degree of integration of the semicircular integrated circuit device can be improved. .

Further, the first (n-type well region 3) and the second semiconductor region (ri'-type semiconductor region 8A) are used as bases, and the p-type source and drain 9 of the MISFET Qpl provided in the well 3A region are used as emitters to prevent parasitic Although a bipolar transistor is constructed.

Since the impurity concentration of the second semiconductor region 8A, which is the base of the parasitic bipolar transistor, is high, the minority carriers (holes) of the parasitic bipolar transistor can be eliminated in a short time. As a result, the parasitic bipolar transistor does not operate, so that the occurrence of latch-up can be reduced.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, in the above embodiment, in the transistor BiP1 and the P-channel MISFET Qpl, the [L'' type buried layer 2A is provided up to the bottom of the r'' type well region 3A in which the P-channel MISFETQp1 is provided. However, an n° type semiconductor region 8A is provided in contact with the side surface of the π type well region 2A.

Since the F-portion power supply potential Vcc can be supplied to the n-type well region 3A through this rI'' type semiconductor region 8A, the rl' type buried layer 2A is connected to the transistor BiPl.
It may be provided only in the region and not provided under the n-type well region 3A. In this case, n-type well region 3
It is desirable to provide the n'-type semiconductor region 8A so as to surround the entire circumference of A.

Further, in the embodiment, the collector is an NPN bipolar transistor connected to the power supply potential VcC.

We have described the element isolation technology between the π-type well regions where the P-channel MISFET is provided, and the PNP bipolar transistor whose collector is connected to the ground potential Vss and the N-channel MISFET are provided. It is also possible to apply it to element isolation technology between a P-type well region and a P-type well region. In this case, the semiconductor substrate 1 is n-type, the buried layer 2A is p° type, the collector 3B is p-type, and the base 13
A is of n type, emitter 14A is of p° type, and collector lead-out layer 8B is of p' type. In addition, the n-type well region 3A in which the P-channel MISFET QpL was provided in the embodiment described above is made p-type, and an N-channel MISFET is provided therein.

In addition, in the above embodiment, the power supply potential ■ is applied to the n-type well region 3A.
The n° type semiconductor region 8A to which cc was supplied is p.

Make it into a mold. Then, the p° type semiconductor region 8A is always supplied with the ground potential Vss, for example, 0■, and the p° type semiconductor region 8A is
Element isolation is performed between the - type well region 3A and the P N I) bipolar transistor.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

Instead of providing an element isolation region between the well region to which the same potential is applied and the collector or emitter, a single continuous semiconductor region is constructed from the well region to the collector or emitter, and this is a semiconductor region with a high degree of impurity. Since element isolation is performed by applying a predetermined potential through the semiconductor region, the distance between the bipolar transistor and the well region is reduced, and the degree of integration of the semiconductor integrated circuit device can be improved.

Further, a parasitic bipolar transistor is formed using the first and second semiconductor regions as a base and the source and drain of the MISFET provided in the well region as emitters, and the parasitic bipolar transistor is formed as a base of the parasitic pibora transistor. Since the impurity concentration in the second semiconductor region is high, the minority carriers of the parasitic bipolar 1-transistor can be eliminated in a short time. As a result, the parasitic bipolar transistor 1 to the transistor do not operate, so that the occurrence of latch-up can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a plan view of essential parts of a semiconductor integrated circuit device according to an embodiment of the present invention. 2 is a plan view of the main parts of the semiconductor integrated circuit device shown in FIG. 1, excluding the wiring on the semiconductor substrate. FIG. 3 is a plan view of the main parts of the semiconductor integrated circuit device shown in FIG. FIG. 4 is a sectional view taken along the line IV-IV of the main part of the semiconductor integrated circuit device shown in FIG. 1; 5 is a cross-sectional view of the main part of the semiconductor integrated circuit device shown in FIG. Sectional view taken along the VI section line. FIG. 7 is an equivalent circuit diagram of a main part of the semiconductor integrated circuit device shown in FIG. 1. 8 to 19 are diagrams for explaining a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, 1... semiconductor substrate, 2A, 2B... n' type buried layer, 3 A, 313 r 3 C-n- type region,
4...p° type region 5...p-type region, 6...p type channel stopper region, 7...field insulating film, 8A...
・11′ type semiconductor region, 8B, 8C...RF type collector extraction layer, 9...p°° source, 1 to rain, 13
A, 13B...p type base. 14A, 14B...11'' type emitter, 15A,
15B, 15C・r1° type region (source, part of 1 to rain), 16A, 16[3,16C...ri-
Type area (source, part of train). Agent Attorney J: Autumn 1fl Shuki

Claims (1)

[Claims] 1. A bipolar transistor is provided on a semiconductor substrate, and a well region of a conductivity type opposite to that of the semiconductor substrate is provided in a portion of the semiconductor substrate remote from the bipolar transistor,
In a semiconductor integrated circuit device in which a MISFET is provided on a surface portion of the well region, the well region in which the MISFET is provided to the collector or emitter of the bipolar transistor is constituted by one continuous first semiconductor region, and A first semiconductor region having the same conductivity type as the first semiconductor region and having a higher impurity concentration than the first semiconductor region is provided between the bipolar transistor and the MISFET in the semiconductor region.
A semiconductor integrated circuit device comprising a second semiconductor region having a depth reaching from the surface of the semiconductor region to almost the bottom of the semiconductor region. 2. The semiconductor integrated circuit device according to claim 1, wherein a predetermined potential is applied to the first semiconductor region through the second semiconductor region. 3. The semiconductor integrated circuit device according to claim 1, wherein the same potential as that of the well region is applied to the collector or emitter.