JPH01248530A - Structure for interconnecting semiconductor chip - Google Patents

Structure for interconnecting semiconductor chip

Info

Publication number
JPH01248530A
JPH01248530A JP63074380A JP7438088A JPH01248530A JP H01248530 A JPH01248530 A JP H01248530A JP 63074380 A JP63074380 A JP 63074380A JP 7438088 A JP7438088 A JP 7438088A JP H01248530 A JPH01248530 A JP H01248530A
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip
electrode
respect
connection structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63074380A
Other languages
Japanese (ja)
Inventor
Mitsuo Matsuyama
光男 松山
Kazumasa Arai
新井　和正
Michio Iizuka
飯塚　道雄
Junji Hayakawa
順二 早川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP63074380A priority Critical patent/JPH01248530A/en
Publication of JPH01248530A publication Critical patent/JPH01248530A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the thickness of a structure for interconnecting a semiconductor chip by forming each of electrode forming parts within the semiconductor chip with a surface which is inclined with respect to the rear of the semiconductor chip. CONSTITUTION:Each of electrode parts of a semiconductor chip 1 is formed so that its surface is inclined with respect to the rear of the chip by an anisotropy etching or other means at the formation of the chip. An electrode of the semiconductor chip 1 is connected to an electrode part of a lead frame 3 formed on the surface inclined with respect to the rear of the semiconductor chip 1 by a bonding wire 5. Accordingly, it is possible to reduce the maximum height a of the wire and the thickness between the upper end of a sealing cap 4 and the lower end of a holding plate 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体チップ接続構造に係り、特に上記構造の
必要高を削減し、上記構造を有する半導体装置の厚さの
低減に好適な半導体チップ接続構造に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor chip connection structure, and in particular to a semiconductor chip suitable for reducing the required height of the above structure and reducing the thickness of a semiconductor device having the above structure. Regarding connection structure.

〔従来の技術〕[Conventional technology]

従来の装置については、特開昭５３−４５１７４号公報
において論じられている。しかし、第２図において疎水
性樹脂６の上端と下端の有効厚さの低減を図る場合につ
い又は、１，２，５．６の厚さ低減が考えられるが、５
Ｖｒつい１は半導体チップの電極部とリードフレームの
電極部が平行面であるために、各々の宵、極間全接続す
るボンティングワイヤはＭ線で接続することは不可能で
ある。したがって上記ワイヤは半導体チップ表面の高さ
を越える弓形状となり、ワイヤの最大高さの低減に制約
があった。即ち疎水性樹脂６の全体の厚さ低減を制約す
る。A conventional device is discussed in Japanese Patent Application Laid-Open No. 53-45174. However, in the case of reducing the effective thickness of the upper and lower ends of the hydrophobic resin 6 in FIG. 2, it is possible to reduce the thickness by 1, 2, or 5.6.
Regarding Vr 1, since the electrode portion of the semiconductor chip and the electrode portion of the lead frame are parallel planes, it is impossible to connect the bonding wire that connects all the electrodes each evening with the M wire. Therefore, the wire has an arcuate shape that exceeds the height of the semiconductor chip surface, and there are restrictions on reducing the maximum height of the wire. In other words, the reduction in the overall thickness of the hydrophobic resin 6 is restricted.

〔発明が解決しようとする課電〕[Charging that the invention attempts to solve]

上記従来技術は半導体装置とし℃の部品高の低減に対す
る配慮がされてどうす、厚さの低減に制約があった〇 本発明の目的は、厚みを低減した半導体チップ接続構造
を提供することＶＣある。Although the above-mentioned conventional technology takes into account the reduction of the component height of semiconductor devices, there are restrictions on the reduction of thickness.An object of the present invention is to provide a semiconductor chip connection structure with reduced thickness.VC be.

〔線端を解決するための手段り 上記目的は半導体チップ接続構造に２いて、半導体チッ
プ内の電極形成部を該半導体チップの裏面に対して傾斜
をもたせた面に形成することにより、達成される。[Means for solving line ends] The above object is achieved by forming the electrode forming portion in the semiconductor chip on a surface inclined with respect to the back surface of the semiconductor chip in the semiconductor chip connection structure. Ru.

〔作用〕[Effect]

半導体チップの第１の電極部を該チップの裏面に対して
傾斜をもたせた面に設置すれば、上記第１の電極部の高
さは、従来の、半導体チップの裏面と平行面を成す半導
体チップの表面と同一平面に電極部が形成される場合に
比べ、低くできる。If the first electrode portion of the semiconductor chip is installed on a surface inclined with respect to the back surface of the chip, the height of the first electrode portion is lower than that of a conventional semiconductor chip that is parallel to the back surface of the semiconductor chip. It can be made lower than when the electrode portion is formed on the same plane as the surface of the chip.

したがって、上記第１の電極部と前記半導体チップの周
囲に形成した第２の電極部の間をワイヤボンディング接
続すると、該第２の電極部が第１の電極部の高さと同程
度とする構成とすれば、前記ワイヤボンディングの最大
高さを従来より低減することができる。即ち、半導体チ
ップ接続構造の必要高を従来より低減できる。Therefore, when the first electrode part and the second electrode part formed around the semiconductor chip are connected by wire bonding, the height of the second electrode part is approximately the same as that of the first electrode part. If so, the maximum height of the wire bonding can be reduced compared to the conventional case. That is, the required height of the semiconductor chip connection structure can be reduced compared to the conventional structure.

〔実施例〕〔Example〕

以下、本発明の実施例を第１〜第５図により説明する。 Embodiments of the present invention will be described below with reference to FIGS. 1 to 5.

第１図は本発明の第１の実施例を示す半導体チップ接続
構造の断面図である。この図において１は半導体チップ
、２は保持板、３はり７ドフレーム、４は封止キャップ
である。半導体チップ１は電極部を、チップ形成時に異
方性エツチング等によって該チップの裏面に対して傾斜
をもたせた面に形成しである。FIG. 1 is a sectional view of a semiconductor chip connection structure showing a first embodiment of the present invention. In this figure, 1 is a semiconductor chip, 2 is a holding plate, 3 is a beam 7 frame, and 4 is a sealing cap. The semiconductor chip 1 has electrode portions formed on a surface inclined with respect to the back surface of the chip by anisotropic etching or the like during chip formation.

一方、半導体チップ１の電極は、ボンディングワイヤ５
によって半導体チップ１の裏面に対して傾斜をもたせた
面に形成したリードフレーム３の電極部に接続する。ａ
は保持板２からボンディングワイヤ５へのワイヤの最大
高さである。第２図は第１図に対する従来の半導体チッ
プ接続構造の断面図である。第１図と同一の部品は、同
符号で示す。６は半導体チップ、７はリードフレームで
、各々の電極部は該チップの表面と平行となる面に形成
しである。ａ′は保持板２からボンディングワイヤ５へ
のワイヤの最大高さである。第２図々示の従来例では、
ボンディングワイヤ５は半導体チップ６の電極部から該
チップの表面の高さを越える弓形状で、リードフレーム
７へ接続される。しかしながら本発明に係る第１図の実
施・例においては電極部を半導体チップ１の裏面に対し
て傾斜をもたせた面に形成したので、ボンディングワイ
ヤ５の接続開始点を従来よりも低くできる。したがりて
、第１図のワイヤの最大高さａは第２図のワイヤの最大
高さａ′に比べ低くでき、封止キャップ４の上漏から保
持板２の下端までの厚さを従来よりも薄くできる。On the other hand, the electrode of the semiconductor chip 1 is connected to the bonding wire 5
The lead frame 3 is connected to an electrode portion of the lead frame 3 formed on a surface inclined with respect to the back surface of the semiconductor chip 1. a
is the maximum height of the wire from the holding plate 2 to the bonding wire 5. FIG. 2 is a sectional view of a conventional semiconductor chip connection structure with respect to FIG. 1. Components that are the same as in FIG. 1 are designated by the same reference numerals. 6 is a semiconductor chip, 7 is a lead frame, and each electrode portion is formed on a surface parallel to the surface of the chip. a' is the maximum height of the wire from the holding plate 2 to the bonding wire 5. In the conventional example shown in Figure 2,
The bonding wire 5 is connected from the electrode portion of the semiconductor chip 6 to the lead frame 7 in a bow shape exceeding the height of the surface of the chip. However, in the embodiment shown in FIG. 1 according to the present invention, the electrode portion is formed on a surface inclined with respect to the back surface of the semiconductor chip 1, so that the connection starting point of the bonding wire 5 can be lowered than in the conventional case. Therefore, the maximum height a of the wire in FIG. 1 can be made lower than the maximum height a' of the wire in FIG. Can be made thinner than

即ち、半導体装置の厚さ低減を期待できる。In other words, a reduction in the thickness of the semiconductor device can be expected.

第３図は第１図に示す実施例の半導体チップ形状を変え
た断面図であり、本発明の第２の実施例である。１００
は半導体チップで、電極部のみならず、チップの表面全
体を該チップの裏面に対して傾斜をもたせた面とした。FIG. 3 is a cross-sectional view of the embodiment shown in FIG. 1 with a different shape of the semiconductor chip, and is a second embodiment of the present invention. 100
is a semiconductor chip in which not only the electrode portion but also the entire surface of the chip is inclined with respect to the back surface of the chip.

これにより第１図同様の効果を期待できることは明らか
であり、さらに半導体チップの素子形成に関わる表面積
を増大するようにチップ表面を形成しであるので、チッ
プサイズを低減できる可能性があり、経済化が期待でき
る。It is clear that the same effect as shown in Figure 1 can be expected by this method, and since the chip surface is formed to increase the surface area involved in forming the elements of the semiconductor chip, there is a possibility of reducing the chip size, making it economical. We can expect it to change.

第４図は本発明の第３の実施例を示すフリップチップ型
の半導体チップ接続構造の断面図である。FIG. 4 is a sectional view of a flip-chip type semiconductor chip connection structure showing a third embodiment of the present invention.

この図において半導体チップ１０の電極は保持板２０上
面の印刷導体９による電極部にハンダボール８を介して
フェイスダウンボンディングされている。該チップの電
極部は該チップの裏面に対して傾斜をもたせた面となる
ように形成しである。−方上記印刷導体９の他端は、リ
ードフレーム３０に接続しである。４０は封止キャップ
である。ｈは半導体チップ１０の表面と保持板２０の上
面とのギャップである。一方、第５図は従来のフリップ
チップ型半導体装置の半導体チップ接続構造の断面図で
ある。第４図と同一部品は、同符号で示す。６０は半導
体チップである。該チップの電極部は該チップの裏面と
平行面上に形成しである。ｈ′は半導体チップ６０の表
面と保持板２０の上面とのギャップである。第５図図示
の従来例ではギャップｈ′はハンダボール８の有効高さ
より低くはならない。しかしながら本発明に係る第４図
の実施例においてはボンディング部を半導体チップ１０
の裏面に対して傾斜をもたせた面に形成したのでギャッ
プｈを従来よりも低くできる。故に第４図におけるギャ
ップｈは第５図におけるギャップｈ′よりも低くなり封
止キャップ４０の止痛から保持板２０の下端までの厚さ
は従来よりも薄くできるため半導体装置の厚、さ低減を
期待できる。In this figure, the electrodes of the semiconductor chip 10 are face-down bonded to electrode portions formed by printed conductors 9 on the upper surface of a holding plate 20 via solder balls 8. The electrode portion of the chip is formed to have a sloped surface with respect to the back surface of the chip. - The other end of the printed conductor 9 is connected to the lead frame 30. 40 is a sealing cap. h is the gap between the surface of the semiconductor chip 10 and the upper surface of the holding plate 20. On the other hand, FIG. 5 is a cross-sectional view of a semiconductor chip connection structure of a conventional flip-chip type semiconductor device. Components that are the same as those in FIG. 4 are designated by the same reference numerals. 60 is a semiconductor chip. The electrode portion of the chip is formed on a surface parallel to the back surface of the chip. h' is the gap between the surface of the semiconductor chip 60 and the upper surface of the holding plate 20. In the conventional example shown in FIG. 5, the gap h' is not lower than the effective height of the solder ball 8. However, in the embodiment of FIG. 4 according to the present invention, the bonding portion is connected to the semiconductor chip 10.
Since it is formed on a surface that is inclined with respect to the back surface, the gap h can be made lower than before. Therefore, the gap h in FIG. 4 is lower than the gap h' in FIG. 5, and the thickness from the sealing cap 40 to the lower end of the retaining plate 20 can be made thinner than before, so that the thickness of the semiconductor device can be reduced. You can expect it.

なお、電極を設置する傾斜をもたせた面と、該チップ内
の素子形成面との境界部分におけるチップ内配線層は拡
散による低抵抗層に置き換えることもできる。Note that the in-chip wiring layer at the boundary between the sloped surface on which the electrode is disposed and the element formation surface in the chip can be replaced with a low-resistance layer formed by diffusion.

また、本発明における半導体チップ接続構造は厚膜半導
体基板、薄膜半導体基板における半導体チップ接続構造
にも適用できる。Furthermore, the semiconductor chip connection structure of the present invention can also be applied to semiconductor chip connection structures in thick film semiconductor substrates and thin film semiconductor substrates.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、半導体チップ接続構造において半導体
デツプの電極部もしくはチップ表面全体を該チップ裏面
に対して傾斜をもたせた面とすることにより、半導体装
置の部品高の低減、あるいは半導体チップの素子形成に
関わる表面積が増大できるので、半導体装置の厚さ低減
、および経済化の効果がある。According to the present invention, in a semiconductor chip connection structure, by making the electrode portion of the semiconductor depth or the entire chip surface inclined with respect to the back surface of the chip, the height of the components of the semiconductor device can be reduced, or the element height of the semiconductor chip can be reduced. Since the surface area involved in formation can be increased, there is an effect of reducing the thickness of the semiconductor device and making it more economical.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１の実施例を示す半導体チップ接続
構造の断面図、第２図は従来技術による半導体チップ接
続構造の断面図、第３図は第１図に示す実施例の半導体
チップ形状を変えた本発明の第２の実施例の断面図、第
４図は本発明の第３の実施例を示すフリップチップ形の
半導体チップ接続構造の断面図、第５図は従来技術によ
るフリップチップ形の半導体チップ接続構造の断面図で
ある。 ２．２０・・・保持板 ３　、７　、３０・・・リードフレーム４．４０・・・
封止キャップ ５・・・ボンディングワイヤ ８・・・ハンダボール ９・・・印刷導体 茎　１　図 １キ漕昌ネ乎、７ブ ′２゜べ宋千コトλ号と ４村二〜マフプ Ｓ、ホ゛ン子スンフ“ワ４ｖ 力　　２　　図 見　３　珂 ヱ　ｔ＋　口 （Ｏ 第　５　同FIG. 1 is a sectional view of a semiconductor chip connection structure showing a first embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor chip connection structure according to the prior art, and FIG. 3 is a semiconductor of the embodiment shown in FIG. FIG. 4 is a sectional view of a flip-chip type semiconductor chip connection structure showing a third embodiment of the present invention, and FIG. 5 is a cross-sectional view of a second embodiment of the present invention in which the chip shape is changed. FIG. 2 is a cross-sectional view of a flip-chip type semiconductor chip connection structure. 2.20... Holding plate 3, 7, 30... Lead frame 4.40...
Sealing cap 5...Bonding wire 8...Solder ball 9...Printed conductor stem 1 Figure 1. Honko Sunfu “wa 4v power 2 illustration 3 kaede t + mouth (O 5th same)

Claims (1)

【特許請求の範囲】[Claims] １、半導体チップと該半導体チップ内の第１の電極と該
電極に接続される接続材と該接続材に接続される第２の
電極から成る半導体チップ接続構造において、上記第１
の電極部を半導体チップ裏面に対して傾斜をもたせた面
に形成したことを特徴とする半導体チップ接続構造。1. In a semiconductor chip connection structure consisting of a semiconductor chip, a first electrode in the semiconductor chip, a connecting material connected to the electrode, and a second electrode connected to the connecting material, the first
A semiconductor chip connection structure characterized in that an electrode portion is formed on a surface inclined with respect to the back surface of the semiconductor chip.
JP63074380A 1988-03-30 1988-03-30 Structure for interconnecting semiconductor chip Pending JPH01248530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63074380A JPH01248530A (en) 1988-03-30 1988-03-30 Structure for interconnecting semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63074380A JPH01248530A (en) 1988-03-30 1988-03-30 Structure for interconnecting semiconductor chip

Publications (1)

Publication Number Publication Date
JPH01248530A true JPH01248530A (en) 1989-10-04

Family

ID=13545502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63074380A Pending JPH01248530A (en) 1988-03-30 1988-03-30 Structure for interconnecting semiconductor chip

Country Status (1)

Country Link
JP (1) JPH01248530A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011129960A (en) * 2011-03-30 2011-06-30 Mitsubishi Electric Corp Semiconductor mold package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011129960A (en) * 2011-03-30 2011-06-30 Mitsubishi Electric Corp Semiconductor mold package

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