JPH01251631A - Wafer - Google Patents

Abstract

PURPOSE:To reduce the irregularity of characteristics in a wafer surface, by forming a test circuit pattern and a dummy pattern, in a region where patterns are not yet formed. CONSTITUTION:On a wafer 1, main body chip circuit patterns 2 are repeatedly formed in the longitudinal and the horizontal directions in the manner in which scribe-lines 3 are made as boundaries on a semiconductor substrate. Further, in several parts of the wafer 1, a test circuit pattern 4 is formed in a region equivalent to or integer times the main chip circuit pattern 2. In the residual region where patterns are not yet formed, a dummy pattern 5 having the same size is formed. Since there are no regions where patterns are not yet formed, the irregularity of etching rate and impurity in the wafer surface caused by dry etching process, ion implantation process, etc., in the manufacturing of semiconductor device is reduce, and the uniformity of semiconductor device characteristics is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a wafer on which a plurality of body chip circuit patterns are formed.

2. Description of the Related Art In the manufacturing process of a conventional semiconductor device, a large number of semiconductor circuit chips are produced from one wafer, and therefore one semiconductor circuit pattern must be arranged. Additionally, test circuit patterns are generally placed at several locations within a wafer for purposes such as investigating characteristics.

An example in which a main chip circuit pattern and a test circuit pattern are formed on the same semiconductor substrate using a reduction projection exposure device (stepper) is explained with reference to FIG. A scribe lane 12 for dividing the semiconductor circuit chip is provided between zero circuit patterns and circuit patterns that are repeatedly formed in the vertical and horizontal directions according to the area.

When the test circuit patterns 13 are arranged and formed on the same semiconductor substrate, in order to match the scribe lanes 12, the test circuits are placed on the same head as the main chip circuit pattern 11 or an integral multiple thereof. It is necessary to arrange the patterns 13.

However, if the size of the test circuit pattern 13 does not match the size of an area that is the same as the main chip circuit pattern 11 or an integral multiple thereof, a non-patterned area 14 occurs in the above area.

In addition, an unformed region where a circuit pattern is not formed also occurs in the peripheral portion of the wafer. Furthermore, even in the main body chip circuit pattern area, there may be an unformed area where no main body chip circuit pattern is formed.

Problems to be Solved by the Invention Semiconductor devices are progressing toward higher integration and miniaturization of circuits. Along with this, there is a great need to minimize variations in element dimensions, transistor characteristics, etc. during the manufacturing process of semiconductor devices. Shikajinaka, ra,
When a circuit pattern is formed using the wafer map as described above, variations within the wafer surface increase due to the influence of the non-patterned region 14. For example, it has been confirmed that in the dry etching process, there is an increase in the variation in the etching rate within the wafer surface, and in the ion implantation process, there is an increase in the variation in the distribution of electrons within the wafer surface.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a wafer that can reduce the influence of unpatterned areas that occur during circuit pattern formation.

Means for Solving the Problems In order to solve the above problems, the present invention forms a dummy pattern in an area where no main circuit pattern is formed, where no main chip circuit pattern is formed, when forming a circuit pattern on a wafer. . Further, a test circuit pattern and a dummy pattern are formed in a pattern-unformed area defined by the main chip circuit pattern. Also,
A dummy pattern is formed in a pattern-unformed area existing around the array of a plurality of main body chip circuit patterns.

Effect: With the above configuration, there is no pattern-unformed area, so
In the process of manufacturing a semiconductor device, it is possible to reduce variations in the characteristics of the semiconductor device within the wafer surface caused by the influence of the non-patterned region.

Example Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a partial schematic diagram of a wafer showing an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a wafer, and on this wafer 1, a main chip circuit pattern 2 is repeatedly formed on a semiconductor substrate vertically and horizontally with a scribe lane 3 as a boundary, as in the conventional case. As shown in FIG. 1, a test circuit pattern 4 is formed in an area that is the same as the main chip circuit pattern 2 or an integral multiple thereof, and a dummy pattern 5 of the same size is formed in the remaining pattern-free area. is formed.

With the above configuration, there is no pattern-unformed area on the wafer 1, so variations in the etching rate and impurities within the wafer surface that occur during the dry etching process, ion implantation process, etc. in the semiconductor device manufacturing process are reduced, and the characteristics of the semiconductor device are reduced. uniformity is improved.

When the circuit pattern described above is formed on a semiconductor substrate using a stepper, it can be easily implemented by using the main circuit chip pattern 2 as the dummy pattern 5 and programming the pattern size and pattern coordinates. In addition, the mask to wafer size is 1:1.
Needless to say, the present invention can be carried out by using diexsion, 10 ximity, contact, X-ray methods, direct writing EB, and ion methods, and it is also possible to use a test circuit pattern as a dummy pattern.

Furthermore, the present invention can be applied to forming dummy patterns in areas around the wafer where no circuit patterns are formed, and similar effects can be achieved.

Furthermore, the present invention can also be applied to forming dummy patterns in locations where no main body chip circuit pattern is formed in the main body chip circuit pattern region, and similar effects can be achieved.

In addition to the effects of the invention, according to the present invention, since there is no unpatterned area on the wafer, manufacturing variations in the semiconductor device manufacturing process are reduced, and the uniformity of the characteristics of the semiconductor device is improved.
Manufacturing of minute semiconductor devices can be easily carried out.

[Brief explanation of the drawing]

FIG. 1 is a partial schematic diagram of a wafer showing an embodiment of the present invention;
FIG. 2 shows a partial schematic diagram of a conventional wafer. 1... Wafer, 2... Main chip circuit pattern, 3
...Scribe lane, 4...Test circuit pattern, 5...Dummy pattern. Illustrated agent Yoshihiro Morimoto! l°To one work 2--One main body push circuit/pattern 3--One-way guide one 4-11 Child entry return Ginog Kuunter 1-Return my part

Claims (1)

[Scope of Claims] 1. A wafer in which a plurality of main body chip circuit patterns are arranged and formed, and a dummy pattern is formed in a region where no main body chip circuit pattern is formed. 2. A wafer in which a plurality of main body chip circuit patterns are formed in an array, and a test circuit pattern and a dummy pattern are formed in a pattern-unformed area defined by the main body chip circuit patterns. 3. A wafer in which a plurality of main body chip circuit patterns are formed in an array, and a dummy pattern is formed in a pattern-free area existing around the array.