JPS63258042A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS63258042A JPS63258042A JP62093899A JP9389987A JPS63258042A JP S63258042 A JPS63258042 A JP S63258042A JP 62093899 A JP62093899 A JP 62093899A JP 9389987 A JP9389987 A JP 9389987A JP S63258042 A JPS63258042 A JP S63258042A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- rectangular
- transistor circuit
- circuit blocks
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体装置チップ表面
の電気回路パターンレイアウトに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to an electric circuit pattern layout on the surface of a semiconductor device chip.
従来、半導体装置表面の電気回路パターンは、矩形の領
域内に面積を最小にすべく入夛組んだ微細パターンが形
成してあった。又、電気回路をＲ−０Ｍ領域、ＲＡＭ領
域、ランダムロジック回路領域と分割してレイアウトす
る場合にも領域間の間隔を最小にすると同時に、領域の
形状は矩形に限らず、互いに入〕組んだ形状で構成して
あった。Conventionally, an electric circuit pattern on the surface of a semiconductor device has been formed with intricate fine patterns within a rectangular region in order to minimize the area. Also, when laying out an electrical circuit by dividing it into an R-0M area, a RAM area, and a random logic circuit area, the spacing between the areas should be minimized, and the shapes of the areas should not be limited to rectangular shapes, but should be arranged so that they do not fit into each other. It was made up of shapes.
前述の従来の半導体装置によれば、１個の半導体装置パ
ターンをウェハース上に焼きつけ転写する際、一括処理
しなければならず、縮小投影露光装置の１回の露光エリ
アを越えた面積の半導体装ｔＩｔ、ヲ製造することは不
可能であった。通常の縮小投影露光装置は、その系学系
の性質上解像度を向上させてより微細なパターンを形成
させようとすれば必然的に露光エリアが狭くなり、前記
の半纏体装置面積がさらに小さく制限されることになる
。According to the conventional semiconductor device described above, when one semiconductor device pattern is printed and transferred onto a wafer, it must be processed all at once. It was impossible to manufacture it. Due to the nature of the conventional reduction projection exposure system, in order to improve the resolution and form finer patterns, the exposure area will inevitably become narrower, and the area of the semi-integrated apparatus described above will be further reduced. will be done.
パターンの微細化とチップ面積の拡大は半導体装置の集
積度向上、即ち機能向上の点で重要な問題であるが、前
述し九理由により従来はその進歩が大きく制限されてい
念。The miniaturization of patterns and the expansion of chip area are important issues in terms of increasing the degree of integration and, in other words, improving the functionality of semiconductor devices, but the progress has been severely limited in the past due to the nine reasons mentioned above.
本発明の目的は、従来の半導体装置で発生していた半導
体装置チップ面積の制限を無くシ、かつ微細パターン化
をも可能にする半導体装置を提供するものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that eliminates the limitations on semiconductor device chip area that occur in conventional semiconductor devices and also allows fine patterning.
本発明の特徴は、矩形の半導体基板表面を、いずれかの
−辺に垂直でかつ矩形を横断する帯状領域で複数の矩形
領域に分割し、各々の矩形領域の中に所定のトランジス
タ回路ブロックを形成し、帯状領域を横断する複数の配
線パターンにより個々のトランジスタ回路ブロックを電
気的に接伏し、全回路ブロックの機能が複合されて１個
の半導体装置として機能することである。A feature of the present invention is that the surface of a rectangular semiconductor substrate is divided into a plurality of rectangular areas by a band-shaped area that is perpendicular to one of the sides and crosses the rectangle, and a predetermined transistor circuit block is placed in each rectangular area. The individual transistor circuit blocks are formed and electrically connected to each other by a plurality of wiring patterns that cross the strip area, and the functions of all the circuit blocks are combined to function as one semiconductor device.
次に本発明の実施例を図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.
第１図は、本発明の一実施例を説明するための半導体装
置の概略平面図である。FIG. 1 is a schematic plan view of a semiconductor device for explaining one embodiment of the present invention.
本発明の半導体装置は、矩形の半導体基板１表面が長辺
に垂直でかつ半導体基板ｌを横断する帯状領域２で２つ
の矩形領域に分割され、各々の矩形領域内に所定の白ン
ジスタ回路ブロック３゜４が形成され、帯状領域２を横
断する複数の配線パターン５により個々のトランジスタ
回路ブロック３，４を電気的に接続し、２つの回路ブロ
ックの機能が複合されて１個の半導体装置として機能す
る構造となっている。In the semiconductor device of the present invention, the surface of a rectangular semiconductor substrate 1 is divided into two rectangular regions by a strip region 2 that is perpendicular to the long side and crosses the semiconductor substrate 1, and a predetermined white transistor circuit block is arranged in each rectangular region. 3.4 is formed, and the individual transistor circuit blocks 3 and 4 are electrically connected by a plurality of wiring patterns 5 that cross the strip area 2, and the functions of the two circuit blocks are combined to form one semiconductor device. It has a functional structure.
以上説明した本発明の半導体装置であれば、その製造工
程に於いて、半導体装置チップ１個分を各ブロック毎２
回に分けてパターン焼きうけ転写することができ、結果
として半導体装置面積を縮小投影露光装置の１回の露光
エリアの２倍まで拡大することができる。尚％２つのブ
ロック間を接続する配線パターンは、各々のブロックの
配線パ ′ターン焼きつけ転写の際に、帯状領域まで
露光エリアを広げて焼きつけ転写すればよく、その位置
合せ余裕として、配線パターン巾を適当に大きくすれば
よい。以上述べ友ように、チップ面積の制限が無くなれ
ば、半導体装置の機能を大巾に向上させることができる
し、微細化の友めに露光エリアが小さくなっても、チッ
プ面積を小さくする必要がない。In the semiconductor device of the present invention as described above, in the manufacturing process, one semiconductor device chip is divided into two blocks for each block.
The pattern can be printed and transferred in several batches, and as a result, the area of the semiconductor device can be expanded to twice the exposure area of a reduction projection exposure apparatus in one batch. %The wiring pattern that connects two blocks can be printed by printing and transferring the wiring pattern of each block by expanding the exposure area to a band-shaped area. You just need to increase it appropriately. As mentioned above, if there were no restrictions on chip area, the functionality of semiconductor devices could be greatly improved, and even if the exposure area became smaller due to miniaturization, it would be necessary to reduce the chip area. do not have.
上述の実施例では、半導体装置表面を２分割した例で説
明し比が、３分割、４分割と分割数を大きくできること
は言うまでもない。In the above embodiment, the semiconductor device surface is divided into two parts, but it goes without saying that the ratio can be increased to three or four parts.
第１図は本発明の一実施例を説明するための半導体装置
の概略平面図である。
尚、図において、ｌ・・・・・・半導体基板、２・・・
・・・帯状領域、３．４・・・・・・トランジスタ回路
ブロック、５・・・・・・配線パターンである。
、ニジ−７・ｃ′FIG. 1 is a schematic plan view of a semiconductor device for explaining one embodiment of the present invention. In the figure, l...semiconductor substrate, 2...
. . . band-shaped region, 3. 4 . . . transistor circuit block, 5 . . . wiring pattern. , Niji-7・c'
Claims (1)
、所定の配線及び絶縁膜を付して電気回路を構成した半
導体装置において、矩形の半導体基板表面をいずれかの
一辺に垂直でかつ矩形を横断する帯状領域で複数の矩形
領域に分割し、各々の矩形領域の中に所定のトランジス
タ回路ブロックを形成し、帯状領域を横断する複数の配
線パターンにより個々のトランジスタ回路ブロックを電
気的に接続し、全回路ブロックの機能が複合されて１個
の半導体装置として機能することを特徴とする半導体装
置。In a semiconductor device in which a plurality of transistors are formed on the surface of a rectangular semiconductor substrate, and predetermined wiring and insulating films are attached to form an electric circuit, the surface of the rectangular semiconductor substrate is perpendicular to one side and crosses the rectangle. A strip area is divided into multiple rectangular areas, a predetermined transistor circuit block is formed in each rectangular area, and the individual transistor circuit blocks are electrically connected by multiple wiring patterns that cross the band area. A semiconductor device characterized in that the functions of circuit blocks are combined to function as a single semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62093899A JPS63258042A (en) | 1987-04-15 | 1987-04-15 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62093899A JPS63258042A (en) | 1987-04-15 | 1987-04-15 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63258042A true JPS63258042A (en) | 1988-10-25 |
Family
ID=14095328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62093899A Pending JPS63258042A (en) | 1987-04-15 | 1987-04-15 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63258042A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6725440B2 (en) | 2000-03-27 | 2004-04-20 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device comprising a plurality of semiconductor devices formed on a substrate |
| JP2016530704A (en) * | 2013-07-03 | 2016-09-29 | ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ | Monolithic integrated circuit die having modular die regions stitched together |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5779647A (en) * | 1980-11-05 | 1982-05-18 | Ricoh Co Ltd | Master slice chip |
| JPS5928359A (en) * | 1982-08-10 | 1984-02-15 | Nec Corp | Manufacture of integrated circuit device |
-
1987
- 1987-04-15 JP JP62093899A patent/JPS63258042A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5779647A (en) * | 1980-11-05 | 1982-05-18 | Ricoh Co Ltd | Master slice chip |
| JPS5928359A (en) * | 1982-08-10 | 1984-02-15 | Nec Corp | Manufacture of integrated circuit device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6725440B2 (en) | 2000-03-27 | 2004-04-20 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device comprising a plurality of semiconductor devices formed on a substrate |
| US6913989B2 (en) | 2000-03-27 | 2005-07-05 | Matsushita Electric Industrial Co., Ltd. | Method of exposing a semiconductor integrated circuit including device regions and global routing region |
| JP2016530704A (en) * | 2013-07-03 | 2016-09-29 | ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ | Monolithic integrated circuit die having modular die regions stitched together |
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