JPH01251920A - Sound outputting level controlling and converting system - Google Patents

Abstract

PURPOSE:To eliminate the necessity of a large-capacity memory even when the numbers of level converting stages and steps are large by making amplified or damped data obtainable when a memory for level conversion is accessed several times during one sample period by only storing two kinds of level converting data of (+) and (-) in the memory for level conversion. CONSTITUTION:The output data of a memory 2 for level conversion are temporarily stored in a register 4 and a selector 8 switches the data of the register 4 to the data of a date memory 1 and causes the data of the memory 1 to be inputted to the memory 2 for level conversion. Since the memory 2 stores two kinds of level converting date of (+) and (-), desired amplified or damped data are obtained when the memory 2 is accessed several times in accordance with the number of memory accessing times set by a setting section 6. Therefore, an increase in the storing capacity of the memory 2 for level conversion can be prevented even if the numbers of level converting stages and levels increase.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory-based audio output device, and particularly to a PC.
This relates to an audio output level conversion control method using M code.

(Prior Art) FIG. 4 shows an example of a conventional configuration of an output level conversion system using a PCM code in a device that outputs audio data stored in a memory as a PCM code.

In Figure 4, 11 is P of 8 bits per sample.
A data memory (M
EM), 12 is a level conversion memory (LVME) that stores level conversion data of 8-bit PCM code.
M), 13 is a memory control unit (MEMCONT) for sequentially reading data memory (MEM) 11 and level conversion memory (LVMEM) 12, 14 is 8-bit parallel output data of level conversion memory (LVMEM) 12. 15 is a shift register (SFR) that converts the data into serial 8-bit data.
FR) Highway interface unit (HWINF) that outputs 14 serial output data to the highway,
16 is 3-bit level conversion memory (LVMEM)
PCM for fixed addressing to l2.
This is a level conversion value setting unit (LVCONT) that sets a code level conversion value in advance.

FIG. 5 is a time chart showing an outline of the sequence of one sample period in the configuration of FIG. 4, and the operation of the system of FIG. 4 will be explained below with reference to this time chart.

First, data obtained by PCM-encoding an analog audio signal is synchronized with the sampling cycle, and is manually entered into the data memory (MEM) II as 8-bit data of DiO~7. ) and is written into the data memory (MEM) 11 under AD (address) control. Then, when the PCM code data stored in the data memory (MEM) 11 is output to the highway, the memory control unit (MEM)
The output level at the PCM code stage is changed by controlling the reading from the data memory (MEM) 11 and level conversion memory (LVMEM) 12 from the PCM code 13. In this case, the memory control unit (MEMCONT)
The read pulse RD is sent every sampling period from l3 to data memory (MEM) 11 and level conversion memory (
LVMEM) 12. Then, the data memory (MEM) 11 stores the PCM code data 8.
bit, and the output is stored in the level conversion memory (LV
MEM) I2 is input to lower addresses AO to 7. On the other hand, the level corresponding data to be converted is stored in the level conversion value setting unit (LVCONT) 16 in the level conversion memory (
LVMEM) 12 upper addresses 88 to IO are input manually. In this way, level conversion memory (LVMEM)
12 is the booter corresponding to the specified address 0UTO~
Outputs 8 bits to 7. Here, level conversion memory (L
An example of memory allocation for VMEM) 12 is shown in FIG. 6th
The example shown in the figure shows a case of level conversion in three stages and eight steps, and the level conversion memory (LEVMEM) 12 stores converted data corresponding to addresses. In this case, the memory capacity is 256 bytes per rubel, and 2048 bytes are required for 8 steps. Next, the shift register (SFR) 14 is transferred to the data memory (M
EM) 11 and level conversion memory (LVMEM) 1
At the falling edge of the read pulse RD in step 2, the level conversion memory (LVMEM) 12 (7) OUTO~7 (7) reads the data in parallel format, and shifts the shift memory control unit (M
EMCONT) 13, the highway interface unit (
)11fINF) Output to 15. The highway interface unit (HIIINF) 15 is a shift register (S
During the output time of the FR) 14, the output gate is gate-controlled by the gate signal GAT from the memory control unit (MEMCONT) 13, and the serial 8-bit data of the shift register (SFR) 14 is sequentially sent to the highway.

(Problems to be Solved by the Invention) However, the prior art described above has the following problems.

(2) As can be seen from the example in FIG. 6, when the number of level stages or steps to be converted increases, the memory capacity of the level conversion memory increases significantly.

(2) If a significant change in the conversion level occurs while the device is in operation, it is necessary to replace the memory or write to the memory.

The present invention eliminates the above-mentioned problems such as the need to prepare a large capacity memory when there are many level conversion steps, and minimizes the capacity of the level conversion memory. An object of the present invention is to provide an audio output level conversion control method that can increase the number of steps.

(Means for Solving the Problems) The present invention provides a data memory that stores audio data obtained by PCM encoding an analog audio signal, a level conversion memory that stores level conversion data of the PCM code, and a level conversion memory that stores the level conversion data of the PCM code, and An audio output device comprising a memory and a memory control unit that sequentially controls reading of the level conversion memory, and performs level conversion on the audio data when the audio data is a PCM code in order to obtain an appropriate audio level when reproducing the audio data. In order to solve the above-mentioned problems, a setting means for presetting a level conversion value and the number of accesses to the level conversion memory, and a register for storing output data of the level conversion memory are provided. and a selector disposed before the address input of the level conversion memory for switching between the output of the data memory and the output of the register, and a selector for switching between the output of the data memory and the output of the register. It is designed to store converted data.

(Operation) In the present invention, the register temporarily stores the output data of the level conversion memory. The selector switches between the data in the register and the data in the data memory, and manually inputs the level conversion memory. The level conversion memory stores two types of level conversion data: plus side and minus side. Therefore, by accessing the level conversion memory several times according to the number of memory accesses set by the setting circuit, desired amplified or attenuated data can be obtained. Moreover, even a large change in the conversion level can be dealt with simply by changing the setting of the number of accesses of the setting means, so that flexible measures can be taken and the above-mentioned problem can be solved.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 indicates a data memory (MEM) for storing 8-bit PCM-encoded audio data per sample; 2;
is a level conversion memory (LVMEM) that stores level conversion data of 8-bit PCM code, 3 is a data memory (MEM), 1 is a level conversion memory (LVMEM), and 3 is a data memory (MEM).
MEM) 2, memory control unit (MEM(:0NT)) for sequentially reading selector (SEL) 8 and flip-flop (F/F) 7, 4 &i Level conversion memory (LVMEM) 2 (08bit parallel output data 5 is a shift register (SFR) that converts the data into serial 8-bit data.
Highway interface unit (HWINF) that outputs the serial output data of FR) 4 to the highway,
6 is a level control unit (L) in which the PCM code level conversion value, level conversion memory, and number of accesses are set in advance;
V(:0NT), 7 is level conversion mesori (LVMEM)
) Flip-flop (F/F) for the register that temporarily stores 8-bit data from 2, 8 is data memory (MEM) 1 or 8-bit human power from flip-flop (F/F) 7 is transferred to the memory control unit (MEMCONT).
3, and is a switching selector (SEL) that outputs one side of the human power.

Next, the operation of the above embodiment will be explained with reference to FIGS. 2 and 3. FIG. 2 is a time chart showing an overview of a sequence in which level conversion is performed to +6 dB per sample in the configuration of FIG. 1 and output to the highway;
FIG. 3 is a diagram showing an example of memory allocation of the level conversion memory (LVMEM) 2, and is an example in the case of having conversion data of +3 dB.

First, data obtained by PCM encoding an analog audio signal is
The memory control unit (ME
AD (address) and WE (write) from MCONT) are manually stored in data memory (MEM) 1. When level-converting the audio data stored in this way and outputting it to the highway, the first read pulse RD is output by the memory control unit (MEM(:0NT) 3) as shown in the time chart of FIG. Hour selector (SEL) 8 is data memory (MEM) i
The PCM code data read from the data memory (MEM) 1 is selected in the direction of outputting the side input, and the PCM code data read from the data memory (MEM) 1 is stored at the lower address A of the level conversion memory (LVMEM) 2.
It will be O~7. On the other hand, at this time, the memory control unit (MEMCO)
Level conversion memory (LVMEM) output by NT) 3.
) 2 is "0", so the level conversion memory (LVMEM) 2 is 13 shown in FIG.
Outputs dB PCM code data to 0UTO-7. In this way, the output data 0UTO to 7 of the level conversion memory (LVMEM) 2 are set in the flip-flop (F/F) 7 at the falling edge of the read pulse RD, and the flip-flop (F/F) 7 is set to the The data converted to -3dB is output. Next, the memory control unit (MEMCONT) 3 switches the selector (SEL) 8 to the flip-flop (F/F) 7 side, and after setting the upper address 88 of the level conversion memory (LVMEM) 2 to “1”. , outputs the second read pulse RD. The lower address of the level conversion memory (LVMEM) 2 depends on the 3 dB data of ■■ in Figure 2, but since 88 is "1", the data of ■ in Figure 2 becomes OdB data, and the read pulse RD At the falling edge of , the flip-flop (F/F) 7 sets the de=re of (2) and outputs to DO~7 at the same time. Next, the memory control section (M
When the third read pulse RD from EMCONT) 3 is input to the level conversion memory (LVMEM) 2,
The lower address of level conversion memory (LVMEM) 2 is OdB data of ■, and the upper address 88 is ■
is “1”, so the level conversion memory (LVMEM
) 2 outputs the +3 dB converted data (2) to 0UTO-7, and at the falling edge of the read pulse RD, the flip-flop (F/F) 7 sets the data (2) and outputs it to DO-7 at the same time.

Next, the fourth read pulse RD from the warp control unit (MEM(:0NT) 3) is sent to the level conversion memory (LVMEM).
2. Level conversion memory (LVMEM)
The lower addresses AO to 7 of 2 are +3 dB data of ■, and the upper address 88 of ■ is "1", so level conversion memory (LVMEM) 2 accesses the +3 dB side memory, and after +6 dB conversion. Data is output to 0UTO-7. At the falling edge of the read pulse RD, the gate signal GAT is sent from the memory control unit (MEMCONT) 3 at the same time as it is set in the flip-flop (F/F) 7, so the data is transferred to the shift register (SFR) 4. is set to Shift register (SFR) 4 is memory control unit (MEM(:0NT)
8-bit 0IIT synchronized with clock CLK from 3
The parallel data of O to 7 is converted into serial data and sequentially output to the highway interface unit (HWINF) 5. Highway interface section (11WINF)
5 is a memory control unit (MEMII:0NT) which sends serial data to the highway while the gate signal GAT from 3 is being output. Thus data memory (MEM) 1
A converted PCM code amplified by +6 dB from the PCM code data read out is output to the highway. If you want to attenuate to the negative side, please use ■ in Figure 2.
By setting the 8th address input to "0", data attenuated by -6 dB can be output to the highway.

(Effects of the Invention) As described in detail above, according to the present invention, by simply storing two types of conversion data, 10 and -, in the level conversion memory, the level conversion memory can be used for one sample period. By accessing the data several times, it is possible to obtain amplified or attenuated data. Therefore, if a large change in the conversion level occurs while the device is in operation, it can be handled simply by changing the access count setting of the level conversion memory, and there is no need to rewrite the level conversion memory, which is economical. This has the effect of easily and flexibly responding to various level conversion values.

Furthermore, the present invention can be applied to a data processing device that increments or decrements input data with a fixed value width by storing a fixed value in a conversion memory.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing an example of memory allocation for level conversion memory in the system shown in FIG. 1, FIG. 4 is a block diagram showing an example of a conventional output level conversion system, and FIG. 4 is an operation time chart of the system shown in FIG. 4, and FIG. 6 is a diagram showing an example of memory allocation of the level conversion memory in FIG. 4. 1... Data memory (MEM) 2... Level conversion memory (LVMEM) 3... Memory control unit (MEMCONT) 4... Shift register (SFR) 5... Highway interface unit (HWINF) 6
...Level conversion value etc. setting section (LVCONT) 7...
Flip-flop (F/F) 8...Selector (SEL)

Claims (1)

[Scope of Claims] A data memory that stores audio data obtained by PCM-encoding an analog audio signal; a level conversion memory that stores PCM code level conversion data; the data memory and the level conversion memory. In an audio output device, the audio output device is equipped with a memory control unit that sequentially reads and controls the level conversion value and the level conversion value. a setting means for presetting the number of accesses to the conversion memory; a register for storing the output data of the level conversion memory; An audio output level conversion control method, comprising: a selector for switching output; and two types of level conversion data, one on a plus side and one on a minus side, are stored in the level conversion memory.