JPH0447867A - fade processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is used in video editing machines, etc., to gradually increase or decrease the level of video signals, etc., and to fade in/fade out ( fade in
The present invention relates to a fade processing device that performs a gradual increase or decrease using digital processing.

[Technology of the Invention] Conventionally, in the case of an analog type fade processing device of this kind, for example, a video signal or the like is passed through a sliding variable resistor (attenuator), and the fade processing device is processed by changing the value of the variable resistor. That is, by controlling the gain from 0% to 100%, the level of the signal is changed and the signals are mixed.

[Problems to be Solved by the Invention] The fade processing device uses a sliding variable resistor for fade-in and fade-out, so it is inexpensive. By the way, video editing machines and the like are increasingly being digitized, and the fade processing device mentioned above can now be implemented using digital arithmetic processing.

However, the above-mentioned fade processing device using digital calculations has a problem in that it has a complicated circuit configuration and is expensive compared to an analog one.

This invention was made in view of the above problems, and its purpose is to provide a fade processing device that can perform fade in/out using digital processing, has a small number of circuit parts, and can be manufactured at low cost. It is in.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a fade processing device that gradually increases or decreases the level of a video signal and enables fade-in and fade-out of the video. A memory that stores data that is gradually increased or decreased in accordance with the number of bits of the digital video data of the video signal, divided in advance into a plurality of areas sequentially starting from address O or the maximum address; ,
a microcomputer that outputs an upper address of the memory in response to a fade-out instruction and sequentially designates a plurality of areas of the memory each time V synchronization of the video signal is performed; This lower address and the upper address from the microcomputer are used to sequentially designate the plurality of areas at each V synchronization of the video signal, read out the data in the designated area, and output it as video data. The summary is what was done.

[Function] With the above configuration, if the input digital video data is 8 bits, for example, from address “0000” to “F
Divide the memory of "FFF" into 256 areas and write data that gradually increases or decreases in these 256 areas, that is, from address "0000" to "0OFF"
Write all (00) data in the area, increase the value of the data as the address increases,
Last area (address “FF0O” to “FFFF”)
(00), (01), (02),...
Write the data of (FE) and (FF),
Then, the input video data is transferred to the lower address of that memory (
The high-order address (8 bits) of the memory is output from the microcomputer, and the address from this microcomputer is updated every V synchronization of the video signal from which the video data is obtained. Then, at each V synchronization, data obtained by gradually increasing the input digital video data is obtained, and a fade-in effect is obtained.

In addition, a fade-out effect can be obtained by lowering the address from the microcomputer every time the V synchronization is performed, or by gradually reducing the data written in the memory in advance.

[Embodiments] Hereinafter, embodiments of the present invention will be described based on FIGS. 1 to 3.

In FIG. 1 and FIG. 2, the fade processing device includes:
Gradually increasing the video data corresponding to the number of bits (for example, 8 bits) of the digital video data of the video signal,
Alternatively, gradually decreasing data (e.g. 8 bits) can be stored at address 0 (e.g. oooo) or maximum address (e.g. FFF).
A memory unit (ROM; look-up table) 1 which sequentially stores data divided into multiple areas (for example, 256 areas) from F) and the upper address of the above memory is X (OOX
X, 0IXX, -, FEXX.

FFXX) and sequentially designates a plurality of areas of the memory every time V synchronization of the video signal is performed. In addition, the lower atto L/X (XXOO, XX0I, -, XXFE,
XXFF) is digital video data of the video signal.

Furthermore, when the memory unit 1 is divided into 256 areas, for example, data (00) is written in one area (data (1)) from address (oooo) to (OOFF), and the address is large. Gradually increasing data is written in the area, starting from address (FFOO) to (F
FFF) no 1 area (data (256) ) d is (00
).

(01), (02),..., (FD), (FE), (
FF) data has been written.

Next, the operation of the fade processing device having the above configuration will be explained with reference to a third time chart.

First, a video signal, etc. is converted into digital data, and digital video data is obtained.
n) It is assumed that an instruction to do so has been input.

Then, as shown in FIGS. 3(a) and 3(b), the microcomputer 2 outputs the upper address of the memory unit 1 every time the video signal, etc. is synchronized.

At this time, the upper addresses are (OO), (01),
(02),..., (F D), (F E), (F F
), and 256 areas of the memory unit 1 are sequentially specified for each V synchronization. On the other hand, the lower address of the memory section 1 is the digital video data of the video signal.

Therefore, when the upper address is (00) in the first V synchronization, one of the addresses (oooo) to (OOFF) can be obtained depending on the input digital video data (8-bit data), and this address can be used to access the memory section 1. The data in data (1) is read out and output as video data.

At this time, the data (1) area has, for example, (00)
Since only the data of 1 is written, the output video data becomes (00) regardless of the input digital video data. Then, at the next V synchronization, the above address becomes (01), and the input digital video data (8 Depending on the bit data), one of addresses (0100) to (OIFF) is obtained, and the data in data (2) of the memory section 1 is read out at this address and output as video data.

At this time, the data (2) area is filled with the data (1).
) area data gradually increased, for example, address (OIFF) is set to (01) and other addresses are set to (00).
Since data has been written, video data of (01) is output only when the input digital video data is (FF).

Similar processing is executed thereafter, and the upper address becomes (FF) at the 256th V synchronization, and one of the addresses from (FFOO) to (FFFF) is obtained depending on the input digital video data (8-bit data). At this address, the data in the data (256) of the memory section 1 is read out and output as video data. At this time, the data (25
6) The area contains data that gradually increases the data in the data (255) area, that is, from address (FFOO) to (FFFF).
F) 4. Since the knee has data written from (00) to (FF), the same data as the input digital video data is output.

In this way, the memory unit 1 is divided into a plurality of areas, data that gradually increases is stored in the plurality of areas, and the plurality of areas are divided by upper addresses, and the upper addresses are changed every time V synchronization of the video signal is performed. At the same time, the input digital video data is set to the lower address of the memory section 1, so the data that gradually increases is read out every time V synchronization is performed.
Since it is used as video data, fade-in video data can be obtained, and since only the memory section 1 and microcomputer 2 are required, the circuit configuration is simple and can be done at low cost.

In the above embodiment, a fade-in operation has been described, but if the upper address output from the microcomputer 2 is changed from (FF) to (00), a fade-out is possible.

In addition, data (1) to (256) in memory unit 1 include:
Although data that has gradually increased is stored, data that has gradually decreased can be stored in a similar manner to achieve fade-out and fade-in operations.

[Effects of the Invention] As explained above, according to the fade processing device of the present invention, data that gradually increases or decreases corresponding to the number of bits of digital video data of the video signal is stored at address O or at the maximum address. The memory is stored sequentially in multiple areas starting from the address, and the upper address of the memory is output according to the above fade-in and fade-out instructions. Equipped with a microcomputer that sequentially specifies multiple areas,
The digital video data of the video signal is set as the lower address of the memory, and the multiple areas are sequentially specified every V synchronization of the video signal using this lower address and the upper address from the microcomputer. Input and output can be performed by digital processing, and a simple circuit configuration is required, resulting in cost reduction.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a fade processing device showing an embodiment of the present invention, FIG. 2 is a schematic diagram of a memory used in the fade processing device, and FIG. 3 explains the operation of the fade processing device. FIG. In the figure, 1 is a memory unit (ROM) and 2 is a microcomputer. Patent applicant: Fujitsu General Co., Ltd. Agent: Patent attorney: Takuya Ohara

Claims (1)

[Claims] (1) In a fade processing device that gradually increases or gradually decreases the level of a video signal and makes it possible to fade in and fade out the video, the level of the video signal gradually increases in accordance with the number of bits of digital video data of the video signal, Or a memory that stores gradually decreasing data in advance in multiple areas sequentially starting from address 0 or the maximum address,
a microcomputer that outputs an upper address of the memory in response to the fade-in and fade-out instructions, and sequentially specifies a plurality of areas of the memory for each V synchronization of the video signal; The video data is set as a lower address of the memory, the lower address and the upper address from the microcomputer are used to sequentially designate the plurality of areas for each V synchronization of the video signal, read out the data in the designated area, and read out the video data. A fade processing device characterized in that it outputs as follows.