JPH01252013A - Automatic gain adjusting circuit - Google Patents

Abstract

PURPOSE:To easily execute gain setting from an external part, to correspond to signal synchronization and to execute optimum gain adjustment by controlling the opening and closing of a switch with a switch control means, which equips a counter to add and subtract a computing value in correspondence to a signal level, changing a resist value by stages to a feed-back circuit according to this opening and closing and adjusting an amplifying gain. CONSTITUTION:A resistor circuit 28 to be composed of plural resistors R1-R32 is arranged to a feed-back circuit 26 of an amplifier 22 in an automatic gain adjusting circuit and the resistance of the feed-back circuit 26, which is set between the arbitrary resistor of this circuit 28 and the amplifier 22, is selected by switches S1-S10. As a basic data preparing means to change over these switches S1-S10, an up-down counter 412 is arranged in a switch control part 40 and basic data to a decoder matrix 401 are outputted from this counter 412. In correspondence to the computing value of the counter 214, the opening and closing of the switches S1-S10 is controlled and the resistors R1-R32 to be set in the feed-back circuit 26 is switched by stages.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic gain adjustment circuit suitable for gain adjustment in servo system signal processing of a video tape recorder.

[Conventional technology]

FIG. 4 shows a capstan servo system of a general video tape recorder. A control signal (CTL signal) is detected from the magnetic tape 4 traveling by the rotation of the capstan motor 2 through the magnetic head 6, and an FG multiplied signal detected in conjunction with the FG coil 8, and a CPG signal through the frequency divider IO. is extracted as. These CTL signals and CPG signals are processed by an automatic gain adjustment circuit (AGC circuit)
12 and controlled to a constant level, it is applied to the phase servo circuit 14, from which a phase servo output is obtained. On the other hand, the FC signal is applied to the speed servo circuit 16, and based on the FG multiplied signal, the speed servo circuit 1
6 provides the speed servo output. A capstan drive output is obtained from the driver 18 by each servo output, the capstan motor 2 is controlled, and the running speed of the magnetic tape 4 is controlled to be constant.

[Problem to be solved by the invention]

By the way, in the AGC circuit installed in such a capstan servo system, conventionally, an amplifier is installed to amplify the CTL signal, and the detected signal obtained by performing absolute value detection or peak value detection on the output of this amplifier is used to power the amplifier. A linear method is used to control the gain.

In such an AGC circuit, it is difficult to set an arbitrary gain externally due to linear processing, and the signals handled are intermittent pulse signals, so the attack time and recovery time for signal level detection are difficult to set. Decision is A
There were drawbacks such as affecting GC performance.

Therefore, an object of the present invention is to realize arbitrary gain settings and to optimize gain control.

[Means to solve the problem]

The automatic gain adjustment circuit of the present invention includes, for example, as shown in FIG. 1, a resistor circuit 28 consisting of a plurality of resistors (resistors R, -R, □) installed in a feedback circuit 26 of an amplifier 22;
A resistor (resistance R) installed between any resistor (resistance R1-R3□) of this resistance circuit 28 and the amplifier 22 and installed in the feedback circuit 26.

~R3□), and a counter (up/down counter 412) that adds or subtracts depending on the output level of the amplifier 22, and switches (S+~S,...) according to the counted value. ), and a resistor (resistance Rl"" R3) installed in the feedback circuit 26.
□) is provided with a switch control means (switch control unit 40) for switching stepwise.

[Function] The feedback circuit 26 of the amplifier 22 includes a plurality of resistors (resistors R1 to
A resistor circuit 28 consisting of R3□) is installed, and the resistor circuit 2
Switches (S, .about.S, . . . ) are installed as means for selecting the resistances (resistors R8 to R3□) for the amplifier 22 from 8 to 8. Then, a switch control means (switch control unit 4
0) is installed, and the switch control means (switch control unit 4
0), the count value of the counter (up/down counter 412) is increased or decreased according to the output level of the amplifier 22, and the opening/closing of the switch (S+-3+) is controlled by the count value, so feedback is generated according to the output level. Feedback resistances are set in the circuit 26 in stages. By setting the resistance value in stages for the feedback circuit 26, the gain of the amplifier 22 is adjusted according to the output level, and an output of a partial level is taken out from the amplifier 22.

[Embodiment] FIG. 1 shows an embodiment of the automatic gain adjustment circuit of the present invention.

A magnetic head 6 is installed as a signal source, and the magnetic head 6 receives control (C) from the running magnetic tape 4.
TL) signal is reproduced. This CTL signal is a thin pulse having amplitude in the positive and negative directions, and is applied to the positive input side of the amplifier 22 through the input terminal 20.

The amplifier 22 is an amplification means whose gain is to be adjusted, and is composed of, for example, an operational amplifier.

Between the output section of this amplifier 22 and the negative input terminal 24,
A feedback circuit 26 is provided for gain setting. A resistor 30 and a capacitor 32 are installed in the feedback circuit 26 along with a resistor circuit 28 that is a combination of a plurality of resistors. Therefore, the gain adjustment of the amplifier 22 is performed by the resistor circuit 28.
and the feedback rate determined by the resistance value ratio of the resistor 30.

In the resistor circuit 28 of this embodiment, a series circuit of 32 resistors RI "" R32 each having the same resistance value is installed as a plurality of resistors. A plurality of switches S1, S2 are connected between the negative input side m of the resistor circuit 28 and each point a, b...j of the resistor circuit 28.
...Sl. is installed. Switch S l"'
S+. For example, when the switch S1 is closed, the resistor R1 is installed as a feedback element of the feedback circuit 26, and when the switch S2 is closed, the resistor R+ and a part of the resistor R2 are installed as feedback elements of the feedback circuit 26. If S, ~SIO is open, resistors R8~R3□
are all installed in the feedback circuit 26 as feedback elements, and the switches 31-S. A necessary resistance value is set in the feedback circuit 26 in stages by the resistors R1 to R3°, whose connections are switched by selectively turning on and off the resistors R1 to R3°. Each switch 31
~S 100 opening/closing control is performed using switch control signals SW1, SW2, . . . SWl applied from a decoder matrix 401 installed in the switch control unit 40. It will be carried out with.

The CTL signal amplified by the amplifier 22 with an arbitrary amplification gain is applied to the frequency divider 36 of the rotation control system of the capstan motor 2 and to the switch control unit 40 that switches the switches 31 to 310. The divided output of the frequency divider 36 is applied as a servo input to the phase servo circuit 14, and the servo output is applied to the capstan motor 2 through the driver 18, so the rotation of the capstan motor 2 is controlled according to the CTL signal. .

The switch control section 40 also includes an inverter 402 and resistors 403 and 404 as a signal inversion circuit in the signal control section.
is installed, and after the CTL signal from the amplifier 22 is inverted, its level is detected by two comparators 405 and 406 installed as signal level detection means.

Comparators 405 and 406 are set with different reference levels 3, Vz (V+ < Vz) as comparison values. For CTL signal level detection, for example, V+
= 3.2V, V2 = 4, OVl: settings, if the CTL signal level is below (a) v r, (
b) If V exceeds 1 and is less than ■2, (C) V Z
For example, if the level of the CTL signal exceeds the reference level ■1 and is less than the reference level 72, as shown in A in FIG. As shown in FIG. 2, a high (H) level comparison output is obtained from the comparator 405, and a low (L) level comparison output is obtained from the comparator 406, as shown in FIG. 2C.

In this case, if the CTL signal is less than the reference level ■1, the comparison outputs of the comparators 405 and 406 both become L level. Further, as shown in D in FIG. 2, when the level of the CTL signal exceeds the reference level v2, as shown in FIG. It will be done.

The comparison output of the comparator 405 is the D-flip-flop circuit (I)-FF) 407.40 that constitutes the delay circuit.
8.409 is added to the reset human power R. D-F
The F407 to F409 are connected in cascade, a CPG signal is applied to the input C through the input terminal 410, and an H level voltage ■□ is applied to the D input of the first stage D-FF407. Therefore, when the reset is released and the CPG signal shown at G in FIG. 3 is applied to the input terminal 410, the output shown at 1 in FIG.
Output from FF408 shown in J in Figure 3, D-FF409
From this, the output shown at K in FIG. 3 is obtained. And D-F
The output of F409 and the CPG signal are connected to AND circuit 411.
A CPG signal shown in M in FIG. 3 is obtained from the AND circuit 411 with a delay time of two cycles of the original CPG signal applied to the input terminal 410.

The output of the AND circuit 411 is applied as a count-up signal, and the comparison output of the comparator 406 is applied as a count-down signal to an up-down counter 412 installed as basic data creation means for switching the switches 81 to S+o. up/down counter 41
2 form basic data for the decoder matrix 401, and are switches S, -S,. The number of bits corresponds to the number of bits, in this embodiment, it is constituted by a 4-bit up/down counter. A clock pulse CL is generated by a count up signal and a count down signal.
K is counted up and counted down, and a power-on reset signal P1 is applied to the reset terminal 413.

The count value of the up-down counter 412 is transferred to the decoder matrix 401, and the decoder matrix 401 switches switches S, -S, according to the count value of the up-down counter 412. Switch control signal SW1 for opening and closing
~SW,. are formed, and corresponding switches 31-S,.

has been added to.

With the above configuration, when the level of the CTL signal is below the reference level ■1, each comparator 405.4
06 both produce an L level comparison output, and D-FF407
~409 reset is released. In this case, the CPG signal applied to the input terminal 410 is
Due to the delay operation shown in G7K in FIG. 3 by 409, A
A CPG signal delayed by two periods is obtained from the ND circuit 411 as shown in M in FIG. 3, and is applied to the up/down counter 412 as a count up signal.

The up/down counter 412 adds and counts clock pulses CLK based on the count amplifier signal. The decoder matrix 401 receives switch control signals SW, ~S according to the count value of the up/down counter 412.
W, is generated. For example, switch control signal SW
, the switch S is closed, and the resistors R1 to R4 are set as feedback elements in the feedback circuit 26, the switch control signal SWb is generated according to the addition count of the up/down counter 412, and the switch S is closed.
, is closed and as long as the addition count continues, the switch S,
, S, . . . so that the resistance value for the feedback circuit 26 becomes the resistance R, -R,, Rs, R=
...and the amplification gain rises.

Next, when the level of the CTL signal exceeds the reference level (2), the comparator 405 generates an H level comparison output, and this comparison output resets the D-FFs 407 to 409. Therefore, the output from the D-FF 409 is canceled, the AND circuit 411 produces an L level output, and the addition count of the up/down counter 412 is stopped. As a result, the count value of the up/down counter 412 is held, and the switch control signal SWB based on the count value, for example, is output from the decoder matrix 401, the switch S8 is closed, and the resistors R1 to R1 are connected to the amplifier 22.
A constant gain of 1□ is set.

Next, when the level of the CTL signal exceeds the reference level ■2, the comparators 405 and 406 both produce comparison outputs of level ■]. The output of comparator 406 is applied as a countdown signal to up/down counter 412, which produces a subtraction count. At this time, according to the comparison output of the comparator 405,
Since D-FF407 to 409 are reset, AND
The circuit 411 produces an L level output, and the addition count of the up/down counter 412 is stopped. When the up/down counter 412 performs subtraction counting, the counted value is added to the decoder matrix 401, and the decoder matrix 401 generates switch control signals SW1 to SW, o according to the counted value of the up/down counter 412. Assuming that switch S is currently closed, switches Sa to switches 37, 36...
The resistance value for the feedback circuit 26 is decreased stepwise to the resistors R12 to R, , R, . . . , and the amplification gain is decreased.

Table 1 shows switches S, -S, when the gain is adjusted and controlled in 11 steps using resistors R8 to R3□. The relationship between the opening and closing of , and the set amplification factor (times) and gain (dB) is shown.

As shown in Table 1 above, the switch S
, ~S1° are controlled to open and close, resistors R3~R3□ are selected for the feedback circuit 26 of the amplifier 22, and the optimum gain is set, and the CT L signal is brought to the reference level ■1~
■It is controlled to be within the range of 2.

Basic data for gain setting is up/down counter 4
12, arbitrary gain settings can be easily made from the outside. Moreover, since counting is performed by the up-down count 412 in one cycle of the CTL signal, the attack time and recovery time are uniquely determined, and when the signal cycle is fast or slow,
A response is made according to the speed and speed, and it is possible to correspond to a wide signal period.

Although the embodiments have been explained using CTL signals of a phase servo system in a video tape recorder as an example, the automatic gain adjustment circuit of the present invention can be applied to various signals in addition to CPG signals. .

[Effects of the Invention] As explained above, according to the present invention, the opening and closing of the switch is controlled using a switch control means equipped with a counter that adjusts the count value according to the signal level, and the resistance value for the feedback circuit is controlled by the opening and closing. Since the amplification gain is adjusted by changing stepwise, the gain can be easily set externally, and the optimum gain can be adjusted in accordance with the signal period.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the automatic gain adjustment circuit of the present invention, FIG. 2 is a diagram showing the operation of the comparator of the automatic gain adjustment circuit shown in FIG. 1, and FIG. FIG. 4 is a block diagram showing a general capstan servo system in a video tape recorder. 22...Amplifier 26...Feedback circuit 28...Resistance circuit R8-Rff2...Resistor S1-310...Switch 40...Switch control section (switch control means) 412
...up/down counter (counter)---v
2 C (output of conoparator 406) -5

Claims (1)

[Claims] Selecting a resistor circuit including a plurality of resistors installed in a feedback circuit of an amplifier, and a resistor installed in the feedback circuit between an arbitrary resistor of this resistor circuit and the amplifier. A switch, and switch control means that includes a counter that adds or subtracts according to the output level of the amplifier, controls opening and closing of the switch according to the counted value, and switches a resistor installed in the feedback circuit in stages. Automatic gain adjustment circuit.