JPH01253271A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPH01253271A
JPH01253271A JP63080942A JP8094288A JPH01253271A JP H01253271 A JPH01253271 A JP H01253271A JP 63080942 A JP63080942 A JP 63080942A JP 8094288 A JP8094288 A JP 8094288A JP H01253271 A JPH01253271 A JP H01253271A
Authority
JP
Japan
Prior art keywords
film
electrode
growth rate
reaction vessel
resistive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63080942A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Uchida
内田 喜之
Katsunori Ueno
勝典 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP63080942A priority Critical patent/JPH01253271A/en
Publication of JPH01253271A publication Critical patent/JPH01253271A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To build a breakdown resistant structure characterized by absence of dispersion of leak currents by a method wherein microcrystals Si:H, produced by plasma CVD and equipped with resistance highly stable and reproducible at low temperatures, are used as a field plate resistance film. CONSTITUTION:A reaction vessel 12 is evacuated by an evacuating system 13 and then an H2-containing film forming gas is introduced into the reaction vessel 12 through a gas supply system 14. After this, power is applied across a cathode electrode 15 and anode electrode 16 from an RF power source 17, which results in the generation of plasma across the two electrodes 15 and 16 and in the formation of an amorphous silicon film on a substrate on the heated anode electrode 16. In this process, the Si:H film growth rate is set at 0.1-0.5Angstrom /sec for the formation of a microcrystal Si:H film constructed of approximately 100Angstrom diameter crystal grains. For a decreased film growth rate, percentage of H2 is to be raised in the film forming gas.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はバイポーラトランジスタ、パワーMO3FET
および絶縁ゲート型バイポーラトランジスタなど高耐圧
を必要とする半導体素子の耐圧構造に関する。
[Detailed description of the invention] [Industrial application field] The present invention is applied to bipolar transistors, power MO3FETs,
The present invention also relates to the breakdown voltage structure of semiconductor devices that require high breakdown voltage, such as insulated gate bipolar transistors.

〔従来の技術〕[Conventional technology]

以上の高耐圧半導体素子の耐圧構造としてガードリング
やフィールドプレートなどが用いられているが、面積が
少なくて済み、また安定した耐圧が得られることから、
フィールドプレートが多く使用されるようになってきて
いる。次にこれら高耐圧半導体素子に設けられるフィー
ルドプレートとその動作について第3図を参照して説明
する。
Guard rings, field plates, etc. are used as the breakdown voltage structure of the above-mentioned high breakdown voltage semiconductor devices, but because they require less area and can provide stable breakdown voltage,
Field plates are increasingly being used. Next, the field plate provided in these high voltage semiconductor devices and its operation will be explained with reference to FIG.

第3図は高耐圧半導体素子の部分断面図であり、N−半
導体基板1.  P″領域2.絶縁膜3.導電金属など
の低抵抗膜4.フィールドプレートの抵抗性膜5.負側
電極6.その端子7.正側電極8゜9とその端子10を
表わす部分である。第3図において電極6と電極9の間
に正の電圧を印加すると P″領域2と N−基板1の
間のPN接合は逆バイアス状態となり、空乏層が N−
基板1側に拡がって電気的に絶縁される。このときの空
乏層の等電位面は例えば第3図の一点鎖線11のように
なる。電極8は電極9と等電位にあるから電極6と電極
8の間にも電圧が印加された状態となる。この状態で、
もし抵抗性n* 5が形成されていない場合は、 P″
領域2と N−基板1の間の耐圧は P゛領域2の不純
物拡散深さの曲率の大きさで決まり、平面におけるPN
接合の場合に比べてかなり小さい値となるのが普通であ
る。それは PJTI域2の曲率の部分に電界が集中す
るからであり、曲率の大きさと空乏層の長さから計算に
より耐圧を求めた線図を第4図に示す、第4図は横軸を
接合の曲ml径r4 と空乏層の長さW、4 の比とし
、縦軸を平面接合の場合の耐圧を1としたときの関係を
表わした線図であり、第4図から曲率を有する接合は、
通常でも平面接合の場合の半分以下の耐圧しか得られな
いことがわかる。
FIG. 3 is a partial cross-sectional view of a high-voltage semiconductor element, showing an N-semiconductor substrate 1. P'' region 2. Insulating film 3. Low resistance film such as conductive metal 4. Resistive film of field plate 5. Negative electrode 6. Its terminal 7. Positive electrode 8. This is the part representing 9 and its terminal 10. 3, when a positive voltage is applied between electrode 6 and electrode 9, the PN junction between P″ region 2 and N− substrate 1 becomes reverse biased, and the depletion layer becomes N−.
It spreads toward the substrate 1 side and is electrically insulated. At this time, the equipotential surface of the depletion layer becomes, for example, as shown by the dashed-dotted line 11 in FIG. Since the electrode 8 is at the same potential as the electrode 9, a voltage is also applied between the electrode 6 and the electrode 8. In this state,
If resistive n*5 is not formed, P″
The breakdown voltage between region 2 and N-substrate 1 is determined by the size of the curvature of the impurity diffusion depth of P region 2, and the PN in the plane
The value is usually much smaller than that in the case of bonding. This is because the electric field concentrates on the curvature of PJTI region 2. Figure 4 shows a diagram showing the breakdown voltage calculated from the magnitude of the curvature and the length of the depletion layer. This is a diagram showing the relationship when the vertical axis is the ratio of the curve ml diameter r4 and the length W,4 of the depletion layer, and the breakdown voltage in the case of a planar junction is set to 1. teeth,
It can be seen that even under normal conditions, the withstand voltage is less than half that of planar bonding.

第3図に示した抵抗性膜5は絶縁膜3とは異なり一定の
抵抗値をもって負側電極6と正側電極8を接続し、でき
るだけ空乏層の拡がり方を平面接合の場合に近イ9させ
、接合の曲率部分への電界の集中を緩和することにより
、耐圧を平面接合の場合に近づけようとするためのもの
である。すなわち、抵抗性膜5の直下の N−基板1の
表面には絶縁膜3を通して抵抗体である膜5の電圧が印
加され、その電圧分布は負側電極6から正側電極8へ向
1.て直線的に電圧が上昇する形となり、 N−基板1
の表面近傍では空乏層が拡げられ P″領域2と N−
基板lの間の接合は平面接合の場合に近くなる0以上の
ことから、このような素子の耐圧を平面接合の場合の耐
圧に近づけるには負側電極6と正側電極8の間の距離を
大きくすればよいことがわかる。そしてこのフィールド
プレートの抵抗性膜5として通常蒸着などにより形成さ
れる非晶質シリコン膜や多結晶シリコン膜が使用されて
いる。
Unlike the insulating film 3, the resistive film 5 shown in FIG. This is intended to bring the breakdown voltage closer to that of a planar junction by reducing the concentration of electric field on the curved portion of the junction. That is, the voltage of the film 5, which is a resistor, is applied to the surface of the N-substrate 1 directly under the resistive film 5 through the insulating film 3, and the voltage distribution is from the negative electrode 6 to the positive electrode 8. The voltage increases linearly, and N-substrate 1
The depletion layer is expanded near the surface of P″ region 2 and N−
Since the junction between the substrates l is greater than or equal to 0, which is closer to that in the case of planar bonding, in order to bring the withstand voltage of such an element closer to the withstand voltage in the case of planar bonding, the distance between the negative electrode 6 and the positive electrode 8 is It turns out that you can make it larger. As the resistive film 5 of this field plate, an amorphous silicon film or a polycrystalline silicon film, which is usually formed by vapor deposition or the like, is used.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上のように高耐圧を必要とする半導体素子に対して抵
抗性膜を設けることは有効な手段であるが、抵抗性膜に
非晶質シリコンを用いるとき、蒸着法は抵抗値の制御を
十分に行ない難く、再現性よく抵抗性膜を形成するのが
むつかしい。この抵抗値は半導体素子のもれ電流を決定
するので、抵抗値にばらつきが生ずると、それに対応し
てもれ電流も変動することになり、素子特性を悪化させ
る原因となる。また一方抵抗性膜に多結晶シリコン膜を
用いる場合、膜の生成温度が400’C前後の高温であ
り、抵抗性膜は金属電極を形成した後に被着するのが普
通であるから、高温処理は金属電極の膜質の劣化を招く
原因となる。
As described above, providing a resistive film is an effective means for semiconductor devices that require high breakdown voltage, but when using amorphous silicon for the resistive film, vapor deposition methods do not allow sufficient control of the resistance value. It is difficult to form a resistive film with good reproducibility. This resistance value determines the leakage current of the semiconductor element, so if a variation occurs in the resistance value, the leakage current will also vary accordingly, causing deterioration of the element characteristics. On the other hand, when a polycrystalline silicon film is used as the resistive film, the film is formed at a high temperature of around 400'C, and since the resistive film is usually deposited after forming the metal electrode, high-temperature treatment is required. This causes deterioration of the film quality of the metal electrode.

本発明は上述の点に鑑みてなされたものであり、その目
的は比較的低い成膜温度で形成することができ、抵抗値
の安定性が高いフィールドプレートの抵抗性膜を存する
半導体素子を提供することにある。
The present invention has been made in view of the above points, and its purpose is to provide a semiconductor element having a field plate resistive film that can be formed at a relatively low film formation temperature and has a highly stable resistance value. It's about doing.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題を解決するために本発明の半導体素子はフィー
ルドプレートの抵抗性膜として、プラズマC,V D法
により低温で再現性よく安定した抵抗値の得られる微結
晶Si:Hを使用するものである。
In order to solve the above problems, the semiconductor device of the present invention uses microcrystalline Si:H, which can obtain stable resistance values with good reproducibility at low temperatures by the plasma C, VD method, as the resistive film of the field plate. be.

(作用〕 本発明における抵抗性膜は300°C程度までの温度で
成膜され、膜厚や比抵抗のばらつきを±10%以内に再
現性よく制御することができ、不純物を導入す、ること
によって109〜1O−1Ω・cmの広範囲な抵抗値が
得られるのでフィールドプレートとして用いるのに好適
であり、もれ電流の安定な耐圧構造を有する半導体素子
を得ることができる。
(Function) The resistive film of the present invention is formed at a temperature of up to about 300°C, and variations in film thickness and specific resistance can be controlled with good reproducibility within ±10%, and impurities can be introduced. As a result, a wide range of resistance values from 10 9 to 1 O −1 Ω·cm can be obtained, making it suitable for use as a field plate, and a semiconductor element having a breakdown voltage structure with stable leakage current can be obtained.

〔実施例〕〔Example〕

以下本発明を実施例に基づき説明する。 The present invention will be explained below based on examples.

上述のように本発明に用いられる抵抗性膜は微結晶Si
 :Hであり、例えば太陽電池の製造に使用されている
プラズマCVD法による薄膜製造装置を利用して形成す
ることができる。第1図はその装置構成の要部断面図を
示したものであり、主な部分は、反応容器12.これを
真空に排気する排気系13.成膜ガスを供給するガス供
給系】4.カッ 0−ド電1415.アノード電極16
.カソード電極15に接続されるRF電源17.アノー
ド電極16 上に位置し抵抗性膜を形成する半導体板1
8.アノード電極16の下方に位置し半導体板18を加
熱するヒータ 19およびヒータ電源20からなる。な
お抵抗性膜を形成するまでの素子製造過程は省略し、こ
こでは単に半導体板1日 として扱うことにする。
As mentioned above, the resistive film used in the present invention is made of microcrystalline Si.
:H, and can be formed using, for example, a plasma CVD thin film production apparatus used in the production of solar cells. FIG. 1 shows a cross-sectional view of the main parts of the apparatus configuration, and the main parts are the reaction vessel 12. Exhaust system 13 to evacuate this to vacuum. Gas supply system that supplies film-forming gas】4. Cup 0-Code Electric 1415. Anode electrode 16
.. RF power source 17 connected to cathode electrode 15. Anode electrode 16 Semiconductor plate 1 located above and forming a resistive film
8. It consists of a heater 19 located below the anode electrode 16 and heating the semiconductor board 18 and a heater power source 20. Note that the device manufacturing process up to the formation of the resistive film will be omitted, and here it will simply be treated as one day of manufacturing a semiconductor board.

この装置を用いて微結晶S! :Hの抵抗性膜を形成す
る方法はほとんど太陽電池の非晶質シリコン膜を形成す
る場合と同じであるから、はじめに通常の非晶質シリコ
ン膜を形成する手順の概要を述べる。まず反応容器I2
を真空排気系13により真空度が数m Torr以下程
度になるまで排気した後、ガス供給系14からHtを含
む5iHaなどの成膜ガスを反応容器12内に供給し、
一部真空排気系13で排気して反応容器12内の圧力を
I Torr程度に保つ。この後カソード電極15 と
アノード電極16にRF電源17から電力を供給し、雨
量i 15.16間にプラズマを発生させる。このとき
電[20によりヒータ 19で約200°Cに加熱され
ているアノード電極16上の例えばここでは図示してな
い基板上に、画電極15.16間に発生したプラズマに
よって非晶質シリコン膜を形成することができる。
Microcrystal S using this device! Since the method for forming a :H resistive film is almost the same as that for forming an amorphous silicon film for a solar cell, an outline of the procedure for forming a normal amorphous silicon film will first be described. First, reaction vessel I2
is evacuated by the vacuum evacuation system 13 until the degree of vacuum is approximately several m Torr or less, and then a film forming gas such as 5iHa containing Ht is supplied into the reaction vessel 12 from the gas supply system 14.
Part of the reaction vessel 12 is evacuated using a vacuum evacuation system 13 to maintain the pressure inside the reaction vessel 12 at about I Torr. Thereafter, power is supplied from the RF power source 17 to the cathode electrode 15 and the anode electrode 16, and plasma is generated during the rain amount i 15.16. At this time, an amorphous silicon film is formed by the plasma generated between the picture electrodes 15 and 16 on, for example, a substrate (not shown here) on the anode electrode 16 which is heated to about 200°C by the heater 19 by the electric current [20]. can be formed.

以上の過程は微結晶Si :Hの膜を形成するときも同
様であるが、非晶質シリコン膜を形成するときと異なる
のは膜の成長速度である。すなわち、通常の非晶質シリ
コン膜では膜の成長速度は1〜4人/seeであるのに
対し、微結晶Si 二H膜を形成するときは成長速度を
遅<Lo、1〜0.5人/sec程度とすることである
。このようにしてほぼ100人の結晶粒をもつSi :
H膜を成長させることができる。膜成長速度を低くする
にはS f HaとHzの成膜ガスにおけるH!の比率
を高くすること、すなわちH2の流量を多くすることで
ある。
The above process is the same when forming a microcrystalline Si:H film, but the difference from when forming an amorphous silicon film is the growth rate of the film. That is, the growth rate of a normal amorphous silicon film is 1 to 4 people/see, whereas when forming a microcrystalline Si 2H film, the growth rate is slowed to <Lo, 1 to 0.5 It should be about 1 person/sec. In this way, Si with almost 100 grains:
A H film can be grown. To reduce the film growth rate, H! in the film forming gas of S f Ha and Hz is required. In other words, to increase the flow rate of H2.

第2図は5tHn:Hz成膜ガスの比率を変えたときの
抵抗性膜を形成する半導体板18の温度(以下これを成
膜温度と呼ぶ)とSi:H膜の成長速度との関係を表わ
す線図である。第2図の曲線(イ)はS i H4: 
Hz = 1 : 41曲線(ロ)はS i Ha :
H2=1:9.曲線(ハ)は5IHa:Hz= 1 :
 14としたものである。第2図かられかるようにH2
の2it量を多くすることにより膜成長速度が低下し、
曲線(ハ)では微結晶St :H膜を得ることができる
。また成膜温度によって膜成長速度はあまり変化しない
から、100〜200°C程度の低温でも微結晶Si:
H膜を成長させることが可能である。この微結晶SL 
:H膜を抵抗性膜として形成する際、不純物を導入する
ことなく膜成長を行なうと、N形で比抵抗がlO″Ω・
1程度のものとなるが、不純物としてボロンなどを第1
図のガス供給系14から導入するとさらに高抵抗の膜が
得られ、同様にpH,などを成膜時に導入することによ
り低抵抗の膜が得られる。以上のように本発明における
抵抗性膜としての微結晶S1 :H膜はH,の流量と、
不純物の導入によって10”〜1O−1Ω・cmの広い
範囲にわたって抵抗値を制御することが容易である。
Figure 2 shows the relationship between the temperature of the semiconductor substrate 18 forming the resistive film (hereinafter referred to as the film forming temperature) and the growth rate of the Si:H film when the ratio of the 5tHn:Hz film forming gas is changed. FIG. The curve (a) in Figure 2 is S i H4:
Hz = 1: 41 curve (b) is S i Ha:
H2=1:9. Curve (c) is 5IHa:Hz=1:
14. As shown in Figure 2, H2
By increasing the amount of 2it, the film growth rate decreases,
In curve (c), a microcrystalline St 2 :H film can be obtained. In addition, since the film growth rate does not change much depending on the film formation temperature, microcrystalline Si:
It is possible to grow H films. This microcrystalline SL
:When forming an H film as a resistive film, if the film is grown without introducing impurities, it will be N-type with a resistivity of 1O''Ω・
However, if impurities such as boron are added to the
If it is introduced from the gas supply system 14 in the figure, a film with even higher resistance can be obtained, and similarly, by introducing pH, etc. during film formation, a film with lower resistance can be obtained. As described above, the microcrystalline S1:H film as a resistive film in the present invention has a flow rate of H,
By introducing impurities, it is easy to control the resistance value over a wide range of 10'' to 1O-1 Ω·cm.

さらにこのようにして得られた微結晶Si:H膜は大面
積のものに対しても膜厚および比抵抗のばらつきが±1
0%以内であるという優れた再現性を有している。
Furthermore, the microcrystalline Si:H film obtained in this way has a variation of ±1 in film thickness and resistivity even for large areas.
It has excellent reproducibility of within 0%.

〔発明の効果] バイポーラトランジスタ、パワーMOS F ET。〔Effect of the invention] Bipolar transistor, power MOS FET.

絶縁ゲート型バイポーラトランジスタなどの高耐圧半導
体素子に設けるフィールドプレートの抵抗性膜は従来蒸
着法などによる非晶質シリコン膜や多結晶シリコン膜を
用いていたが、これらは抵抗値の制御や再現性に劣り、
また高温処理を必要とするなど満足すべきものが得られ
なかったのに対し、本発明では実施例で述べたように、
プラズマCVD法による薄膜製造装置を利用して成膜ガ
スのSiH4:HzのHz a量を多くして成膜速度を
低下させ、微結晶St :H膜を低温で形成するととも
に不純物を導入して抵抗値が広範囲に制御可能な膜とし
、この抵抗値が安定で再現性のよい微結晶St :H膜
をフィールドプレートに好適な抵抗性膜として用いたた
め、もれ電流にばらつきのない特性の安定な耐圧構造を
もつ半導体素子を構成することができるという大きな効
果を得ることができる。
Conventionally, amorphous silicon films or polycrystalline silicon films made by vapor deposition have been used as resistive films for field plates in high-voltage semiconductor devices such as insulated gate bipolar transistors, but these have been difficult to control the resistance value and reproducibility. inferior to
In addition, high-temperature treatment was required, so that satisfactory results could not be obtained, whereas in the present invention, as described in the examples,
Using a plasma CVD thin film manufacturing device, the amount of Hz a in the SiH4:Hz film forming gas was increased to reduce the film forming rate, and a microcrystalline St:H film was formed at a low temperature while impurities were introduced. The resistance value can be controlled over a wide range, and the microcrystalline St:H film, which has a stable resistance value and good reproducibility, is used as a resistive film suitable for the field plate, resulting in stable characteristics with no variation in leakage current. A great effect can be obtained in that a semiconductor element having a high breakdown voltage structure can be constructed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明における微結晶Si:HWJを形成する
装置の要部断面図、第2図はH2流量をパラメータとす
る成膜温度と膜成長速度との関係を示す線図、第3図は
フィールドプレートを存する半導体素子の部゛分断面図
、第4図は曲率をもつPN接合の曲率半径と空乏層の長
さとの比に対する耐圧の関係線図である。 ■・・・ N−半導体基板、2・・・ P′領領域3・
・・絶縁膜、5・・・抵抗性膜、6・・・負側電極、8
,9・・・正側電極、11・・・バイアス時の等電位面
、12・・・反応容器、13・・・真空排気系、14・
・・ガス供給系、15・・・力゛ノードy 1 図 へ騨、温度(C) ぢ 2 図
Fig. 1 is a cross-sectional view of the main parts of the apparatus for forming microcrystalline Si:HWJ in the present invention, Fig. 2 is a diagram showing the relationship between film formation temperature and film growth rate using H2 flow rate as a parameter, and Fig. 3 4 is a partial cross-sectional view of a semiconductor element including a field plate, and FIG. 4 is a diagram showing the relationship between the breakdown voltage and the ratio of the radius of curvature of a PN junction having curvature to the length of the depletion layer. ■... N-semiconductor substrate, 2... P' region 3.
...Insulating film, 5...Resistive film, 6...Negative side electrode, 8
, 9... Positive side electrode, 11... Equipotential surface during bias, 12... Reaction vessel, 13... Vacuum exhaust system, 14...
...Gas supply system, 15...Power node y 1 Figure, temperature (C) 2 Figure

Claims (1)

【特許請求の範囲】[Claims] 1)第1導電型半導体基板に第2導電型領域を有し、前
記半導体基板と前記第2導電型領域に逆バイアスを印加
することにより空乏層の拡がる前記半導体基板の表面に
設けられた絶縁膜を介して抵抗性膜によって電圧を印加
する半導体素子であって、前記抵抗性膜として微結晶S
i:H膜を用いることを特徴とする半導体素子。
1) An insulator provided on the surface of the semiconductor substrate having a second conductivity type region in a first conductivity type semiconductor substrate, and in which a depletion layer is expanded by applying a reverse bias to the semiconductor substrate and the second conductivity type region. A semiconductor element in which a voltage is applied by a resistive film through a film, the resistive film being a microcrystal S.
A semiconductor device characterized by using an i:H film.
JP63080942A 1988-04-01 1988-04-01 Semiconductor element Pending JPH01253271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63080942A JPH01253271A (en) 1988-04-01 1988-04-01 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63080942A JPH01253271A (en) 1988-04-01 1988-04-01 Semiconductor element

Publications (1)

Publication Number Publication Date
JPH01253271A true JPH01253271A (en) 1989-10-09

Family

ID=13732542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63080942A Pending JPH01253271A (en) 1988-04-01 1988-04-01 Semiconductor element

Country Status (1)

Country Link
JP (1) JPH01253271A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1000892C2 (en) * 1994-07-27 1997-07-29 Sharp Kk Thin film semiconductor device, thin film transistor and method of its manufacture.
KR100393955B1 (en) * 1995-12-09 2003-08-06 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device comprising a microcrystalline semiconductor film

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1000892C2 (en) * 1994-07-27 1997-07-29 Sharp Kk Thin film semiconductor device, thin film transistor and method of its manufacture.
US5796116A (en) * 1994-07-27 1998-08-18 Sharp Kabushiki Kaisha Thin-film semiconductor device including a semiconductor film with high field-effect mobility
US6271062B1 (en) 1994-07-27 2001-08-07 Sharp Kabushiki Kaisha Thin film semiconductor device including a semiconductor film with high field-effect mobility
KR100393955B1 (en) * 1995-12-09 2003-08-06 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device comprising a microcrystalline semiconductor film

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