JPH01255932A - Instruction processor - Google Patents

Abstract

PURPOSE:To shorten instruction processing time by predicting an introduced instruction, executing a precedence processing, and when the prediction is wrong, executing the processing in accordance with the introduced instruction. CONSTITUTION:A first processing means to execute the processing in accordance with a prescribed instruction introduced successively executes the precedence processing in accordance with the predictive result. A deciding means 131 decides whether or not the prediction by a predictive means 111 is right and the decided result is supplied to a second processing means 141. When the predictive result by the predictive means 111 is wrong, the second processing means 141 executes the processing in accordance with the introduced instruction. Thus, since the instruction introduced is predicted and the precedence processing is executed, instruction processing time can be shortened.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples ■, Correspondence between the Examples and FIG. 1 ■ , Structure of the embodiment ■, Operation of the embodiment (i) Input/output command (ii) Operation when a startup detection interrupt occurs (iii) Operation when a data/status transfer completion interrupt occurs ■, Summary of the embodiment ■ 8. Effects of the invention in modified form [Summary] Regarding an instruction processing device configured to execute processing according to instructions introduced sequentially, the purpose of the invention is to reduce instruction processing time by retaining information regarding the order of instruction introduction, A prediction means for predicting an instruction to be introduced next; a first processing means for executing advance processing according to a prediction result by the prediction means; A second processing means that executes a process according to the introduced instruction when the judgment result of the judgment means is introduced and the prediction by the prediction means is not correct. Configure it as follows.

[Industrial application field]

The present invention relates to an instruction processing device, and more particularly to an instruction processing device that executes processing according to instructions that are sequentially introduced.

[Conventional technology]

A normal instruction processing device generally performs program processing on introduced instructions for reasons such as device simplification and flexibility.

For example, as an example of an instruction processing device, consider a channel connection adapter built into a communication control processing device that controls data exchange between a line and a host computer or the like.

FIG. 4 shows the configuration of a communication system using the communication control processing device.

In the figure, a host computer 411 is connected to a communication control processing device 421 via a channel device 413, and is further connected to an external line.

This communication control processing device 421 is a communication control processing device 42
1, a main storage unit (MSU) 443 that stores control programs executed by the CCU 441, data, etc., and a channel that controls data exchange with the host computer 411 side. A connection adapter 431, a line unit 453 that accommodates multiple lines, and a line control adapter 4 that controls data exchange with the line side via the line unit 453.
51.

The CCU 441 supplies various input/output commands to the channel connection adapter 431 or the line control adapter 451. The channel connection adapter 431 and line control adapter 451 execute microprograms to
Executes processing according to the supplied instructions.

For example, when an interrupt is generated from the host computer 411 to the channel connection adapter 431 (such as a startup interrupt to start communication or a completion interrupt when data transmission is finished), the channel connection adapter 431 interrupts the channel connection adapter 431 with predetermined data (interrupt (type of interrupt, address of interrupt source, etc.)
Create.

Next, the CCU 441 sequentially sends the input commands to the channel connection adapter 431, and the channel connection adapter 431 supplies response data corresponding to the received input commands to the CCU 441.

[Problem to be solved by the invention]

By the way, the above-mentioned channel connection adapter 431 has a problem in that the microprogram deals with the instruction each time it receives an instruction from the CCU 441, which increases the instruction processing time.

Although it is possible to shorten the processing time by implementing the processing by the channel connection adapter 431 in hardware, it lacks flexibility. Also, although it is possible to implement hardware in consideration of flexibility,
This increases the complexity of the circuit and increases the cost.

Therefore, there has been a desire for a system that can maintain flexibility and shorten processing time with a relatively simple circuit configuration.

The present invention was created in view of the above points, and an object of the present invention is to provide an instruction processing device that reduces instruction processing time.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of an instruction processing device according to the present invention.

In the figure, a prediction unit 111 in an instruction processing device that performs processing according to predetermined instructions that are sequentially introduced holds information regarding the instruction introduction order and predicts the next instruction to be introduced.

The first processing means 121 executes advance processing according to the prediction result by the prediction means 111.

The determining means 131 determines whether the prediction by the predicting means 111 is correct when the instruction is introduced.

The second processing means 141 receives the judgment result from the judgment means 131 and executes processing according to the introduced instruction when the prediction by the prediction means 111 is not correct.

Therefore, the overall configuration is such that the first processing means 121 executes the preliminary processing by predicting the command to be introduced, and when the prediction is incorrect, the second processing means 141 executes the processing.

[For production]

The prediction means 111 predicts the next instruction to be introduced, and the first processing means 121 executes advance processing according to the prediction result. Further, the determining means 131 determines whether or not the prediction by the predicting means 111 is correct, and the determination result is supplied to the second processing means 141.

If the prediction result by the prediction means 111 is incorrect, the second processing means 141 executes processing according to the introduced command.

According to the present invention, the instruction processing time can be shortened by predicting the instruction to be introduced and performing advance processing, and when the prediction is incorrect, executing processing according to the introduced instruction. can.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment to which the instruction processing device of the present invention is applied.

1. Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The prediction means 111 uses the address RAM 211. Corresponds to the address register 213.

The first processing means 121 is an input data buffer (IDB)
223. This corresponds to the storage area 321.

The determining means 131 corresponds to the input data read control section 231, the instruction decoder 2411, and the interrupt control section 243.

The second processing means 141 includes a storage area 321. ALU341
corresponds to

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

In Figure 2, the channel connection adapter 200 and CeO 241 in the communication control processing device are connected by a bus (
The overall configuration of the communication control processing device is assumed to be the same as that shown in FIG. 4).

The channel connection adapter 200 includes a channel control processor 3 that controls the entire channel connection adapter 200.
10, a control memory 520 that stores a control program executed by the channel control processor 310, and a channel interface control unit for controlling the exchange of data and instructions between the channel control processor 310 and a channel device (not shown). 530 and channel control processor 3
It includes a bus interface control unit 210 for controlling the exchange of data and instructions between the CeO 1O and the CeO 241.

The bus interface control unit 210 also stores an address RAM 211 that holds information regarding the next instruction to be introduced.
and an address register 2 that holds the input instruction to be introduced.
13, an instruction decoder 241 that decodes the instruction, an interrupt control unit 243 that controls the output of an interrupt signal to the channel control processor 310, and a determination as to whether or not the predicted instruction matches the actually introduced instruction. an input data read control unit 231 that performs the above operations, an input data buffer 223 that temporarily holds response data corresponding to commands, and a multiplexer (MPX) 225 . It includes a receiver 251 and a driver 253.

Additionally, channel control processor 310 includes control memory 52
0, a storage area 321 for storing response data corresponding to commands, and two MPXs 331 and 333.

The commands supplied from the CCl 241 to the bus interface control unit 210 are sent to the ALU 34 via the receiver 251.
1. Instruction decoder 241. It is supplied to the data terminals of the address register 213 and address RAM 211. The output terminal of the instruction decoder 241 is connected to an interrupt control section 243, and the interrupt control section 243 is further connected to the ALU 341 and the input data read control section 231. The output terminal of the address register 213 is connected to the address terminal of the address RAM 211.
The data terminal (output side) is the input data read control section 23
1 and one input end of MPX331.

The other input end of MPX 331 is connected to ALU 341, and the output end of MPX 331 is connected to the address terminal of storage area 321. The input side data terminal of the storage area 321 is connected to the ALU 341, and the input side data terminal of the storage area 321 is connected to the ALU 341.
The output side data terminal of 21 is connected to one input terminal of MPX333.

The other input end of MPX333 is connected to ALU341, and the output end of MPX333 is connected to MPX2 through one input end of MPX225 and input data buffer 223.
25.

Data output from the output end of the MPX 225 is sent to the CCl 241 via the driver 253.

In addition, the ALU 341 is connected to the address register 213 and the CC
l241, and through these connection lines,
An interrupt signal output from the ALU 341 is supplied.

I-” 1 blood yoj■ is 1 Next, the operation of the embodiment of the present invention described above will be explained.

Now, in response to a request from the channel device side, the CCl 241 from the ALU 341 in the channel control processor 321
Consider the case where an interrupt is output for .

The CCU 441 that receives the interrupt from the ALU 341 outputs various commands to the channel connection adapter 200, and the channel connection adapter 200 executes processing corresponding to the commands.

Note that the interrupts output from the ALU 341 to the CCl 241 include the activation detection side input that is output when the communication control processing device is activated from the host computer, etc., and data and status from the host computer, etc. Consider two cases: (1) data/status transfer completion side, which is output when the output of (indication signal, etc.) is completed.

-〇〇- Shinshu or Mikou First, from CCl241 to channel connection adapter 200
We will explain the input/output commands sent to.

Table 1 shows an example of an input command (for example, it is assumed that there are 10 types of input commands, and some of them are shown). This is the address (hereinafter referred to as instruction address) of an external register (virtual register) for reading the data, and the data to be actually read is stored in the storage area 32.
1 is held in the area corresponding to this instruction address.

Table 2 also shows an example of output commands (for example, 10
Assume that there are several types of input commands, some of which are shown below)
.

Table 2 Next, the channel device side starts up, and the ALU341
The detailed operation when a startup detection interrupt is output will be explained.

FIG. 3 shows the operation timing when the activation detection interrupt is supplied to the CeO 241. In the figure, "instruction register" is a virtual external register for reading response data when the CeO 241 outputs an input command, and "instruction decode" is the decoding operation by the instruction decoder 241, rWE.

indicate write enable signals supplied to the address RAM 211, respectively.

Also, the "address register" is the address register 213
The address data stored in the lower 4 bits of ``address RAMJ'' indicates the data output from the address RAM 211, and ``input data buffer J indicates the data stored in the input data buffer 223,'' respectively.

A startup detection interrupt is output from the ALU 341, and a series of input/output instructions output by the CeO 441 in response to the interrupt are normally in the following order.

■INPUT (5) ■INPUT (0) ■INPUT (1) ■0UTPUT (0) Here, INPUT (X) is the input instruction corresponding to instruction address X, and 0UTPUT (Y) is the instruction address Y.
Each represents an output command corresponding to .

Furthermore, when a startup detection interrupt is output from the ALU 341, the channel connection adapter 200 stores "'01" in the upper two bits of the address register 213 of the bus interface control unit 210, and also stores the startup data (the above-mentioned (data to be sent back to the CeO 241 in response to an input command) is created and stored in the storage area 321.

First, the CeO 241 that received the startup detection interrupt sends the input command INPUT (5) to the channel connection adapter 20.
Send to 0.

This instruction is sent to the instruction decoder 241 via the receiver 251.
At the same time, this instruction address data ""5"
(4-bit data “'0101”) is stored in the lower 4 bits of the address register 213.

The instruction decoder 241 decodes the input instruction INPUT (5), and the interrupt control unit 243 sends an interrupt signal to the ALU 341 according to the decoding result.

When the interrupt from the interrupt control unit 243 is received, the ALU3
41 is the data (CeO
441 is a startup detection interrupt or a data/status transfer completion interrupt, and which channel connection adapter 200 sent the interrupt to the CeO 241) from the storage area 321,
CeO via PX333.225 and driver 253
Send to 44th engineer.

Also, at this time, the data “010101” is transferred from the address register 213 to the address terminal of the address RAM 211.
is supplied. The corresponding area of the address RAM 211 contains an input command INPUT (0) that is expected to be input next.
The instruction address data II OI+ of is stored,
This command address data "0" is supplied to the address terminal of the storage area 321 via the input data read control section 231 and MPX 331.

The storage area 321 outputs the response data of the input command INPUT (0) stored in the area specified by the command address data ゛°0゛ from the address RAM 211, and this response data is sent to the input data buffer 223 via the MPX 333. is maintained.

Next, when the input command INPUT (0) is output from the CeO 241 to the channel connection adapter 200, the command decoder 241 decodes this command and interrupts the interrupt controller 24.
3 supplies the decoding result to the input data read control section 231.

The input data read control unit 231 first reads the address RA.
Input command INPUT (0) input from M211
Based on the instruction address data "0" of , and the decoding result of the input instruction INPUT(,0) input from the interrupt control unit 243, it is determined whether the prediction is correct. When the prediction is correct, a switching instruction is sent to the MPX 225, and the response data held in the input data buffer 223 is sent to the CCU 441.

When the sending of the response data to the CCU 441 is completed, the input command INPUT (
The response data of 1) is held in the input data buffer 223. Next, an input command INPUT (1) is introduced, and if the predictions match, the response data stored in this input data buffer 223 is sent to the CCU 441.

Further, when the prediction by the input data read control section 231 is not correct, a determination result to that effect is supplied from the input data read control section 231 to the interrupt control section 243. When the interrupt control unit 243 receives this determination result,
Sends an interrupt signal to ALU341, and thereafter ALU3
Program processing according to 41 is performed.

Also, at this time (when the prediction is not correct), writing of data to the address RAM 211 is enabled (for example, a write enable signal is sent from the interrupt control unit 243 to the address RAM 211), and the command supplied from the CCU 441 Address data to address RAM211
write to. As a result, the prediction data stored in the address RAM 211 is updated each time.

Thereafter, advance processing corresponding to each input command is performed in the same manner.

Next, the operation when data transfer or status transfer from the channel device side is completed and a data/status transfer completion interrupt is output from the ALU 341 to the CCU 441 will be described.

At this time, the instructions output from the CCU 441 are in the following order.

■INPUT (5) ■INPUT (2) ■INPUT (3) ■INPUT (4) ■0UTPUT (',) When the ALU 341 outputs a data/status transfer completion interrupt, the channel connection adapter 200 outputs the address of the bus interface control unit 210. “10°” is stored in the upper two bits of the register 213, and predetermined data necessary for data (status) transfer is created and stored in the storage area 321.

Thereafter, the preceding processing corresponding to each input command is performed in the same manner as in the above-mentioned "r(ii) Operation at the time of activation detection interrupt occurrence".

■Summary of -1 In this way, from CCU441 to channel connection adapter 2
When various input commands are sent to 00, the command address data of the next input command to be received is read from the address RAM 211. Then, response data is read from the storage area 321 based on this command address data and held in the input data buffer 223.

When the next input command is input from the CCU 441 to the channel connection adapter 200 and the prediction is correct, the response data held in the input data buffer 223 is transferred to the CCU 441.
supply to. Also, if the prediction is not correct, AL
An interrupt signal is sent to U341, and program processing by ALU341 is executed.

Therefore, by predicting the command to be introduced and preparing response data, the command processing time can be shortened.

Note that in the embodiment of the present invention described above, the response data of the input command is prepared as a preliminary process.
Any method may be used as long as advance processing is possible (response data can be prepared or response data is not required, and processing branches are infrequent).

Further, in the embodiment, the processing in the channel connection adapter 200 in the communication control processing device was considered, but the present invention can be applied to other processing devices that perform program processing.

Furthermore, in "1. Correspondence between Examples and FIG. 1",
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, the instruction processing time is reduced by predicting the instruction to be introduced and performing advance processing, and when the prediction is incorrect, executing the processing according to the introduced instruction. Since it can be shortened, it is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the instruction processing device of the present invention, and FIG.
The figure is a configuration diagram of an embodiment to which the instruction processing device of the present invention is applied, FIG. 3 is an operation timing diagram of the embodiment, and FIG. 4 is a configuration diagram of a communication system. In the figure, 111 is a prediction means, 121 is a first processing means, 131 is a determination means, 141 is a second processing means, 200.431 is a channel connection adapter, 210 is a bus interface control unit, and 211 is an address RAM. 213 is an address register, 223 is an input data buffer, 225, 331, 333 is an MPX, 231 is an input data read control unit 1, 241 is an instruction decoder, 243 is an interrupt control unit, 251 is a receiver, 253 is a driver, 310 is a channel A control processor, 321 a storage area, and 341 an ALU. 520 is a control memory, and 530 is a channel interface control unit. 7 pieces, layer 〇 G■゛゛D, 7 blowfish Fig. 1 S also L stem structure reed mouth Fig. 4

Claims (1)

[Claims] (1) In an instruction processing device that performs processing in accordance with predetermined instructions that are sequentially introduced, a prediction means (111) that holds information regarding the instruction introduction order and predicts the next instruction to be introduced; and the prediction unit. a first processing means (121) for executing a preceding process according to a prediction result by the means (111); and a first processing means (121) for determining whether or not the prediction by the prediction means (111) is correct when an instruction is introduced. A determination means (131) for performing the determination, and a determination result in the determination means (131) are introduced,
a second unit that executes processing according to the introduced instruction when the prediction by the prediction means (111) is not correct;
An instruction processing device comprising: processing means (141).