JPH0431418B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A first channel common control unit that accepts commands from a central processing unit, terminates commands, controls channel paths, controls subchannels, etc., and circulates processing of each channel. A channel comprising an individual control unit that controls the individual control units individually in the order of channel numbers, and a second channel common control unit that performs control of the individual control units, command fetching, data transfer with the main storage device, etc. In the processing device, when a fault that cannot be identified in a channel occurs, the first channel common control unit continuously issues a fault processing execution start instruction to the individual control unit to shorten the fault processing execution time. This is what I did.

[Industrial application field]

The present invention relates to failure handling methods for microprocessors in channel processing units in general computer systems, and in particular to acceptance of instructions from central processing units, termination of instructions, control of channel paths, control of subchannels, etc. This is related to the processing method for a failure in which the channel number cannot be specified, which is detected by the first channel common control unit. It is related to the method of giving .

[Conventional technology]

FIG. 7 shows the configuration of a general computer system having a channel processing device to which the present invention is directed. In FIG. 7, 1 is a central processing unit, 2 is a channel processing unit, 3 is a main storage device, 4 is a storage control device, 5 is a first channel common control section, 6 is a second channel common control section, 7 is an individual control unit, 8 is a first microprocessor, 9 is a second microprocessor, 10 is a third microprocessor,
11 indicates channels, respectively. In the illustrated example, the channel processing device 2 has 16 channels 11, but by connecting four sets of the second common control section 6 and the individual control sections 7 to the first common control section 5, , it is possible to control up to 64 channels 11. The channel processing device 2 includes a first channel common control section 5 and a second channel common control section 6.
and an individual control section 7. The first common control section 5 is provided with a first microprocessor 8, the second common control section 6 is provided with a second microprocessor 9, and the individual control section 7 is provided with a third microprocessor. A processor 10 is provided. The first microprocessor 8 of the first common control section 5 is
Execute and decode instructions (vs. CPU), manage channel paths, load/store subchannels (vs.
MCU), IO interrupts (to CPU), etc. The second microprocessor 9 of the second common control unit 6 analyzes and executes IO instructions, loads/stores subchannels, transfers data to and from the main memory 3, reads CCW (channel command word), It has functions such as IO interrupt. The third part of the individual control unit 7
The microprocessor 10 mainly has the function of performing sequence control of the IO interface, the function of checking the on/off of the IO interface and tag-in signal and turning on/off of the tag-out signal, and the function of controlling the IO interface and tag-in signal. It has functions such as status analysis.

By the way, if a hardware failure occurs that makes it impossible to identify the channel number while the first microprocessor 8 is running, all channels 11 under its control will be It is common practice to disconnect the IO interface connected to the Otherwise, IO devices commonly used by multiple systems will remain connected to the failed system, reducing availability to other systems.

In the prior art, when a failure occurs, other I/O is transferred from the first microprocessor 8 to the second microprocessor 9 and third microprocessor 10.
Similar to the instructions, using the normal interface, notify cyclically and individually in order of channel number, and IO
The interface is separated.

[Problem to be solved]

However, the conventional method as described above has the following problems.

(a) Since a normal interface is used, it takes time to notify all channels.

(b) System reliability increases if normal interfaces are not used for failure notification.

The present invention was created in view of these points, and when a failure in which the channel number cannot be specified is detected, the IO interface can be quickly disconnected, and the reliability of the system is improved. The purpose is to provide a channel failure handling method that has become possible.

[Means for solving problems]

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 shows the configuration of a storage means for storing individual channel information. In Figure 1, 1
2 indicates a storage means. In the storage means 12,
Control information for the machine number 0 channel, control information for the machine number 1 channel, . . . , control information for the machine number F channel are stored. The individual control section 7 cyclically reads out the control information for each channel from the storage means 12 and updates it. That is, the individual control unit 7 reads the channel control information of the machine number 0 in the storage means 12 in the #0 cycle, for example, and performs the determination process in the next cycle.
Write in the next cycle, read out the machine number 1 channel control information in the storage means 12 in the #1 cycle, perform judgment processing in the next cycle, write in the next cycle, and read the machine number 1 channel control information in the storage means 12 in the #F cycle.
The channel control information of the machine number F in the storage means 12 is read out, the judgment process is performed in the next cycle, the writing is performed in the next cycle, and the channel control information of the machine number 0 in the storage means 12 is read out again in the #0 cycle, Judgment processing is performed in the next cycle, and writing is performed in the next cycle. The common control unit 6 stores the storage means 1 when necessary.
2 control information is read and written when the process is completed.

When the individual control unit 7 requests processing to the common control unit 6, the individual control unit 7 stores the request signal and the contents of the request in the control information area of each channel. continue,
Common control unit 6 when executing processing of each channel (in order)
A request is issued to. This processing request is queued. When sending a processing request from the common control section 6 to the individual control section 7, the common control section 7 stores the request signal and request contents in the control information area of each channel. Subsequently, the individual control unit 7 performs processing when executing processing for each channel.

The storage means 12 that stores control information for each channel includes a control register that can be read/written only by the individual control unit 7 that performs cyclic control in synchronization with the channel number, and a second common control unit 6. There is also a control register that can be read/written by both the individual controller 7 and the individual controller 7. For convenience, the former will be referred to as control registers and the latter as stack registers.

FIG. 2 shows the format of part of the channel-specific control information stored in the stack register. K0 OP is an abbreviation for K0 OPERATION and indicates that processing related to K0 RQ is being executed. It is the individual control unit 7 that sets K0 OP on. At this time, set K0 RQ to OFF. As instructed by the microprogram of the second microprocessor 9, the K0 OP is set off.

FIG. 3 shows the format of part of the channel-specific control information stored in the control register. K0 REQUEST CODE is individual control unit 7
These are various processing request codes from K0 REQ.
K0 Abbreviation for REQUEST, indicating that there is a request to execute various processes. K0 RQ and K1 RQ are each set to off when determining the priority, and at the same time K0
OP and K1 OP are each set to on. Note that the processing request code and processing execution request existence flag can also be written in the stack register.

FIG. 4 shows how various processing requests taken out by the individual control section are transmitted via the priority determining circuit to the second microprocessor control circuit along with the channel number and processing code.
In Fig. 4, 13-i (i=0, 1, 2...)
is a request register, 14 is a priority determination circuit, 15
1 and 2 respectively indicate the second microprocessor control circuit. Request register 13-0 stores requests belonging to K0, and request register 13-1 stores requests belonging to K0.
Requests belonging to K1 are stored in the request register 13.
-2 stores requests belonging to K2. K0,
K1, K2, etc. can be considered to indicate major classifications of processing requests. V indicates that the processing request stored in the request register is valid. Each request register 13-0, 13-1, 13-2, . . . stores a channel number and a processing request code REQ CODE. Note that a channel number synchronization control section (not shown) in the individual control section 7 performs the process of extracting a processing request from the storage means 12 and setting it in the request register. The channel number in the request register indicates which channel the request relates to. When selection permission is designated by the second microprocessor 9, the priority determination circuit 14 prioritizes processing requests stored in the request registers 13-0, 13-1, 13-2, . . . One request is selected according to the order and the selected request is output. The output from the priority determination circuit 14 is the channel number and
Consists of REQ CODE MODIFIER.
REQ CODE MODEFIER is the major classification (Ki) and
It can be thought of as consisting of REQ CODE. The output of the priority determining circuit 14 is input to a second microprocessor control circuit 15. The second microprocessor control circuit 15 can be thought of as generating an address for the control memory of the second microprocessor 9. When the second microprocessor 9 processes the processing request, it gives selection permission to the priority level verification circuit 14.

The individual control unit 7 reads the contents of the stack register and control register of the machine number N at a timing determined by the machine number N, but the second microprocessor 9
If there is a processing request for the corresponding request register, the processing request is written to the corresponding request register on the condition that the corresponding request register is empty. If it is not empty, it will wait until the next timing assigned to machine number N. This processing request is processed by the second microprocessor 9, which retrieves the control information stored in the storage means 12 (for example, channel status display, data buffer, etc.) when necessary. - pointer, etc.) and stores the processing result in the storage means 12 when the processing is completed.
write to the control information area of machine number N. If a processing request for another content occurs on the same channel, the processing that occurred after that channel is put on hold, so the priority order is determined in order of channel number. Furthermore, when multiple processing requests occur simultaneously on the same channel, priority is given according to the type. For example, processing requests for CCW FETCH during data chaining or data address conversion when a page cross occurs are better than requests for processing at the end of data transfer.
Processed with priority over CSW creation processing.

FIG. 5 is a diagram showing the configuration of one embodiment of the third microprocessor 10. In Figure 5, 16
is the third microprocessor control memory, 17 is the control memory address register, 18 is the selector, 1
9 is a shift register for holding addresses, 20 is a control storage data register, 21 is a tag-out register, 22 is a tag-in register, and 23 is a third register.
24 represents a microprocessor control circuit, and 24 represents a write register. Address register 17 specifies the address of control memory 16. After reading from the control memory 16,
The contents of address register 17 are updated and input to the right end of shift register 19. Shift register 19 has 15 register elements. The address stored in address register 17 is a microcontroller for controlling the channel with machine number N.
Assuming that the storage location of the order is specified, the address stored in the leftmost register element of the shift register 19 specifies the storage location of the micro order for controlling the channel of machine number N+1. The address stored in the next register element specifies the storage location of the micro order for controlling the channel of machine number N+2. The same applies hereafter. The content of shift register 19 is 1
Needless to say, it is shifted to the left every cycle. The selector 17 selects either the upper input or the lower input according to the value of the selection instruction signal, and stores the selected address in the address register 17.
Enter. The leftmost register element of the shift register 19 is connected to the upper input. Micro orders read from control store 16 are stored in control store data register 20. Depending on the contents of the control storage data register 20, each part of the individual control section 7 is controlled, data is written into the storage means 12, etc. The third microprocessor control circuit 23 generates a start address of a microprogram for processing a processing request from the second microprocessor 9, and stores a control storage address according to the contents of the tag-in register 21. It performs control such as updating. Write register 24
The data to be written into the storage means 12 is set in .

FIG. 6 is a time chart illustrating failure handling of the first common control unit and individual control unit according to the present invention. In FIG. 6, reference numeral 25 indicates a failure processing control unit that detects various failures. Failure processing control unit 25
Detection signals from error detection devices (not shown) installed in each part of the channel processing device 2 are inputted to the , and various hardware failures can be detected by signal line for each type. Suppose that a hardware failure in which the channel number cannot be specified is detected by the failure processing control unit 25 at time C while the first microprogram (the microprogram executed by the first microprocessor 8) is running.
This fact is notified to the third microprocessor 10 via a specific signal line, and then the fault handling control section 25 instructs the first microprocessor 8 to suspend or terminate the processing. Note that hardware failures that make it impossible to identify a channel number include, for example, a parity error in the channel number register (unable to identify the channel number), a hardware error during processing to determine the channel number (microprogram execution A hardware error is detected in a specific routine and set by a microprogram).

When notified by a specific signal line that a hardware failure that cannot be specified by a channel number has occurred, the microprocessor control circuit 23 of the third microprocessor 10 uses a control storage address generation section (not shown) to In addition to generating a fault processing execution start address, the selector 18 is controlled so that the fault processing execution start address is input to the address register 17 at a certain timing (for example, the timing assigned to channel M).
Even at timings +1, M+2, ..., M+15, the failure handling execution start address is address register 17.
After that, control is performed so that the address output from the shift register 19 is input to the address register 17. The contents of the control memory 16 specified by this failure processing execution start address are placed in a branch order so that they jump to the beginning of the microprogram routine that actually disconnects the IO interface. Machine number i (i
= 0, 1, ..., F), the fault processing execution start address is set to address register 17.
from channel i after a predetermined period of time after being set to
Selective Reset signal is sent.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the time required to notify all channels of the occurrence of a hardware failure whose channel number cannot be specified can be shortened, and system reliability can be improved. It can have a great effect.

[Brief explanation of drawings]

Figure 1 shows the configuration of the storage means for storing control information for each channel, and Figure 2 shows the stack.
FIG. 3 is a diagram showing the format of a part of channel-specific control information stored in the control register. FIG. 4 is a diagram showing the format of a part of channel-specific control information stored in the control register. FIG. The figure shows the configuration of one embodiment of the third microprocessor, FIG. 6 is a time chart illustrating failure handling of the first common control section and individual control section according to the present invention, and FIG. 1 is a diagram showing the configuration of a general computer system including a target channel processing device. 1...Central processing unit, 2...Channel processing device, 3...Main storage device, 4...Storage control device, 5
...First channel common control section, 6...Second channel common control section, 7...Individual control section, 8...First microprocessor, 9...Second microprocessor, 10... ...Third microprocessor, 11... Channel, 12... Storage means, 13
...Request register, 14...Priority determination circuit,
15...first microprocessor control circuit, 1
6...Second microprocessor control memory, 1
7... Control storage address register, 18... Selector, 19... Shift register for holding address, 20... Control storage data register, 21...
... tag-out register, 22 ... tag-in register, 23 ... third microprocessor control circuit, 24 ... write register, 25 ... failure processing control section.

Claims (1)

[Claims] 1. In a channel processing device in a general computer system, a first channel common control unit 5 including a first microprocessor 8 that commonly controls a plurality of channels; A second channel common control section 6 including a second microprocessor 9 to control the channel, and a third microprocessor 1 to control the processing of each channel cyclically and individually in order of channel number.
0, and a failure occurrence transmission means 25 for notifying the occurrence of a failure from the first channel common control unit 5 to the individual control unit 7; The first channel common control section 5 is controlled by the generation and transmission means 25.
1. A channel failure handling method, characterized in that the channel failure handling method is configured to cyclically and individually execute processing requests notified from the channel number order.