JPH01257366A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

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Publication number
JPH01257366A
JPH01257366A JP63085776A JP8577688A JPH01257366A JP H01257366 A JPH01257366 A JP H01257366A JP 63085776 A JP63085776 A JP 63085776A JP 8577688 A JP8577688 A JP 8577688A JP H01257366 A JPH01257366 A JP H01257366A
Authority
JP
Japan
Prior art keywords
gate insulating
film
insulating film
gate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63085776A
Other languages
Japanese (ja)
Other versions
JPH07109858B2 (en
Inventor
Yoshinori Asahi
朝日 良典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63085776A priority Critical patent/JPH07109858B2/en
Publication of JPH01257366A publication Critical patent/JPH01257366A/en
Publication of JPH07109858B2 publication Critical patent/JPH07109858B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To improve the performance of logic circuit part by a method wherein one of a plurality of gate insulating films is composed of an oxynitride film which has a high dielectric constant. CONSTITUTION:Gate oxide films 3 and 4 which have predetermined thicknesses are formed in element regions between field oxide films 2 on the surface of a semiconductor substrate 1. Gates 15 and 16 are provided on the gate oxide films 3 and 4 respectively. Thus two transistors Tr1 and Tr2 are formed. The thickness of the gate insulating film 3 is so predetermined as to be sufficient for high voltage application. On the other hand, the gate insulating film 4 is composed of a silicon oxynitride film and, although it has the thickness same as the gate insulating film 3, as the silicon oxynitride film has a dielectric constant than a silicon oxide film, a large gate capacitance is obtained. With this constitution, the gate insulating film 4 functions like the thinner silicon oxide film and the current driving force can be increased and the fine structure can be realized so that a high performance logic circuit can be formed.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は回路動作上の要請から異なる膜厚のゲート絶縁
膜が要求される半導体装置、例えばメモリ回路とロジッ
ク回路とを有する半導体装置、およびその製造方法に関
する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is applicable to semiconductor devices that require gate insulating films of different thicknesses due to circuit operation requirements, such as memory circuits and logic circuits. The present invention relates to a semiconductor device having the present invention and a method for manufacturing the same.

(従来の技術) 半導体装置の高集積化、高速処理化などの要求からゲー
ト絶縁膜の膜厚は薄くなる傾向にある。
(Prior Art) Due to demands for higher integration and faster processing of semiconductor devices, the thickness of gate insulating films tends to become thinner.

しかし、ゲート絶縁膜の膜厚とゲート酸化膜に印加する
ことができる電圧は相互に関連しており、高電圧を印加
する場合にはゲート絶縁膜の膜厚を厚くする必要がある
。例えば、ダイナミックRAMにおいては、メモリ回路
部のキャパシター蓄積電荷を保証するため、ワード線に
印加する電圧Vを電源電圧(V DD)よりも高(する
ワード線ブースト方式が採用されており、この高電圧V
が印加されるトランジスタのゲート絶縁膜を厚くして、
その信頼性の確保が行われている。従ってダイナミック
RAMを構成する半導体チップではロジック回路のみか
ら構成される半導体チップに比べてゲート絶縁膜の膜厚
が厚くなっている。
However, the thickness of the gate insulating film and the voltage that can be applied to the gate oxide film are interrelated, and when applying a high voltage, it is necessary to increase the thickness of the gate insulating film. For example, in dynamic RAM, a word line boost method is adopted in which the voltage V applied to the word line is made higher than the power supply voltage (V DD) in order to guarantee the charge stored in the capacitor in the memory circuit. Voltage V
By thickening the gate insulating film of the transistor to which is applied,
Its reliability is being ensured. Therefore, in a semiconductor chip that constitutes a dynamic RAM, the thickness of the gate insulating film is thicker than that in a semiconductor chip that consists only of logic circuits.

(発明が解決しようとする課題) このようにメモリ回路とロジック回路とを有する従来の
半導体チップでは、メモリ回路に要求されるゲート絶縁
膜信頼性の点からゲート酸化膜を厚く設定するために、
ロジック回路部にも同一厚のゲート絶縁膜を用いようと
すると、ロジック回路部のトランジスタの微細化が困難
となり、またトランジスタの駆動力が低下することによ
りロジック回路部の高性能化を阻害する。また、ゲート
絶縁膜厚をメモリ回路部とロジック回路部とで変えよう
とすると、ゲート絶縁膜をエツチングした後薄いゲート
絶縁膜を形成しなければならず、その膜厚制御が難しい
(Problems to be Solved by the Invention) As described above, in conventional semiconductor chips having a memory circuit and a logic circuit, in order to set the gate oxide film thick from the viewpoint of gate insulating film reliability required for the memory circuit,
If it is attempted to use a gate insulating film of the same thickness also in the logic circuit section, it becomes difficult to miniaturize the transistors in the logic circuit section, and the driving force of the transistors decreases, which impedes the high performance of the logic circuit section. Furthermore, if the thickness of the gate insulating film is to be changed between the memory circuit section and the logic circuit section, a thin gate insulating film must be formed after etching the gate insulating film, making it difficult to control the film thickness.

本発明は上記事情を考慮してなされたもので、ロジック
回路部の高性能化を図るため、実際の膜厚は同一であっ
ても実効的には異なる膜厚のゲート絶縁膜を同一チップ
上に形成した半導体装置と、そのための製造方法を提供
することを目的とする。
The present invention has been made in consideration of the above circumstances, and in order to improve the performance of the logic circuit section, gate insulating films of different thicknesses are effectively formed on the same chip even though the actual film thickness is the same. An object of the present invention is to provide a semiconductor device formed in the same manner and a manufacturing method therefor.

〔発明の構成〕[Structure of the invention]

(課題を解決するための手段) 上記目的を達成するため、本発明は、単一の半導体チッ
プの半導体基板上に形成された複数のゲート絶縁膜の内
、一方がシリコン酸化膜からなり、他方がシリコンオキ
シナイトライド膜であることを特徴とする半導体装置を
提供する。
(Means for Solving the Problems) In order to achieve the above object, the present invention provides that, among a plurality of gate insulating films formed on a semiconductor substrate of a single semiconductor chip, one is made of a silicon oxide film and the other is made of a silicon oxide film. Provided is a semiconductor device characterized in that is a silicon oxynitride film.

又、この半導体装置の製造方法として、半導体基板上に
シリコン酸化膜により成る複数のゲート絶縁膜を形成す
る工程と、シリコン酸化膜上にマスキング層を形成し、
その一部を除去して一部のゲート絶縁膜を露出させる工
程と、露出したゲート絶縁膜を窒化してシリコンオキシ
ナイトライド膜とする工程とを備えることを特徴とする
半導体装置の製造方法を提供する。
Further, the method for manufacturing this semiconductor device includes the steps of forming a plurality of gate insulating films made of silicon oxide films on a semiconductor substrate, forming a masking layer on the silicon oxide film,
A method for manufacturing a semiconductor device comprising the steps of: removing a part of the gate insulating film to expose a part of the gate insulating film; and nitriding the exposed gate insulating film to form a silicon oxynitride film. provide.

(作 用) 本発明に係る半導体装置では、オキシナイトライド化し
たゲート絶縁膜は元のシリコン酸化膜のゲート絶縁膜よ
り比誘電率が高いため、実際の膜厚は同じでも、実効的
に膜厚の薄いシリコン酸化膜のゲート絶縁膜と同様に機
能する。従って、ロジック回路部にオキシナイトライド
化したゲート絶縁膜を採用すれば、ロジック回路部の性
能が向上する。
(Function) In the semiconductor device according to the present invention, the oxynitride gate insulating film has a higher dielectric constant than the original silicon oxide gate insulating film, so even though the actual film thickness is the same, the effective film thickness is It functions similarly to a thin silicon oxide gate insulating film. Therefore, if an oxynitride gate insulating film is used in the logic circuit section, the performance of the logic circuit section will be improved.

又、本発明に係る製造方法ではオキシナイトライド膜と
シリコン酸化膜とを同一の半導体チップに形成すること
ができる。
Further, in the manufacturing method according to the present invention, an oxynitride film and a silicon oxide film can be formed on the same semiconductor chip.

(実施例) 以下、本発明を添付図面を参照して具体的に説明する。(Example) Hereinafter, the present invention will be specifically described with reference to the accompanying drawings.

第1図は本発明の一実施例の半導体装置の断面図を示す
。半導体基板1表面のフィールド酸化膜2間の素子領域
に所定膜厚のゲート酸化膜3.4が形成されている。各
ゲート酸化膜3.4下にはソース・ドレイン拡散層10
が設けられ、このソース・ドレイン拡散層10には電極
(アルミニウム電極)12が接続されている。ゲート酸
化膜3゜4上にはゲート15.16が設けられている。
FIG. 1 shows a sectional view of a semiconductor device according to an embodiment of the present invention. A gate oxide film 3.4 having a predetermined thickness is formed in the element region between the field oxide films 2 on the surface of the semiconductor substrate 1. Under each gate oxide film 3.4 is a source/drain diffusion layer 10.
is provided, and an electrode (aluminum electrode) 12 is connected to this source/drain diffusion layer 10. Gates 15 and 16 are provided on the gate oxide film 3.4.

こうして、2つのトランジスタTr1およびTr2が形
成されている。このトランジスタT「1゜Tr2の内、
一方のトランジスタTriは例えばメモリ回路を構成し
、他方のトランジスタTr2は例えばロジック回路を構
成する。そして、トランジスタTriのゲート絶縁膜3
はシリコン酸化膜からなっており、トランジスタTr2
のゲート絶縁膜4はシリコンオキシナイトライド膜から
なっている。ゲート絶縁膜3は高電圧印加が可能な厚み
に設定されており、このゲート絶縁膜3を有するトラン
ジスタTriは信頼性の高いメモリ回路を構成する。一
方、シリコンオキナイトライド膜からなるゲート絶縁膜
4はゲート絶縁膜3と同一の膜厚を有しているが、比誘
電率がシリコン酸化膜よりも高いため、ゲート容量が大
きくなっている。従って、薄い膜厚のシリコン酸化膜と
同様に機能し、電流駆動力の増大および微細化が可能と
なるため、高性能なロジック回路が構成できる。
In this way, two transistors Tr1 and Tr2 are formed. This transistor T "1° Tr2,
One transistor Tri constitutes, for example, a memory circuit, and the other transistor Tr2 constitutes, for example, a logic circuit. Then, the gate insulating film 3 of the transistor Tri
is made of a silicon oxide film, and the transistor Tr2
The gate insulating film 4 is made of a silicon oxynitride film. The gate insulating film 3 is set to have a thickness that allows application of a high voltage, and the transistor Tri having this gate insulating film 3 constitutes a highly reliable memory circuit. On the other hand, the gate insulating film 4 made of a silicon oxynitride film has the same thickness as the gate insulating film 3, but has a higher relative dielectric constant than the silicon oxide film, and thus has a larger gate capacitance. Therefore, it functions in the same way as a thin silicon oxide film, and it is possible to increase current driving power and miniaturize the structure, so that a high-performance logic circuit can be constructed.

次に、本発明の製造方法を第2図により説明する。Next, the manufacturing method of the present invention will be explained with reference to FIG.

半導体基板1上にフィールド反転防止層を形成した後、
選択酸化法によってフィールド酸化膜2を形成する。こ
の後、フィールド酸化膜2間の素子領域にシリコン酸化
膜からなるゲート絶縁膜3゜4を成長させ、このゲート
絶縁膜3.4下の基板領域にイオン注入を行って不純物
領域13.14を形成する。この不純物領域13.14
はトランジスタTri、Tr2のしきい値電圧(V T
)i)調整およびバンチスルー耐圧向上に寄与する。不
純物領域13.14形成の後、全面に多結晶シリコン5
を所定厚さで堆積させる(第2図(a))。
After forming the field reversal prevention layer on the semiconductor substrate 1,
A field oxide film 2 is formed by selective oxidation. Thereafter, a gate insulating film 3.4 made of a silicon oxide film is grown in the device region between the field oxide films 2, and ions are implanted into the substrate region under this gate insulating film 3.4 to form impurity regions 13.14. Form. This impurity region 13.14
is the threshold voltage (V T
) i) Contributes to improvement of adjustment and bunch-through withstand voltage. After forming impurity regions 13 and 14, polycrystalline silicon 5 is applied to the entire surface.
is deposited to a predetermined thickness (FIG. 2(a)).

次に多結晶シリコン5上にフォトレジストパターンを形
成し、これをマスクとしてトランジスタ一方のゲート絶
縁膜4上の多結晶シリコン層5を除去してゲート絶縁膜
4を露出させる(同図(b))。既述のようにゲート絶
縁膜4はロジック回路を構成するトランジスタTr2の
ゲート絶縁膜であり、これを次にオキシナイトライド化
する。オキシナイトライド化の方法としては、熱窒化あ
るいはプラズマ窒化などの適当な方法が採用できる。こ
のオキシナイトライド化により、ゲート絶縁膜4はシリ
コン酸化膜からシリコンオキシナイトライド膜に変化し
、比誘電率が増大する。
Next, a photoresist pattern is formed on the polycrystalline silicon 5, and using this as a mask, the polycrystalline silicon layer 5 on the gate insulating film 4 on one side of the transistor is removed to expose the gate insulating film 4 (FIG. 4(b)). ). As described above, the gate insulating film 4 is the gate insulating film of the transistor Tr2 constituting the logic circuit, and is then converted into oxynitride. As a method for oxynitriding, an appropriate method such as thermal nitriding or plasma nitriding can be adopted. By this oxynitride conversion, the gate insulating film 4 changes from a silicon oxide film to a silicon oxynitride film, and the dielectric constant increases.

なお、オキシナイトライド化に際しては多結晶シリコン
層5表面にも窒化!l1k7が形成されるが、多結晶シ
リコン層5で覆われたゲート酸化膜3はオキシナイトラ
イド化されることがない(同図(C))。
In addition, when converting to oxynitride, the surface of the polycrystalline silicon layer 5 is also nitrided! 11k7 is formed, but the gate oxide film 3 covered with the polycrystalline silicon layer 5 is not converted into oxynitride (FIG. 3(C)).

続いて、露出したゲート絶縁膜4表面を含む全表面に多
結晶シリコン8を堆積し、その上に多結晶シリコンと同
一のエツチング速度を有するレジスト9を堆積させて表
面を平坦化する(同図(d))。そして、このレジスト
9および多結晶シリコン8をエッチバックし、さらに窒
化層7をエツチング除去した後、残った多結晶シリコン
8゜5にリン拡散を行い、次いで多結晶シリコン8゜5
をバターニングをしてゲート15.16を形成する(同
図(e))。
Subsequently, polycrystalline silicon 8 is deposited on the entire surface including the exposed surface of the gate insulating film 4, and a resist 9 having the same etching rate as the polycrystalline silicon is deposited thereon to flatten the surface (see FIG. (d)). After etching back the resist 9 and polycrystalline silicon 8 and etching away the nitride layer 7, phosphorus is diffused into the remaining polycrystalline silicon 8.5.
are patterned to form gates 15 and 16 (FIG. 1(e)).

その後は、第1図のようにイオン注入によってソース・
ドレイン拡散層10を形成し、絶縁膜11を堆積した後
、絶縁膜11を開孔してその開孔部に電極12を形成す
る。これにより、シリコン酸化膜からなるゲート絶縁膜
3を有するトランジスタTriとシリコンオキシナイト
ライド膜からなるゲート絶縁膜4ををするトランジスタ
Tr2とを単一の半導体チップ上に形成することができ
る。
After that, as shown in Figure 1, the source is
After forming the drain diffusion layer 10 and depositing the insulating film 11, a hole is formed in the insulating film 11 and an electrode 12 is formed in the hole. Thereby, the transistor Tri having the gate insulating film 3 made of a silicon oxide film and the transistor Tr2 having the gate insulating film 4 made of a silicon oxynitride film can be formed on a single semiconductor chip.

このような製造方法ではゲート絶縁膜4をエツチングし
て薄い膜厚とする工程が不要となるため膜厚の制御性が
良好となる。又、ゲート絶縁膜4〜のオキシナイトライ
ド化により、多結晶シリコンからゲート絶縁膜を介して
の基板内への不純物拡散を抑制することができる。
Such a manufacturing method eliminates the need for the step of etching the gate insulating film 4 to make it thinner, resulting in better controllability of the film thickness. Further, by converting the gate insulating film 4 to oxynitride, diffusion of impurities from polycrystalline silicon into the substrate through the gate insulating film can be suppressed.

〔発明の効果〕 以上のように本発明は、複数のゲート絶縁膜の内の一部
を比誘導率の高いオキシナイトライド膜としたので、そ
のトランジスタの電流駆動力の増大および微細化が可能
である一方、他のゲート酸化膜の高電圧印加に対する信
頼性を保証することができる。又、本発明の製造方法は
シリコン酸化膜をオキシナイトライド化してシリコンオ
キシナイトライド膜とし、薄い膜厚を形成する工程を不
要とするため、膜厚制御性が良好となる。
[Effects of the Invention] As described above, the present invention uses an oxynitride film with a high specific inductivity as part of the plurality of gate insulating films, so that it is possible to increase the current driving power of the transistor and to miniaturize it. On the other hand, the reliability of other gate oxide films against high voltage application can be guaranteed. Further, the manufacturing method of the present invention converts a silicon oxide film into an oxynitride film to obtain a silicon oxynitride film, and eliminates the need for a step of forming a thin film, resulting in good film thickness controllability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の半導体装置を示す断面図、
第2図はその製造工程を示す断面図である。 1・・・半導体基板、3・・・シリコン酸化膜、4・・
・シリコンオキシナイトライド膜、5.8・・・多結晶
シリコン層、15.16・・・ゲート。 出願人代理人  佐  藤  −雄 Tri       Tr2 罠1 図 罠2図
FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a sectional view showing the manufacturing process. 1... Semiconductor substrate, 3... Silicon oxide film, 4...
- Silicon oxynitride film, 5.8... Polycrystalline silicon layer, 15.16... Gate. Applicant's representative Sato-Yo Tri Tr2 Trap 1 Figure Trap 2 Figure

Claims (1)

【特許請求の範囲】 1、単一の半導体チップの半導体基板上に形成された複
数のゲート絶縁膜の内、一方がシリコン酸化膜からなり
、他方がシリコンオキシナイトライド膜であることを特
徴とする半導体装置。 2、半導体基板上にシリコン酸化膜により成る複数のゲ
ート絶縁膜を形成する工程と、 シリコン酸化膜上にマスキング層を形成し、その一部を
除去して一部のゲート絶縁膜を露出させる工程と、 露出したゲート絶縁膜を窒化してシリコンオキシナイト
ライド膜とする工程と を備えることを特徴とする半導体装置の製造方法。
[Claims] 1. Among the plurality of gate insulating films formed on the semiconductor substrate of a single semiconductor chip, one is made of a silicon oxide film and the other is a silicon oxynitride film. semiconductor devices. 2. A step of forming a plurality of gate insulating films made of silicon oxide on a semiconductor substrate, and a step of forming a masking layer on the silicon oxide film and removing a part of the masking layer to expose a part of the gate insulating film. and nitriding the exposed gate insulating film to form a silicon oxynitride film.
JP63085776A 1988-04-07 1988-04-07 Method for manufacturing semiconductor device Expired - Fee Related JPH07109858B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63085776A JPH07109858B2 (en) 1988-04-07 1988-04-07 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63085776A JPH07109858B2 (en) 1988-04-07 1988-04-07 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH01257366A true JPH01257366A (en) 1989-10-13
JPH07109858B2 JPH07109858B2 (en) 1995-11-22

Family

ID=13868284

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH07109858B2 (en)

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WO2002063668A1 (en) * 2001-02-06 2002-08-15 Matsushita Electric Industrial Co., Ltd. Method of forming insulating film and method of producing semiconductor device
US6699776B2 (en) 1998-12-22 2004-03-02 Kabushiki Kaisha Toshiba MOSFET gate insulating film and method of manufacturing the same

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JPS582071A (en) * 1981-06-25 1983-01-07 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS6116576A (en) * 1984-07-03 1986-01-24 Ricoh Co Ltd Manufacture of semiconductor device
JPS6358959A (en) * 1986-08-29 1988-03-14 Mitsubishi Electric Corp Field-effect type semiconductor device with capacitor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02237153A (en) * 1989-03-10 1990-09-19 Fujitsu Ltd Volatile semiconductor memory device
US6335549B1 (en) * 1993-11-02 2002-01-01 Mitsubishi Denki Kabushiki Kaisha EEPROM with high channel hot carrier injection efficiency
US6483133B2 (en) 1993-11-02 2002-11-19 Mitsubishi Denki Kabushiki Kaisha EEPROM with high channel hot carrier injection efficiency
US6699776B2 (en) 1998-12-22 2004-03-02 Kabushiki Kaisha Toshiba MOSFET gate insulating film and method of manufacturing the same
WO2002063668A1 (en) * 2001-02-06 2002-08-15 Matsushita Electric Industrial Co., Ltd. Method of forming insulating film and method of producing semiconductor device
JP2002314074A (en) * 2001-02-06 2002-10-25 Matsushita Electric Ind Co Ltd Method for forming insulating film and method for manufacturing semiconductor device
US6734069B2 (en) 2001-02-06 2004-05-11 Matsushita Electric Industrial Co., Ltd. Method of forming a high dielectric constant insulating film and method of producing semiconductor device using the same

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