JPH01259559A - Charge coupled device - Google Patents

Abstract

PURPOSE:To decrease the plunge of pulse applied to reset gate electrodes and a CCD gate electrode, by connecting the high-concentration impurity layer of a charge-coupled signal charge detecting part through the gate part of a detecting switch element and a low-concentration impurity layer. CONSTITUTION:The high-concentration impurity layer 6 of an electric charge detecting part 3 is connected through the channel part 8 of an adjacent gate electrode 4 and a low-concentration impurity layer 12. Therefore, the reference electric potential of the electric charge detecting part 3 is never affected by the changes of the voltage of a reset drain 5 and the high-concentration impurity layer 6 has no coupling capacity with the adjacent reset gate 4 and an output gate 2. This suppresses the plunge of pulse applied to the reset gate 4 and the influence of the pulse applied to CCD gate electrodes 1 plunging through the output gate 2 to obtain a stable electric charge detecting device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a charge-coupled device (hereinafter abbreviated as COD) that can be used in video cameras, delay lines, etc., and specifically relates to the structure of its charge detection section. be.

BACKGROUND OF THE INVENTION In recent years, due to rapid advances in semiconductor technology, COD has become smaller and more dense, and has come to be used in integrated video cameras, facsimiles, and the like.

FIG. 5 shows a plan view of a charge detection section of a conventional charge-coupled device. 1 is the CCD gate electrode that constitutes the COD, 2 is the CO
3 is an output gate electrode that outputs the charge carried by D to the charge detection section; 3 is a charge detection section that converts the charge into voltage; 4 is a reset gate electrode that provides a reference potential to the charge detection section 3; 5
is a reset drain that provides a reference potential to the charge detection section 3.

Further, FIG. 6 is a cross-sectional structural diagram taken along line AA' in FIG. 5. In FIG. 6, 1 to 5 are the same as 1 to 5 in FIG.
D gate electrode 1. Output gate electrode 2. A low concentration impurity layer 9 constitutes a channel portion of the reset gate electrode 4, and a substrate.

The operation of the charge-coupled device configured as described above will be described below with reference to the potential diagram in FIG. 7 and the application pulse timing diagram in FIG. 8.

FIG. 7 shows the potential distribution at the tl and t2 timings when the voltage shown in FIG. 8 is applied to each part shown in FIGS. 5 and 6. FIG. In Figure 7, 10.11 is CCD
indicates the signal charge that has been transferred. At the timing t1 in FIG. 8, the CCD gate electrode 1 and the reset gate electrode 4 are at a low voltage.

When the reset gate electrode 4 becomes a low voltage, the high concentration impurity layer 6 and the high concentration impurity layer 7 are separated, and when the CCD gate voltage 1 becomes a low voltage, the signal charge 10 is transferred to the channel part of the CCD gate electrode 1. It is transferred to the high concentration impurity layer 6 through the channel portion of the output gate electrode 2. At this time, since the high-concentration impurity layer 6 and the high-concentration impurity layer 7 are separated, the potential of the high-concentration impurity layer 6 is modulated by the transferred charge and is detected through the charge detection section 3. Next, in FIG. 8, at timing t2, the CCD gate electrode 1 and the reset gate electrode 4 are at a high voltage. By applying a high voltage to the reset gate electrode 4, the high concentration impurity layer 6 and the high concentration impurity layer 7 are connected, and the signal charges 10 existing in the high concentration impurity layer 6 are transferred to the channel portion of the reset gate electrode 4, and the high concentration impurity layer 7 is connected. The signal charge 10 is transferred to the reset drain 5 through the high concentration impurity layer 7, and the high concentration impurity layer 6 becomes the voltage applied to the reference potential reset drain 5 before the signal charge 10 is transferred.At this time, the CCD gate electrode 1 It has a high potential and accumulates the signal charge 11 transferred from the CCD gate electrode in the previous stage.

After that, by repeating each timing of jl+j2,
Detection of signal charges is performed.

Problems to be Solved by the Invention However, in the above configuration, the coupling capacitance existing between the reset gate electrode 4 and the high concentration impurity layer 6, and the coupling capacitance existing between the CCD gate electrode 1 and the output gate electrode 2.
Due to the coupling capacitance existing between the output gate electrode 2 and the high concentration impurity layer 6, the reset gate electrode 4 and C
The pulse applied to the CD gate electrode 1 jumps into the high concentration impurity layer 6 and modulates the potential of the charge detection section 3.

Further, there was a problem in that fluctuations in the reset drain voltage directly caused fluctuations in the reference potential of the charge detection section.

In view of the above-mentioned problems, the present invention provides reset gate electrode 4 and C
By reducing the jump of pulses applied to the CD gate electrode 1, the charge detection section 3 detects the pulses applied to other electrodes.
This provides a CCD that is less likely to be modulated.

Means for Solving the Problems In order to solve the above problems, the charge-coupled device of the present invention has the following features:
The highly concentrated impurity layer of the charge-coupled signal charge detection section is
This is a CCD configured to be connected to the gate portion of the detection switch element via a low concentration impurity layer.

Function: With this configuration, it is possible to realize a CCD having a stable charge detection section in which the pulses applied to the reset gate electrode 4 and the CCD gate electrode 1 are less likely to jump.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a charge detection section in a CCD according to an embodiment of the present invention, and FIG. 2 is a cross-sectional structural diagram taken along line AA' in FIG. 1.

In FIGS. 1 and 2, the CCD gate electrode 1, output gate electrode 2, charge detection section 3, reset gate electrode 4, and reset drain 5 are the same as in FIG. In FIG. 2, reference numeral 6 denotes a high concentration impurity layer which forms a main part of the charge detection section 3, and the high concentration impurity layer 6 of the conventional example shown in FIG. while being apart from it. 7 is a high concentration impurity layer, 8
7 is a low concentration impurity layer, 9 is a substrate, and 7 to 9 are the same as the conventional example shown in FIG. A low concentration impurity layer 12 is provided between the high concentration impurity layer 6 and the channel portion of the adjacent gate electrode.

The operation of the charge detection device configured as described above will be described below with reference to the potential diagram in FIG. 3 and the applied pulse timing diagram in FIG. 4.

The potential distribution at timings 11 and t2 when the voltages shown in FIGS. 3 and 4 are applied to each part shown in FIGS. 1 and 2 is shown. In Figure 3, 10.11 is a CCD
indicates the signal charge that has been transferred. At the timing t1 in FIG. 4, the CCD gate electrode 1 and the reset gate electrode 4 are at a low voltage. By lowering the voltage of the reset gate electrode 4, the high concentration impurity layer 6 and the low concentration impurity layer 1
2 is electrically separated from the high concentration impurity layer 7.

Further, as the voltage of the CCD electrode 1 becomes low, signal charges are transferred to the region of the high concentration impurity layer 6 and the low concentration impurity layer 12, and a voltage change is detected through the charge detection section 3.

At the next timing t2 in FIG. 4, the CCD gate electrode 1 and the reset gate electrode 4 are at high voltage. By applying a high voltage to the reset gate electrode 4, the signal charges 1 existing in the high concentration impurity layer 6 and the low concentration impurity layer 12 are removed.
0 is transferred to the reset drain through the channel part of the reset gate electrode 4 and the high concentration impurity layer 7, and the potentials of the high concentration impurity layer 6 and the low concentration impurity layer 12 become the reference potential before the signal charge 10 is transferred. However, this reference potential is not determined by the voltage applied to the reset drain 5 as shown in the conventional example, but is determined by the depletion voltage of the low concentration impurity layer.At this time, the CCD gate electrode 1 is at a high potential. After the signal charges 11 transferred from the previous CCD gate electrode are accumulated, the signal charges are detected by repeating the timings t1 and t2.

As described above, with this configuration, the reference potential of the charge detection section is not affected by the voltage fluctuation of the reset drain 5 at all, and the high concentration impurity layer has a coupling capacitance with the adjacent reset gate 4 and output gate 2. Therefore, the effect of the pulses applied to the reset gate 4 and the pulses applied to the CCD gate electrode 1 passing through the output gate 2 can be suppressed, and a stable charge detection device can be realized.

Effects of the Invention As described above, the present invention has a configuration in which the high-concentration impurity layer of the charge detection section is connected to the channel section of the adjacent gate electrode via the low-concentration impurity layer, thereby reducing the influence of applied pulses. Moreover, it is possible to realize a stable charge detection device that is completely unaffected by the voltage fluctuations of the reset drain 5, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the main parts of an embodiment of the device of the present invention, and FIG.
The figure is a cross-sectional structure diagram taken along line A-A' in Figure 1, Figure 3 is a potential diagram during operation of the device of the present invention, Figure 4 is a diagram of applied pulse timing during operation of the device of the present invention, and Figure 5 6 is a plan view showing the main parts of the conventional device, and FIG. 6 is taken along A-A in FIG.
7 is a potential diagram during operation of the conventional device, and FIG. 8 is an applied pulse timing diagram during operation of the conventional device. 1... CCD gate electrode, 2... Output gate electrode, 3... Charge detection section, 4...
・Reset gate electrode, 5...Reset drain, 6...High concentration impurity layer, 7...High concentration impurity layer, 8...Low concentration impurity layer , 9...
...Substrate, 10...Signal charge, 11...
...Signal charge, 12...Low concentration impurity layer. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 1-CCD Boo F! Figure 2 Figure 3 Figure 4 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] A charge detection section that converts the charge-transferred signal charge into a voltage is provided with a highly-concentrated impurity layer at a position away from the gate section of the readout switch element, and the gate section and the gate section are provided in a peripheral portion of the high-concentration impurity layer. A charge coupled device comprising a low concentration impurity layer of the same conductivity type as the high concentration impurity layer in contact with the high concentration impurity layer.