JPH01261925A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To secure the stable and high speed action of a semiconductor IC by providing a second holding means which holds a logical level signal at the timing of a clock signal and which outputs the holding value to a holding means. CONSTITUTION:The holding circuit 27 consisting of TTR25 and an invertor 26 is provided immediately before the holding circuit 24 consisting of a transfer transistor(TTR)21 and an invertor 23. When the clock signal phi is inputted to the gate of TTR25, an input signal IN is transmitted to the circuit 24 through the circuit 27. At that time, the transfer timing of TTR21 is delayed from the signal but the timing that the signal IN is held by the circuit 27 coincides with the rise of the signal phi. Namely, prescribed non-overlap is secured between the timing that the logical level of the signal IN is decided and that of the signal phi. Even if non-overlap between the transfer timing of TTR21 and the signal phi reduces, transmission data of TTR21 is data decided in the circuit 27, and the logical level of the signal IN which is always decided is held in the circuit 24.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 6 to 8) Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems (1) Basics of the Invention Principle (Figures 1 to 3) (2) First embodiment of the present invention (Figure 4) (3) Second embodiment of the present invention (Figure 5) Effects of the invention [Summary] Large-scale semiconductor integrated circuit In this regard, the present invention aims to provide a semiconductor integrated circuit that ensures stable high-speed operation, and includes a holding means for holding a signal at a predetermined logic level based on the timing of a predetermined clock signal when a signal of a predetermined logic level is input. In the semiconductor integrated circuit, a second holding means is provided before the holding means for holding the logic level signal at the timing of the clock signal and outputting the held value to the holding means.

[Industrial application field]

Recently, many large-scale semiconductor integrated circuits with a large number of integrated elements have been realized, and in particular, semiconductor integrated circuits that handle digital signals tend to have higher integration and faster processing speeds as applications expand. It is in.

By the way, when dealing with digital signals, the timing of signal processing is important, and it is necessary to process various signals at predetermined timings. In particular, when high-speed processing operations are required, minute timing settings are required; for example,
In some cases, a delay of several nanoseconds becomes a problem, and advanced technology is required to match the timing at the circuit design stage with the actual operating timing of the semiconductor integrated circuit. In other words, the main causes of signal delay are the effects of the delay time constant made up of the wiring resistance and distributed capacitance between the elements that make up the semiconductor integrated circuit, and the response delay of the elements themselves, but the signal delay time ( (delay time) may vary due to changes in ambient temperature or variations in elements.

Therefore, in order to operate a semiconductor integrated circuit at a predetermined timing, it is necessary to design a circuit that takes into account the signal delay time and its fluctuations in advance, and especially when high-speed operation is required, it is necessary to design a circuit that takes into account the delay time of the signal and its fluctuations. Even minute signal delays cannot be ignored.

Additionally, the proportion of delay time in operating speed increases as the operating speed increases, so semiconductor integrated circuits that operate stably and at high speed without causing racing or hazards even when operating timing fluctuates. It has been demanded.

[Conventional technology]

Examples of such conventional semiconductor integrated circuits include those shown in FIGS. 6 to 8, for example.

FIG. 6 is a diagram showing a first conventional example.

In the figure, a signal input to an N-channel (Nch) transfer transistor l is transmitted to an inverter 2 according to a clock signal φ1, and the output of the inverter 2 is
It is held by the input capacitance of the inverter 4 via the transfer transistor 3 of the channel. That is, when clock signal φ is at H level, transfer transistor 1
is turned on, so if the input signal IN is at H level, this signal charges (precharges) the input capacitance of the inverter 2. Signal transmission by transfer transistor 3 is performed according to the output of AND gate 5, and the output of AND gate 5 is controlled according to the timing of clock signal φ2. As shown in FIG. 7, the timing of the clock signal φ2 is set so that the clock signal φ is at the H level during the positive level period, and the clock signal φ1 and the clock signal φ2 are both at the L level (hereinafter referred to as the non-level period). (referred to as overlap) tI % L2 is set.

That is, when clock signal φ2 becomes H level, transfer transistor 3 is turned on and the output of inverter 2 is transmitted to inverter 4. The output of impark 4 is N
The output of the inverter 4 is held by the input capacitance of the inverter 7 because the transfer transistor 6 is turned on when the clock signal φ1 becomes H level.

That is, transfer transistor 3 is connected to inverter 2
Transfer transistor 6 transmits the output of inverter 4 to inverter 7 after the output of inverter 4 is determined.

FIG. 8 is a diagram showing a second conventional example, and the same constituent members as those in the conventional example shown in FIG. 6 are given the same reference numerals and their explanations will be omitted.

In the same figure, a data bus 11 is connected to the input of the transfer transistor 3, and the data bus 11 is precharged by a P-channel transistor 12 according to a clock signal, and the output of an AND gate 13 to which a clock signal φ2 is input. Accordingly, it is discharged by the N-channel transistor 14. That is,
The transfer transistor 3 transmits the data to the inverter 4 after the data on the data bus 11 is determined, and a non-overlapping portion as shown in FIG. 7 is provided at the timing of the clock signal φ1 and the clock signal φ2. There is.

[Problem to be solved by the invention]

However, in such a conventional semiconductor integrated circuit, since the transfer transistor 3 is configured to transmit a signal from the previous stage based on the clock signal φ2 inputted to the AND gate 5, the circuit operation becomes unstable. The problem was that it was easy to become

That is, since the clock signal φ2 is input to the gate of the transfer transistor 3 via the AND gate 5, a signal delay occurs between the input and output of the AND gate 5 depending on the response speed of the element. Further, since there is a delay time constant due to wiring resistance and distributed capacitance between the AND gate 5 and the transfer transistor 3, a delay also occurs in the input timing of the transfer transistor 3 with respect to the output timing of the AND gate 5.

Therefore, since the actual transfer operation by the transfer transistor 3 is delayed from the timing of the clock signal φ2, it is necessary to set the non-overlapping portions of the clock signal φ2 and the clock signal φ2 in consideration of these delays.

However, even if a non-overlapping portion is set in anticipation of a delay in advance, the rising and falling edges of the signal are distorted by the delay, so the actual non-overlapping width may become narrow due to the influence of the threshold level. In particular, when high-speed operation is intended, the above-described problem is noticeable, and the narrow non-overlapping width makes hazards or racing more likely to occur. In addition, in high-speed operation, the ratio of delay time to operation speed increases as the operation speed increases, and the actual delay time becomes extremely small, so it is difficult to accurately predict fluctuations in non-overlap width. This becomes difficult. Therefore, when considering fluctuations due to changes in ambient temperature, unevenness of elements, etc., it is often difficult to secure a predetermined non-overlapping width that can avoid hazards and racing. In this case, there is a high possibility that the semiconductor integrated circuit will operate in a manner different from the intended operation due to the occurrence of hazards or racing, resulting in a decrease in the stability of circuit operation during high-speed operation. For example, when racing occurs in the circuit shown in FIG. 6.8, in the former case, the transfer transistor 3
Alternatively, by turning on the transfer transistor 6, uncertain data is transmitted to the subsequent stage. Furthermore, in the latter case, uncertain data during precharging of the data bus 11 is similarly transmitted to the subsequent stage.

Furthermore, due to layout considerations in large-scale semiconductor integrated circuits, the distance between elements may increase, leading to an increase in the delay time constant. In such cases, it becomes difficult to ensure a non-overlamp width. There is also.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit that ensures stable high-speed operation.

[Means to solve the problem]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention is provided with a holding means for holding a signal of a predetermined logic level based on the timing of a predetermined clock signal when a signal of a predetermined logic level is input manually. A second holding means is provided upstream of the holding means for holding the logic level signal at the timing of the clock signal and outputting the held value to the holding means.

[Effect]

In the present invention, after a signal of a predetermined logic level is held in advance by the second holding means at the timing of a clock signal,
The signal is held by the holding means based on the timing of the clock signal.

Therefore, the signal held by the holding means becomes an already determined signal held in advance by the second holding means, and the occurrence of racing is avoided and stability of high-speed operation is ensured.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

First, the configuration will be explained. First, the basic principle of the present invention will be described with reference to FIGS. 1 to 3.

In FIG. 1, transfer transistor 21 guides input signal IN to inverter 23 based on the output of AND gate 22, and the input capacitance of inverter 23 maintains the logic level of the input signal.

A clock signal φ is input to the AND gate 22, and a signal instructing the transfer operation of the transfer transistor 2'1 appears at the output of the AND gate 22 while the clock signal φ is at the H level. For example, input signal I
When the input signal EN of the N and AND gate 22 is at the H level and the clock signal φ goes to the H level, the output of the AND gate 22 goes to the H level only while the clock signal Φ is at the H level.
become the level. In this case, the AND gate 22 output is AN
The response speed of the D gate 22 is delayed in its response to the input. In addition, as described above, there is an effect of the delay time constant determined by the product of the distributed capacitance including the wiring resistance from the output of the AND gate 22 to the gate of the transfer transistor 21 and the gate capacitance of the transfer transistor 21.
The signal at the gate of the transfer transistor 21 is AN.
A further delay occurs than the output of the D gate 22. Therefore, the non-overlap time between the timing at which the logic level of the input signal IN is determined and the transfer operation by the clock signal φ is reduced, and racing is likely to occur in the circuit shown in FIG. Therefore, the same figure (b
), a second holding circuit 27 consisting of a transfer transistor 25 and an inverter 26 is provided immediately before the holding circuit 24 consisting of a transfer transistor 21 and an inverter 23, and a clock signal φ is input to the gate of the transfer transistor 25. The input signal IN is the second
The signal is transmitted to the holding circuit 24 via the holding circuit 27 . At this time, although the transfer timing of the transfer transistor 21 is delayed from the clock signal φ as described above, the timing at which the input signal IN is held in the second holding circuit 27 coincides with the rising edge of the clock signal φ.

That is, a predetermined non-operational knob is secured between the timing when the logic level of the input signal IN is determined and the timing of the clock signal φ. Therefore, even if the non-overlap between the transfer timing of the transfer transistor 21 and the clock signal φ is reduced, the data transmitted by the transfer transistor 21 is already fixed data held in the second holding circuit 27. The logic level of the input signal IN, which has been determined since then, is always held by the holding circuit 24.

In this way, by providing the second holding circuit 27 that holds the input signal IN in advance at the timing of the clock signal φ before the delay occurs, it is possible to always maintain a predetermined non-overlap and prevent racing from occurring. This is intended to avoid this problem and ensure stability during high-speed operation.

Note that the holding circuits 24 and 27 can also be replaced with flip-flops 28 of the type shown in FIG. Alternatively, the clock signal φ may be input and the signal to be transmitted to the next stage may be taken out from the output Q or the inverted output Q.

In addition, as shown in FIG. 3, clocked gates 31 and 32
It is also possible to use clocked gate 31.3
2 transmits or cuts off the output by inputting a pair of clock signals CK and CK, transmitting the output when the clock signal CK is at H level, and transmitting the output when the clock signal CK is at the H level.
The output is cut off when K is at L level. In other words, the same figure (
In the circuit a), the clock signal CK is supplied from the output of the AND gate 33, and the clock signal CK is supplied from the output of the AND gate 33 to the inverter 34.
The clock signal CK is obtained through the clock signal φ, and the operation timing of the clocked gate 31 is delayed from the timing of the clock signal φ, similarly to the circuit shown in FIG. Therefore, the possibility of lacing occurring increases, but
By providing a second clocked gate 32 at the front stage of the clocked gate 31 as shown in FIG. It is intended to stabilize circuit operation such as.

FIG. 4 is a diagram showing a first embodiment of the present invention based on the above basic principle, in which the present invention is applied to the first conventional example shown in FIG. In addition, in the figure, members having the same configuration as those of the first conventional example are given the same reference numerals and their explanations will be omitted.

A second holding means 42 for holding the output of the inverter 2 at the timing of the clock signal φ2 is provided before the holding means 41 consisting of the transfer transistor 3 and the inverter 4.
will be provided. The second holding seven stages 42 consists of a transfer transistor 43 and an inverter 44, and the gate of the transfer transistor 43 receives the same signal as the clock signal φ2 input to the AND gate 5 (that is, the same polarity and the same period as the clock signal φ2). (signals with the same pulse width) are input by a clock generator (not shown).

In the above configuration, the clock signal φ and the clock signal φ
Since a predetermined non-overlapping portion is provided in advance in inverter 2, the transfer operation by transfer transistor 43 is reliably performed after the transfer operation by transfer transistor 1 is completed and the output logic level of inverter 2 is determined. That is, the output logic level of the second holding means 42 is the same as that of the inverter 2 located at the previous stage.
When the output logic level of the inverter 2 is determined and a predetermined non-overlap time has elapsed, the output logic level of the inverter 2 is determined according to the output logic level of the inverter 2 inputted to the second holding means 42. Therefore, since there is no factor that reduces the non-overlap time, racing does not occur between the transfer transistor 1 and the inverter 4. The output of the inverter 4 is passed through the holding means 41 to the subsequent circuit.
That is, it is transmitted to the inverter 7 via the transfer transistor 6, but the output of the AND gate 5 based on the clock signal φ2 is led to the gate of the transfer transistor 3, and the output of the AND gate 5 is connected to the AND gate as described above. The timing of the clock signal φ2 is delayed from the timing of the clock signal φ2 due to the influence of the response delay of 5 and the delay time constant due to the wiring. Therefore; transfer transistor 43
The transfer transistor 3 performs the transfer operation later than the previous one, but since the second holding means 42 reliably holds the predetermined output of the inverter 2, the holding means 41 It does not hold a logical output value, i.e., AND
Even if the response delay of the gate 5 or the delay time constant due to wiring fluctuates.

Since the second holding means 42 holds the output of the previous stage in advance, the holding means 41 will not hold uncertain data due to the occurrence of racing. Therefore, reliable operation can be performed according to preset timing. Further, since the operation timing of the second holding means 42 and the preceding stage circuit, that is, the transfer transistor 1, is performed while maintaining a preset non-overlap time, racing does not occur even during high-speed operation. This ensures stability during high-speed operation.

FIG. 5 is a diagram showing a second embodiment of the present invention, in which the present invention is applied to the second conventional example shown in FIG. In the figure, members having the same configuration as those of the first embodiment and the second conventional example are designated by the same reference numerals, and their explanations will be omitted.

The data on the data bus 11 is transferred to the transfer transistor 5.
1 and an inverter 52 to the holding means 41, and the transmission by the second holding means 53 is performed in response to the H level of the clock signal φ2. Therefore, the transfer transistor 3 is the second
The determined data on the data bus 11 held by the holding means 53 can be transmitted to the inverter 4,
The same effects as in the first embodiment can be obtained.

〔effect〕

According to the present invention, the second holding means for holding a signal at a predetermined logic level at the timing of a clock signal is provided;
Since the holding means holds a signal at a predetermined logic level in advance, it is possible to avoid the occurrence of racing, and it is possible to obtain a semiconductor integrated circuit that ensures stable high-speed operation.

[Brief explanation of the drawing]

Figures 1 to 3 are diagrams showing the basic principle of the present invention. Figure 1 is the first circuit diagram, Figure 2 is an example of the holding circuit, and Figure 3 is the second circuit diagram. Circuit diagram: FIG. 4 is a circuit diagram showing the configuration of a first embodiment of the semiconductor integrated circuit according to the present invention; FIG. 5 is a circuit diagram showing the configuration of the semiconductor integrated circuit according to the second embodiment of the present invention. 6 to 8 are diagrams showing conventional semiconductor integrated circuits, FIG. 6 is a circuit diagram showing the first conventional example, FIG. 7 is a timing chart showing its operation timing, and FIG. is a circuit diagram showing the second conventional example. 41... Holding means. 42.53...Second holding means. 6 no
′−′″＼, ノ Structure Second conventional example: No. 8 Circuit diagram showing

Claims (1)

[Scope of Claims] A semiconductor integrated circuit comprising a holding means for holding a signal of a predetermined logic level based on the timing of a predetermined clock signal when a signal of a predetermined logic level is input, the semiconductor integrated circuit comprising: at a stage preceding the holding means; A semiconductor integrated circuit comprising second holding means for holding a logic level signal at the timing of the clock signal and outputting the held value to the holding means.