JPH01264270A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To reduce a resistance without causing a detect in an interface between an electrode extraction layer and a channel by smoothly connecting a conduction band or a valence band in the interface between a source-drain electrode extraction layer and the channel. CONSTITUTION:A high-purity GaAs buffer layer 2 is crystal-grown on a whole face of a substrate 1; a mask 9 is shifted on it; n-type AlGaAs 5 is crystal- grown. Then, n-type GaAs layers 3, 4 are grown; a window is opened only at the upper part of the n-type AlGaAs 5; in etching operation is executed; the active layer 5 is exposed. Then, an AuGe alloy is applied to the drain and source electrode extraction layers 3 and 4 in order to obtain ohmic contact; a metal having the Schottky contact, e.g. Al, is applied to the n-type AlGaAs 5; these are worked individually by using an ordinary photolithographic method and an ordinary lift-off method; a drain electrode 6, a source electrode 7 and a gate electrode 8 are formed. Since the electrode extraction layers and a channel formation layer are deposited continuously, a conduction band or a valence band or both of them are connected smoothly; an increase in a resistance can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device suitable for high-speed operation.

[Conventional technology]

Conventionally, a method for reducing the resistance of the electrode lead portion of a semiconductor device has been described in Japanese Patent Laid-Open No. 61-270873.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, there is a series resistance between the source/drain and the channel, and the transistor characteristics fluctuate over a long period of time. This is considered to be because the isolation region is etched after the electrode extraction layer is formed and the channel forming layer is further deposited, so defects occur at the interface between the electrode extraction layer and the channel.

SUMMARY OF THE INVENTION An object of the present invention is to provide an element structure and a manufacturing method thereof that can reduce resistance without causing defects at the interface between an electrode extraction layer and a channel.

(Means for Solving Problem 11) The above object is achieved by selectively forming either the electrode extraction layer or the channel forming layer, and then continuously forming the other one.

However, the meaning of the word "continuous" here is that the above two layers are deposited in a non-oxidizing atmosphere, for example, in the case of molecular beam epitaxy growth, as follows. First, a mask with holes made in a thin plate of Si or the like is placed close to the substrate surface, and crystals are selectively grown through the holes6.
Next, the mask is moved without breaking the vacuum, and crystal growth is performed on the entire surface.The mask is moved in a straight line into the vacuum.

The introduction mechanism of rotational motion makes it possible to perform this with an accuracy of 1 μm or less without breaking the vacuum. Therefore, selective growth can be performed while the sample remains in the crystal growth chamber.

Each process of mask movement and full-scale growth can be performed continuously without exposing the sample to the atmosphere. Furthermore, it is of course possible to repeat the above process continuously in any order.

In addition, for example, if crystal growth using a focused ion beam is used, selective growth can be achieved by drawing with a focused ion beam without using a mask with holes. Continuous crystal growth is also possible using this method.

[Effect]

Since the electrode extraction layer and the channel forming layer are continuously deposited, no defects occur at the interface. Therefore, the conduction band, valence band, or both at the interface between the electrode extraction layer and the channel are smoothly connected.

Therefore, the resistance between the electrode extraction layer and the channel increases.

In addition, fluctuations in transistor characteristics over a long period of time are eliminated.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 The HEMT of Example 1 of the present invention is shown in FIGS. 1 and 2 (a) to
This will be explained with reference to FIG. 2(d).

First, as shown in FIG. 2(a), a high purity GaAs buffer layer 2 is grown on the entire surface of a semi-insulating GaAs substrate 1 by molecular beam epitaxy. The carrier concentration of the buffer layer 2 is I x 10/d or less, and the film thickness is 0.1 μm.
The above is necessary. What are the crystal growth conditions?

Substrate temperature between 500°C and 800°C, film formation rate of 0.1 μm
/hr to 10 μm/hr. Without taking out the substrate from the growth chamber, as shown in FIG. , crystal growth of n-type A11GaAs5 is performed while maintaining the state. N-type AuGaAs5 has a Si concentration of 3 × 10 μm δ
/aJ, 1lJ3μm, film thickness 30nm, AQ composition 0.3
The crystal growth conditions are the same as described above. Thereafter, the mask 9 is moved and removed, and n-type GaAs layers 3 and 4 having a Si concentration of 5.times.101 g/ffl and a film thickness of 50 nm are grown over the entire surface as shown in FIG. 2(c).

This crystal is taken out from the growth chamber and subjected to normal photolithography as shown in Figure 2(d).
A window is opened only in the upper part of the n-type AΩGaAs 5, and an etching process is performed on the window to expose the active layer 5. Etching includes selective etching, such as CCQ.
Dry etching with x F z + Ha gas or wet etching with Hz Oz + N H40H is used, or non-selective etching, such as dry etching with CQx gas, is used. Since the electrode lead-out layers 3 and 4 are as thin as 50 nm, sufficient controllability can be obtained even by non-selective etching.Firstly, to obtain ohmic contact on the drain and source electrode lead-out layers 3 and 4. AuGe alloy is deposited, and a metal having a Schottky contact, such as AQ, is deposited on the n-type AQGaAs5, and each is processed by conventional photolithography and lift-off methods to form the drain electrode 6. A source electrode 7 and a gate electrode 8 are formed to obtain the transistor shown in FIG. In this transistor, region 5 and region 2 are channel forming layers, and a channel 10 is formed on the region 5 side of region 2.

According to this embodiment, the source resistance is significantly reduced to 60 mΩ-■. As a result, the noise figure was 0.9 dB at 12 GHz in a transistor with a gate length of 0.5 μm.
A result of 1.3 dB at GHz was obtained.

Example 2 As shown in FIG. 3, in Example 1, n-type A Q Ga
High purity G a A s fluorine layer 2 instead of A s 5
An undoped channel M5' (impurity concentration lXl0
”/ad or less, film thickness 20 nm) and n-type AQGaAs5
A two-layer structure (similar to Example 1) is formed. As a result, the spreading resistance at the junction between the lower portion of the conductive channel 1o and the source/drain electrode extraction portion 3.4 is halved. As a result, the noise figure was further improved to 12
0.85dB at GHz, 1 at 18GHz.
It became 22dB.

Example 3 In Example 2, the buffer layer 2 was made of A A O, aG a O, 7A S (impurity concentration 1X10''/d or less, thickness similar to Example 2) instead of Ga As.

This reduces the current flowing through the substrate side, improving the pinch-off characteristics, and also reducing the drain conductance. This increased the maximum amplifiable frequency by 40%.

Example 4 In Example 1, changes are made after the part where crystal growth is performed through a mask. Figures 4(a) and 4(b)
). First, the source/drain electrode lead-out portions 3 and 4 are selectively crystal-grown through a mask in areas other than the central band-shaped region, and then the mask is removed and n-type AQGaAs 5 is grown on the entire surface, as shown in FIG. 4(a). The crystal shown in is obtained. The impurity density and film thickness of each region are based on Example 1. Next, the portion of the n-type AQGaAs 5 other than the upper surface of the source/drain electrode extraction portion 3 layer 4 is protected by ordinary photolithography, and then etched to expose the upper surface of the source/drain region.

Also source and drain.

Each electrode of the gate was formed in the same manner as in Example 1, as shown in FIG. 4(b).
In a zero-wire structure to obtain a transistor having the shape shown in FIG. 1, the distance between the source and drain can be made smaller than the mask dimension by increasing the distance between the mask and the substrate and utilizing the effect of the molecular beam wrapping around the periphery of the mask. Therefore, the source-gate resistance is further reduced than in the first embodiment. Although the device structure was similar to the conventional example, the same values as in Example 2 were obtained as the device characteristics due to the effect of reducing interface defects.

Example 5 In Example 4, the active layer 5 was replaced with a two-layer structure similar to Example 2. Due to the same effect as in Example 2, the noise figure was 0.8 dB at 12 GHz.

1.2 dB was obtained at 18 GHz.

Example 6 In Example 5, the same A as in Example 3 was used in the buffer layer 2.
A fiGaAs layer was used. As a result of the same improvement as in Example 3, the maximum amplifiable frequency increased by 40%.

Example 7 As shown in FIG. 5, 1. n-type AQGa
The single layer portion of As5 is made of n-type AQ GaAs11, high purity GaAs12. Replaced with a three-layer structure of n-type A Q GaAg 13. In regions 11 and 13, the impurity concentration AQ composition is the same as in region 5, and the film thickness is 80 in region 11 and 80 in region 13.
There are 250 people. In region 12, the purity is similar to region 2, and the film thickness is 100. Similar effects can be obtained with this film thickness in the range of 50 to 300 people. In this structure, the conductive channel under the gate has three layers, and the channel resistance is approximately 1/3 that of the first embodiment. Therefore, it has excellent driving ability and is particularly suitable for high output applications or integrated circuit applications.

In particular, in this structure, n-type G
a A s 3 and 4 are both in contact without a heterojunction, resulting in a low resistance contact. This is not possible with conventional methods, ie, etch-then-deposit methods, and is a major advantage of the present invention.

Embodiment 8 As shown in FIG. 6, in Embodiment 7, a high-purity GaAs layer 5' (the specifications are in accordance with Embodiment 2) is provided under the region 11 as in Embodiment 2. The same effect as in Example 2 reduces the series resistance to the bottom layer of the conductive channel,
Driving ability is further improved.

Example 9 In Example 8, the buffer layer 2 was made of AQ as in Example 3.
It was composed of GaAs. Since the current flowing through the buffer layer is substantially eliminated, the threshold value of the FET changes when the gate length is shortened to 1 μm or less. The so-called short channel effect is almost absent up to a gate length of 0.3 μm, and the drain conductance g- is also reduced, making it suitable as a high-output FET in a band of 10 GHz or more.
A gain of 6.0 dB and an output of 1.5 W at 30 GHz were obtained using a 3 μm FET.

In Examples 7 to 9, 2M of n-type AQGaAs layers were provided, but
It goes without saying that similar effects can be obtained in the case of three or more layers.

Also, an n-type Al2GaAs layer (5 or 11°13)
High purity A at the interface with high purity Ga A s M
Q GaAs (10 to 500 people) may be inserted, but since it is not related to the essence of the operation, it is omitted here. Of course, even if this is inserted, the same result as shown here can be obtained.

In each of the above examples, the AQ composition in AQGaAs is 0.
3, but a similar effect can be obtained if the value is 0.15 or more. However, if the AQ composition is 0.4 or more, the material becomes chemically active, so there are restrictions on the process. In addition, the impurity concentration is also 5 in the source/drain horizontal extraction portions 3 and 4.
x 1017/a1 or higher.

3×10 for n-type AQGaAs5 and 11.13
”/d or more, however, the optimum impurity concentration of AflGaAs is A Q Ga As , Ga A
It depends on the film thickness of the s-layer 5°11, 12, 13. That is, the impurity concentration and film thickness must be set so that all conductive channels and the AMGaAs layer can be depleted by a gate voltage within a range where the Schottky contact of the gate does not break down.

Moreover, in the above embodiment, the A Q GaAs layer G a A
s combination, other material systems such as AQGaSb/GaSb, InGaAsP/GaAs.

InAQGaP/GaAs, InP/InGaAsP
.

Of course, a combination of InAQGaAs/InGaAs and the like can also provide exactly the same effect.

Moreover, it goes without saying that the same effect can be obtained even if all the p-type and n-type are replaced.

Also, here all FETs using Schottky gates are used.
However, other types of gates include MIS gates in which a dielectric material is inserted at the interface between metal and semiconductor, and pn gates.
It goes without saying that there is essentially no difference in the case of using a junction gate using a junction or a semiconductor as a gate as long as it operates as an FET, and the same effect can be obtained.

Regarding methods of selectively growing crystals, in addition to the usual molecular beam epitaxy method, there are also molecular beam epitaxy using gas as a raw material, chemical vapor deposition method, and selective growth method using a mask. etc. can be mentioned. Other methods that can be considered include selective growth using optical excitation or crystal growth using focused ion beams. Even if these are used, the same effect can be obtained if the generation of interface defects is avoided by performing continuous growth.

Embodiment 10 Even without using these special methods, a similar structure can be obtained as follows by using a groove machined into an inversely tapered shape as shown in FIG. First, a growth method with a large wraparound, such as molecular beam epitaxy using a molecular beam from an oblique direction, or, for example, a substrate temperature of 700°C or higher,
A growth method with strong primary directionality in which the buffer layer 2 is deposited on the bottom metal surface of the groove by a molecular beam epitaxy method or the like in which the migration distance of incident molecules on the surface is larger than the overhang length of the groove, for example, the substrate temperature is set to 500°C. The n-type AQGaAs layer 5 is deposited by molecular beam epitaxy, etc., while reducing the distance between the molecular beam source and the substrate. At this time, A
Q-containing substances are known to have a small surface migration distance, which also promotes this effect. Alternatively, the same effect can be obtained by increasing the pressure of the As molecular beam.

Next, under the same conditions as those for growing buffer layer 2, n-type GaA
Grow s-layers 3 and 4. This results in a structure essentially similar to that shown in FIG. 2(Q).

In this way, the present invention can be carried out without involving the operation of moving the mask. In the case of this embodiment, the substrate and the reverse tapered portion 14 may be made of the same material or of different materials, and the tapered shape can be arbitrarily selected within a range that does not impair the effects of the above method. Other steps and characteristics are the same as in Example 1.

〔Effect of the invention〕

According to the present invention, since no defects occur between the electrode lead-out portion and the active portion, there is an effect of reducing resistance and stabilizing characteristics.

[Brief explanation of the drawing]

Fig. 1 is a sectional view of Embodiment 1 of the present invention, Fig. 2 is a manufacturing process diagram thereof, Fig. 3 is a sectional view of Embodiment 2, and Fig. 4 is a sectional view of Embodiment 4.
FIG. 5 is a sectional view of Example 7, FIG. 6 is a sectional view of Example 8, and FIG. 7 is a sectional view of Example 10 in the middle of the process. 1... Substrate, 2... Buffer layer, 3... N-type Ga
As, 4- n-type Ga As, 5- n-type AflG
aAs, 6... drain electrode, 7... source electrode,
8... Gate electrode, 9... Mask, 10... Conductive channel, 11.13"'n-type A Q GaAs, 1
2-...High purity Ga As, 14 thatch 1 kunibud 4 tsubuki hai 2 fig. 10 + yaki 1 shi

Claims (1)

[Claims] 1. A field effect transistor having a substrate, a channel forming layer having a mesa portion formed on the substrate, and a source electrode extraction layer and a drain electrode extraction layer formed in contact with the channel exposed in the mesa portion, A semiconductor device characterized in that a conduction band/valence band at an interface between the source/drain electrode extraction layer and the channel are smoothly connected.