JPH01265232A - Thin film transistor matrix substrate - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a thin film transistor matrix substrate used in a flat display panel such as a liquid crystal, and particularly relates to a bus connecting between gate electrodes or drain electrodes of each transistor. The present invention relates to an IJ board having a configuration suitable for reducing the resistance of the line portion.

[Conventional technology]

A conventional example of a thin film transistor matrix substrate is disclosed in Japanese Patent Laid-Open No. 105582/1982.

The outline will be explained below with reference to FIGS. 9 and 10.

FIG. 9 is a partial plan view of the thin film transistor matrix substrate, and FIG. 10 is a cross-sectional view taken along the line B-B'. 5 is a semiconductor film, 6 is a gate bus line, 7 is a drain bus line, 8 is a pixel electrode, and 9 is an auxiliary bus line. When a voltage is applied to the gate electrodes 1&C through the gate bus line 6, the channel of the transistor opens and the drain node (
A signal transmitted to the drain electrode 2 through the line 7 is input to the pixel electrode 8.

Figure 10 shows B-B'ls of the gate bus line section in Figure 9.
This shows the I#r plane, and the bus line of gate electrode 1 is shown below.

It consists of a gate bus line 6 and an auxiliary bus line 9 that overlaps and is partially cut off from the gate bus line.

[Problem to be solved by the invention]

In the thin film transistor matrix substrate mentioned above, as the size increases, the resistance of the gate and drain bus lines increases with the size (this causes a delay in the transmission signal, and for this reason, depending on the position on the panel) There is a problem that display responsiveness varies.

Generally speaking, there are two ways to reduce the resistance of the bus line: widening the entire width of the bus line and increasing the film thickness. As a result, the pixel electrode will have to be made smaller.As a result, the chain acid that actually performs display will be reduced, leading to a decline in image quality.Also, in the latter case,
Increasing the film thickness of the bus line placed on the lower side increases the step difference in the bus line formed on the upper side.V
C7', CQ, there is a problem that the upper bus line is easily disconnected.Therefore, the problem was to reduce the resistance of the bus line so that these problems do not occur.

An object of the present invention is to reduce the resistance of the bus line without causing problems such as a reduction in the display area or an increase in the number of bus lines, and to achieve good responsiveness even in large panels, regardless of the position on the panel. An object of the present invention is to provide a thin film transistor matrix substrate with excellent properties.

[Means to solve the problem]

The above purpose is to change the width of the first bus line in the portion where the first bus line (gate bus line or drain bus line) and the auxiliary bus line of the first bus line do not overlap with the first bus line. By making the line width wider than the wider of either the first bus line or the auxiliary bus line in the portion where the auxiliary bus line overlaps,
achieved.

The reason why the resistance of the bus line can be reduced by using the iC configuration as described above will be explained based on a specific example.

The circuit of the bus line is a rework of the wiring between the first layer part α of the gate bus line 6 shown in [1] and the second layer part consisting of the gate bus line 6 and the auxiliary bus line 9, and one cell of that The equivalent circuit of the resistance of the gate bus line 6 and the auxiliary bus line 9 can be expressed as shown in the 51st VC. The resistance corresponding to the gate bus line 6 in the previous part, and the resistance corresponding to the auxiliary bus line 9 in the same part. If we assume that the contact is in contact with each other and ignore the contact resistance, the resistance of one cell is calculated by the above R1m and R, as shown in Figure 5.
2 are connected in parallel, and R11 is further connected in series.

The typical resistance value of one cell of the above bus line is calculated as follows. The length of one cell is 240 μm, and in order to ensure that a short circuit does not occur at the intersection of the gate bus line 6 and the drain bus line 7, the distance of the further portion α of the gate bus line 6 is required to be 50 to 50 μm. Therefore, if this distance is assumed to be 30μm, the distance between the remaining two-layer parts will be 210μm. What is the film thickness of gate bus line 6?

In order to suppress the step difference in the film formed thereon, the thickness is kept to about 100μ, and the sheet resistance is also about 5Ω/day. Since the auxiliary bus line 9 is formed on the upper part, its film thickness is relatively low, and its sheet resistance is also (approximately L1Ω/day).The gate bus line 6 and the auxiliary bus line 90
If both widths are 10 μm, resistor R11#R in Figure 5
u # The resistance values of the birds are 15Ω, 105Ω, and 2.
1Ω, and the resistance value of the entire cell is approximately 17.10. As is clear from this, the ratio of the resistance of the part α of the gate bus line 6 to the resistance of the wiring of one cell is as large as about 88%.

Therefore, in order to lower the resistance value of the entire bus line, it is necessary to lower the resistance of these six parts. The length of this α part is 3
0 to 50 μm, which is about 10 to 20% of the cell length, and the wiring width is made thicker in this part (even if the wiring width is made thicker, the area of the pixel TIL pole 8 is hardly reduced. Therefore, the gate bus line 6
By making the line width of only one layer α wider than the other portions, the influence of the reduction in display area can be reduced (and the resistance of the bus line portion can be reduced).

[Effect]

The effects of the above configuration will be explained according to Figures 6 and 7.

FIG. 6 shows the basic configuration for reducing wiring resistance according to the present invention.

In the conventional method, the width of the gate bus line 6 in the single layer portion where the auxiliary bus line 9 is not provided is the same as that in other portions, as shown by the dotted line in the figure. The wiring width is expanded as shown by the solid line in the figure. Therefore,
The resistance of this part decreases. Currently, the width of conventional wiring is 10 μm.

When the length L is 50 μm, the resistance ratio of the first layer part to the widening tr is shown in Figure 7, and the resistance ratio including the second layer part is shown in Figure 8. show. The resistance of the entire bus line can be determined by lowering the resistance of the gate bus line 6 in the first layer without the auxiliary bus line 9, which accounts for more than 80% of the resistance of the entire cell. Without changing the resistance of the parts, it can be lowered as shown in Figure 8.
The speed of signals traveling on the bus line can be increased.

〔Example〕

Hereinafter, embodiments of the present invention will be explained with reference to FIGS. 1 to 4.

FIG. 1 shows a plan view of an embodiment of the present invention. First, a gate electrode 1 and a gate bus line 6 are formed on a glass substrate (not shown). At this time, the wiring width of the gate bus line 6 corresponding to the cut portion of the power auxiliary bus line 9 provided on the Kate Hass line 6 is made wider than the wiring width of the portion where the auxiliary bus line 9 is to be provided. .Furthermore, an insulating film 4 and a semiconductor film 5, which serve as interlayer insulation between the gate insulating film, the gate bus line 6, and the drain bus line 7, and the semiconductor film 5 are sequentially formed thereon.

Next, a source electrode 3, a drain electrode 4, a drain bus line 7, and an auxiliary bus line 9 are formed, and finally, a storage electrode 8 is formed to obtain a thin film transistor matrix substrate.

Conventionally, the width of the gate bus line 6 has been the same in all parts, but in this embodiment, a method is used in which the width of a part of the gate bus line 6 is widened as shown in 6d above. The area where the width of the gate bus line 60 is widened is a part of the area near the intersection with the drain bus line 7, so that the pixel electrode 8
There is little need to reduce the size of . On the other hand, as mentioned above, as for the resistance of the gate bus line 6, more than 80% of the resistance was in the area near the intersection with the drain lot line 7, where no auxiliary bus line could be provided. As described above, lowering the resistance of this portion reduces the resistance of the entire gate bus line.

FIG. 2 shows a plan view of another embodiment of the present invention.
FIG. 5 shows a cross section taken along the line AA' on the gate bus line in FIG. 2. In this embodiment, the parts related to the present invention are almost the same as those in the embodiment shown in FIG.
+3) Apply the gate bus line 6 to the entire surface of the board.
Only the parts necessary for contact with the auxiliary bus line 9 were machined with through-holes in the LE membrane 4 and connection through-holes 10 were provided! It has become a sign. According to this configuration, in the embodiment shown in FIG. 1, selective etching with respect to the gate bus line 6 was required to form the auxiliary bus line 9, but in this embodiment, the gate bus line 6 is Since it is protected by the insulating film 4, there is an effect that selective etching is not required.

In the embodiments shown in FIGS. 1 and 2, the width of the gate bus line 60 is increased.
Since the area of the intersection between the drain bus line 7 and the drain bus line 7 increases, the probability of a short circuit due to a defect in the interlayer insulating film increases. In order to prevent this, an embodiment of the present invention is shown in FIG. 4 in which the width of the gate bus line 60 at the portion where it intersects with the drain bus line 7 is narrowed as in the conventional case. With this configuration, the resistance of the gate bus line can be reduced without increasing the short circuit 44 between the gate bus line 6 and the drain bus line 7.

In all of the above embodiments, thin film transistors with an inverted staggered structure in which the gate tjIL of the thin film transistor is placed at the lower fIkK were described; The same thing can be done in the case of a matrix substrate having . In other words, in a matrix substrate having a structure in which an auxiliary bus line is provided on a part of the drain bus line, the − of the drain bus line is partially widened in the part where the auxiliary bus line cannot be provided near the opposite part from the gate bus line. As a result, the resistance of the entire drain bus line can be reduced and a thin-layer transistor matrix substrate with excellent responsiveness can be obtained.

[Young rice of invention]

According to the present invention, by widening only a portion of the width of the bus line of the thin film transistor matrix substrate, it is possible to reduce the resistance of the bus line without deteriorating the 1111 quality due to the movement of the pixel electrode or the like.

The resistance of the entire bus line can be reduced to about 60% by doubling the width of the part of the auxiliary bus line that does not form a cliff. As a result, a thin film transistor matrix with excellent responsiveness can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view of one embodiment of the present invention, FIG. 2 is a plan view of another embodiment of the present invention, FIG. 3 is a sectional view taken along line A-A' in FIG. A plan view of yet another embodiment of the invention, Fig. 5 shows an equivalent circuit of one toggle resistance for one cell, Fig. 6 shows an explanatory diagram showing the basic mW of wiring resistance reduction according to the invention, Figs. Figure 8 shows wiring expansion I! A diagram showing the resistance reduction due to
FIG. 9 is a plan view showing an example of an IJ board according to the prior art, and FIG. 10 is a thin cross section taken along line B-B' in FIG. Explanation of symbols 1... Gate electrode 2... Drain electrode 3.
・・Source electrode 4・1ltA gland ty45・
...Semiconductor M6...Gate bus line 7
...Drain bus line 8...Pixel electrode 9...Auxiliary bus line 1o...Connection ball. Figure 1 Figure 2 G get bus line 9 浣tun excitation 1N null line 10 carrying red dog 1 Shiho 1 Figure 4 5 Figure 6 Line 8 Assistance 5 I W2 c) Person m) Figure 8 W2 Cpn)

Claims (1)

[Claims] 1. A group of thin film transistors each consisting of an active layer of a semiconductor thin film, a gate insulating film, and three electrodes of drain, source, and gate, and first and second transistors that connect either between the gates or between the drains of the individual thin film transistors, respectively. and an auxiliary bus line of the first bus line that has a portion that overlaps with the first bus line and is cut so as not to come into contact with the second bus line. In the matrix substrate, the width of the first bus line in the part where the first bus line and the auxiliary bus line do not overlap is the width of the first bus line in the part where the first bus line and the auxiliary bus line overlap.
A thin film transistor matrix substrate characterized in that the line width is wider than the wider of either the bus line or the auxiliary bus line.