JPH01268154A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To flatten an interlayer insulating layer without cracking by incorporating phosphorus in solution of glass which becomes the material of a coating baked oxide film. CONSTITUTION:A pattern of first aluminium wiring layer 3 is formed on a semiconductor substrate 1 formed with an element region and made, for example, of Si and an interlayer insulating film 2. Then, the substrate 1 is disposed in a plasma vapor growing device, and coated with a plasma oxide film (SiO2 film) 4 by N2O+SiH4 gas. Then, glass material dissolved in ethanol is rotatably coated by a spin coater to obtain a coating baked oxide film 5. Here, the solution of the coating glass material includes, for example, a solution having 5wt.% or less of SiO2 concentration and 5wt.% or less of P2O5 concentration. Phosphorus ions are introduced into the glass material thereby to remarkably reduce a crack of the coating baked oxide film.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure such as an LSI, and in particular, flattening an insulating film between the eyebrows in a multilayer wiring structure to reduce the occurrence of cranks. The present invention relates to a method of manufacturing a semiconductor device that achieves this while preventing.

[Conventional technology]

2. Description of the Related Art In recent years, multilayer wiring structures have been commonly used in semiconductor devices, especially LSIs, as their integration becomes higher.

For example, an interlayer insulating film such as a plasma CVD silicon nitride film is provided on a first aluminum wiring provided on a semiconductor substrate having a 5iOz film, and a second aluminum wiring is formed on top of the first aluminum wiring, thereby forming a multilayer wiring structure. It is something to do.

However, since the interlayer insulating film is extremely thin, there is a difference in level between the first wiring part and the non-wiring part, and when wiring in the second layer, there are problems such as disconnection at the step part and the fact that the wiring layer is not formed uniformly. is likely to occur.

Therefore, the technology for planarizing interlayer insulating films in multilayer wiring structures has become an important element in semiconductor devices having multilayer wiring structures, and includes techniques such as the high-ass spatter method, etch-back method, lift-off method, and spin-on-glaze film coating.
Various planarization techniques such as coating methods (ss, 5OG) are used.

In particular, the coating and baking oxide film method involves dropping a silicon compound dissolved in an aqueous solvent, such as ethanol, onto a substrate and baking it after spin coating with a spin coke. was often used.

FIG. 2 shows a multilayer wiring structure of a semiconductor device using the conventional coating and firing oxide film method.

In FIG. 2, for example, a first aluminum (A6) wiring layer 13 is formed on a semiconductor substrate 11 covered with a SiO□ film 12.
After forming a coated and fired oxide film 14 on the substrate including the first Aβ wiring layer 13, a ρ wiring layer 15 is formed in the second layer to form a multilayer wiring structure.

This coated and fired oxide film can be formed in multiple layers to achieve planarization (for example, see Japanese Patent Laid-Open No. 102754/1983).

[Problem to be solved by the invention] 7 However, in the conventional interlayer insulating film planarization technology as described above, cracks etc. occur when forming 11.5 and 1L with a film thickness of 0.5 μm or more, for example. This made it impossible to simulate the thickness of 1.

Furthermore, even when forming a multilayer coated and fired oxide film, there is a possibility that cracks or the like may occur in the oxide film during firing.

Therefore, an object of the present invention is to provide a method for forming a multilayer wiring structure in which the interlayer insulating film can be flattened without producing cranks or the like, in order to solve the drawbacks of the conventional method.

[Means and effects for solving the problem] In order to achieve the above-mentioned "object 1," the present invention uses at least one layer of coated and fired oxide film as an interlayer insulating film of a semiconductor device having a multilayer wiring structure. It is characterized in that it contains phosphorus (P) in the solution which is beneficial, and the concentration of P2O5 in the solution is 5% or less.

By doing this, it is possible to prevent cracks from forming in the coated and fired oxide film and to flatten the interlayer insulating film.

C Example] An embodiment of the present invention will be explained with reference to the first centroid.

FIG. 1 is an explanatory diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. In FIG. 1, ■ is a semiconductor substrate, 2 is an interlayer insulating film, 3 is a first A wiring layer, 4 is a vapor grown oxide film, 5 is a coated and fired oxide film, 6 is a second Al wiring layer, 7 shows a vapor phase grown oxide film.

The interlayer insulating film of this example has a three-layer structure.

The manufacturing method will be explained below.

(1) A pattern of a first Δρ wiring layer 3 having a film thickness of approximately 1 μm is formed on a semiconductor substrate 1 made of, for example, Si and an interlayer insulating film 2 on which element regions (not shown) have been formed using a conventional method (
(See Figure 1(a)).

(2) Next, place the substrate 1 in a plasma vapor phase epitaxy apparatus and deposit a plasma oxide film (Si
C2 film) 4 was deposited at a temperature of 330℃ and a pressure of 1.0T during deposition.
A film with a thickness of 1.0 μm is formed under the conditions of 60 W of RF power and 60 W of RF power. Next, the glass material of the present invention melted with ethanol is spin-coated using a spin coater to obtain a coated and fired oxide film 5.

Here, the solution of the glass material to be applied has, for example, a Si02 concentration of less than Si% pzo5? A solution with a degree of sulfur of 5 wt% or less is used. This is thought to prevent ions from entering from outside the SOG by incorporating phosphorus ions into the glass material, and significantly reduces the occurrence of cranks in the coated and fired oxide film.

Table 1 shows the concentration of P2O5 contained in glass materials and
The relationship with the occurrence of /ri is shown.

Incidentally, the crack here refers to a relatively deep flaw that enters the coated and fired oxide film in parallel with the Aρ wiring layer, and often affects the reliability of the semiconductor device. Also micro
The crank is a baboon with a length of less than 1 μm that enters the coated and fired oxide film at a location away from the wiring, and has no bearing on the reliability of the device.

Table 2 shows the results of evaluating changes in the SOG solution state based on turbidity. If crystal particles are precipitated in the glass material solution during storage in a factory or the like, the solution becomes cloudy, and there is a risk that a glass film suitable for the glabella insulating film cannot be formed. Here, the temperature of 35°C was tested because the temperature could reach this level depending on the season when the solution was transported.

As is clear from Table 1 and Table 2, the glass material to be coated and fired is P20 from the viewpoint of crack prevention and solution stability.
Use a solution with a J4 degree of 5 wt% or less. At this time, Si
The concentration is preferably 5.8 wt% or less, and of course the commonly used 5 wt% or more can also be used.

The coated and fired oxide film 5 has a thickness of about 0.1 μm, for example, on a flat portion such as on the first An wiring layer 3 .

Subsequently, after baking at a temperature of 120° C. for 1 minute and a temperature of 250° C. for 30 minutes, the process of applying the same glass material as above on the film was repeated twice, and then the semiconductor substrate 1
The whole is fired at 120°C for 1 minute, at 250'C for 30 minutes, and then at 400'C for 15 minutes to obtain the desired coated and fired oxide film 5. This coated and fired oxide film 5 is mainly formed in the recesses formed by the first Aj2 wiring layer 3 on the surface of the substrate, so the surface of the substrate after film formation has a flat shape with few irregularities (see Fig. 1). (see (b)).

(3) Furthermore, a silicon oxide film 7 is formed on this semiconductor substrate 1 to a thickness of about 0.2 μm using an atmospheric pressure vapor phase growth apparatus (see FIG. 1).
See C).

(4) Next, predetermined portions of the three-layered glabella insulating film are treated with RIE (Reactive Ion Et) using the usual method.
After forming contact holes by etching using a method (see FIG. 1(d)), a pattern for the second An wiring layer 6 is formed by, for example, sputtering to complete the multilayer wiring structure (see FIG. 1(d)).

〔Effect of the invention〕

By forming a coated and fired oxide film in a multilayer wiring structure as in the present invention using a glass material containing P2O at a temperature of 5 wt% or less, no cracks will occur even during multilayer coating of the oxide film. The surface can also be sufficiently flattened. Therefore, the reliability of the semiconductor device is further improved.

[Brief explanation of the drawing]

FIG. 1 is a process explanatory diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a conventional example. ■-Semiconductor substrate, 2-Interlayer insulating film, 3-First An
Wiring layer, 4- Vapor grown oxide film, 5- Coated and fired oxide film, 6- Second A1 wiring layer, 7- Vapor grown oxide film. Patent applicant Fuji Xerox Co., Ltd. Representative Patent Attorney
Akira Yamatani

Claims (2)

[Claims] (1) Has a multilayer wiring structure, with at least one layer in the interlayer insulating film.
1. A method for manufacturing a semiconductor device including a coated and fired oxide film layer, the method comprising: containing phosphorus (P) in a glass solution serving as a material for the coated and fired oxide film. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the glass solution serving as the material for the coated and fired oxide film contains P_2O_5 and its concentration is 5 wt% or less.