JPH0362554A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0362554A JPH0362554A JP20784790A JP20784790A JPH0362554A JP H0362554 A JPH0362554 A JP H0362554A JP 20784790 A JP20784790 A JP 20784790A JP 20784790 A JP20784790 A JP 20784790A JP H0362554 A JPH0362554 A JP H0362554A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- oxide film
- insulating film
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000010410 layer Substances 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 18
- 238000001947 vapour-phase growth Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 238000010304 firing Methods 0.000 claims 1
- 238000000927 vapour-phase epitaxy Methods 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 32
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 32
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 12
- 238000009413 insulation Methods 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 description 20
- 229910052717 sulfur Inorganic materials 0.000 description 20
- 229910052799 carbon Inorganic materials 0.000 description 11
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 239000012808 vapor phase Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000000576 coating method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層配線構造を有する半導体装置およびその製
造方法に係り、特にアルミニウム多層配線間の層間絶縁
膜に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a multilayer wiring structure and a method for manufacturing the same, and particularly relates to an interlayer insulating film between multilayer aluminum wirings.
ＬＳＩなどの半導体装置における多層配線構造において
配線用金属としてはアル旦ニウム膜が最も一般的に用い
られている。第１のアルミニウム配線層上にプラズマＣ
ＶＤ窒化シリコン膜等の層間絶縁膜を設け、その上に第
２のアルミニウム配線層を設けて多層配線構造とする。Aluminum film is most commonly used as a wiring metal in multilayer wiring structures in semiconductor devices such as LSIs. Plasma C on the first aluminum wiring layer
An interlayer insulating film such as a VD silicon nitride film is provided, and a second aluminum wiring layer is provided thereon to form a multilayer wiring structure.
しかし前記絶縁膜はごく薄いため第１の配線部分と非配
線部分に段差を生じ、第２層目の配線の際、段差部で断
線したり、均一に配線層が形成されない不都合を生じる
。そのため多層配線における層間絶縁膜の平坦化技術は
多層配線構造を有する半導体装置において重要な要素と
なり、バイアススパッタ法、エッチバック法、リフトオ
フ法、Ｓ、Ｏ，Ｇ、 （Ｓｐｉｎｏｎ Ｇｌａｓｓ）塗
布法などの各種平坦化技術を駆使して構造の平坦化が行
われている。However, since the insulating film is very thin, a step is formed between the first wiring portion and the non-wiring portion, and when the second layer of wiring is formed, wires may be broken at the step portion, and the wiring layer may not be formed uniformly. Therefore, the technology for planarizing the interlayer insulating film in multilayer interconnections has become an important element in semiconductor devices with multilayer interconnection structures, and techniques such as bias sputtering, etchback, lift-off, S, O, G, (Spinon Glass) coating methods, etc. Structures are planarized using various planarization techniques.
特にＳ、０．Ｇ、塗布法はエタノール等有機溶剤に溶か
したガラス材料を基板に滴下し、スピンコーターで回転
塗布後焼成するもので、プロセスが容易で量産性に優れ
ているためしばしば用いられている。第２図にその一例
を示す。Especially S, 0. G. The coating method involves dropping a glass material dissolved in an organic solvent such as ethanol onto a substrate, spinning the coating with a spin coater, and then baking it, which is often used because it is an easy process and has excellent mass productivity. An example is shown in Figure 2.
第２図において１は半導体基板、２は絶縁膜、３は第１
のアルミニウム配線層、５はＳ、Ｏ，Ｃ，膜、６は第２
のアルくニウム配線層、８はプラズマＣＶＤ窒化膜を示
す。In FIG. 2, 1 is a semiconductor substrate, 2 is an insulating film, and 3 is a first
aluminum wiring layer, 5 is S, O, C, film, 6 is the second
The reference numeral 8 indicates an aluminium wiring layer, and 8 indicates a plasma CVD nitride film.
この方法はまず絶縁膜２を介して、第１のアルミニウム
配線層３を形成した半導体基板■上にプラズマＣＶＤ法
による窒化シリコン膜８を約３３０°Ｃで形成後、エタ
ノールに溶かしたガラス材料をスピンコーターで回転塗
布して焼威し、第１の配線層３付近に出来る凹部にＳ、
Ｏ，Ｃ，膜５を形成して、基板表面を平坦化する（第２
図（ａ）参照）。In this method, first, a silicon nitride film 8 is formed by plasma CVD at about 330°C on a semiconductor substrate (2) on which a first aluminum wiring layer 3 has been formed, via an insulating film 2, and then a glass material dissolved in ethanol is added. Spin coat with a spin coater and burn it out, and apply S to the recesses formed near the first wiring layer 3.
O, C, film 5 is formed to planarize the substrate surface (second
(See figure (a)).
次に第１のアルミニウム配線層３との接触孔を形成後第
２のアルミニウム配線層６を形成する（第２図（ｂ）参
照）。Next, after forming a contact hole with the first aluminum wiring layer 3, a second aluminum wiring layer 6 is formed (see FIG. 2(b)).
この方法ではＳ、Ｏ，Ｇ、膜５と第２のアルミニウム配
線層６が接するため、Ｓ、Ｏ，Ｃ，膜５被着後のキユア
リング、第２のアルミニウム配線パターン形成後の保護
膜の形成時等における熱処理工程の際、Ｓ、０．Ｇ、膜
から水分子が放出されこれがアルミニウム配線層中に吸
収されるという問題がある。In this method, since the S, O, G, film 5 and the second aluminum wiring layer 6 are in contact with each other, curing is performed after the S, O, C, film 5 is deposited, and a protective film is formed after the second aluminum wiring pattern is formed. During the heat treatment process, S, 0. G. There is a problem that water molecules are released from the film and absorbed into the aluminum wiring layer.
Ｓ、０．Ｇ、膜から放出される水分子は、ガラス材料を
溶かしていたエタノールが十分放散されない等の理由に
よるものと考えられる。S, 0. G. The water molecules released from the membrane are thought to be due to reasons such as the fact that the ethanol that had dissolved the glass material was not sufficiently released.
この水分子が、アル【ニウム配線層６中に含有されると
、長時間使用後、アルミニウム自身の電気的特性が劣化
し半導体装置の信頼性に問題を生じる。If these water molecules are contained in the aluminum wiring layer 6, the electrical characteristics of the aluminum itself will deteriorate after long-term use, causing problems in the reliability of the semiconductor device.
そこでこの不都合を解消するため第３図に一例を示す方
法が行われている。In order to solve this problem, a method is used, an example of which is shown in FIG.
即ち、第２図と同様にして形成したｓ、ｏ、Ｇ、Ｄ！ｉ
！５の上にプラズマＣＶＤ窒化シリコン膜９成膜温度約
３３０℃をオーバーコートする（第３図（ａ）参照）。That is, s, o, G, D! formed in the same manner as in FIG. i
! 5 is overcoated with a plasma CVD silicon nitride film 9 at a deposition temperature of about 330° C. (see FIG. 3(a)).
その上から第１のアルミニウム配線層３との接触孔を形
成後第２のアルミニウム配線層６を形成するものである
（第３図（ｂ）参照）。After forming a contact hole with the first aluminum wiring layer 3 from above, the second aluminum wiring layer 6 is formed (see FIG. 3(b)).
これによってＳ、０．Ｇ、膜が直接アルくニウム層に接
することがない。As a result, S, 0. G, the film does not come into direct contact with the aluminum layer.
ところが、第３図において第１のアルミニウム配線層３
上に絶縁膜を形成する場合、高温で形成すると、この高
温の熱処理によってアルミニウム配線層３にヒロック（
凸起）を生じさせ、これが該絶縁膜の厚さより大きくな
ると、アル５ニウム配線間の絶縁不良を生じるので、低
温形成が望まれる。このため従来は、絶縁膜として一般
にプラズマＣＶＤ法による窒化シリコン膜着膜温度約３
３０℃が用いられていた。However, in FIG.
When forming an insulating film on the aluminum wiring layer 3, if it is formed at a high temperature, hillocks (
If this protrusion becomes larger than the thickness of the insulating film, poor insulation will occur between the aluminum wirings, so low-temperature formation is desired. For this reason, in the past, a silicon nitride film was generally deposited as an insulating film by plasma CVD at a temperature of about 3.
30°C was used.
しかし、プラズマＣＶＤ法による窒化シリコン膜は、絶
縁膜２や基板ｌとの間の残留ストレスが大きいため、出
来上がった半導体装置に悪影響を及ぼす。However, the silicon nitride film produced by the plasma CVD method has a large residual stress between the insulating film 2 and the substrate 1, which adversely affects the finished semiconductor device.
またこの窒化シリコン膜８．９とＳ、Ｏ，Ｃ，膜５は相
互の密着性が弱いことと、両者の熱膨張係数が異なるた
め、窒化シリコン膜８．９とＳ、Ｏ，Ｃ，膜５の界面が
部分的にはがれてしまう問題点があった。Furthermore, since the silicon nitride film 8.9 and the S, O, C, film 5 have weak adhesion to each other and have different coefficients of thermal expansion, the silicon nitride film 8.9 and the S, O, C, film There was a problem that the interface of No. 5 was partially peeled off.
従って本発明の目的は、基板との間の残留ストレスが少
ない上、Ｓ、０．Ｇ、膜と熱膨張係数が互いに著しく異
ならない層間絶縁膜とその製造方法を提供するものであ
る。Therefore, an object of the present invention is to reduce the residual stress between the substrate and the S, 0. G. The present invention provides an interlayer insulating film whose coefficient of thermal expansion is not significantly different from that of the film, and a method for manufacturing the same.
〔課題を解決するための手段および作用〕本発明は上記
目的を遠戚するため、第１の配線層と第２の配線層間の
層間絶縁膜として、プラズマＣＶＤ法による酸化膜を第
１層とし、塗布焼成酸化膜（Ｓ、Ｏ，Ｇ、膜）を第２層
とし、気相成長酸化膜を第３層とする３層構造とするこ
とによって層間絶縁膜の平坦化を行うものである。[Means and effects for solving the problem] In order to achieve the above object, the present invention uses an oxide film formed by plasma CVD as the first layer as an interlayer insulating film between the first wiring layer and the second wiring layer. The interlayer insulating film is planarized by forming a three-layer structure with a coated and fired oxide film (S, O, G, film) as the second layer and a vapor-grown oxide film as the third layer.
本発明により、層間絶縁膜の第１層目として、下地の半
導体基板１や絶縁膜２との残留ストレスが少なく、第２
層目のＳ、Ｏ，Ｃ，膜とほとんど成分が変わらないので
熱膨張係数が大きく異なることのない酸化膜を用いるこ
とにより、両者の界面がはがれることもない。According to the present invention, as the first layer of the interlayer insulating film, there is little residual stress with the underlying semiconductor substrate 1 and the insulating film 2, and the second layer
By using an oxide film whose components are almost the same as those of the S, O, and C films in the layer, and whose thermal expansion coefficients do not differ greatly, the interface between them will not peel off.
さらにＳ、Ｏ，Ｇ、膜を、熱膨張係数があまり異なるこ
とのない気相成長酸化膜でオーバーコートすることによ
り、Ｓ、０．Ｇ、膜のアルミニウム配線層への悪影響が
改善される。Furthermore, by overcoating the S, O, and G films with a vapor-phase grown oxide film whose thermal expansion coefficients do not differ much, the S, O, and G films are coated with a vapor-phase grown oxide film whose thermal expansion coefficients do not differ much. G. The negative influence of the film on the aluminum wiring layer is improved.
本発明の実施例を第１図によって説明する。 An embodiment of the present invention will be explained with reference to FIG.
第１図において、１は半導体基板、２は絶縁膜、３は第
１のアルミニウム配線層、４はプラズマＣＶＤ酸化膜、
５はＳ、０．Ｇ、膜、６は第２のアルミニウム配線層、
７は気相成長酸化膜をそれぞれ示す。In FIG. 1, 1 is a semiconductor substrate, 2 is an insulating film, 3 is a first aluminum wiring layer, 4 is a plasma CVD oxide film,
5 is S, 0. G, film, 6 is the second aluminum wiring layer,
7 indicates a vapor-phase grown oxide film.
本発明の多層配線構造を有する半導体装置は、第１図（
ｄ）に示す如く、第１のアルミニウム配線層３と第２の
アルミニウム配線層６の間の眉間絶縁膜として、プラズ
マＣＶＤ酸化膜４とＳ、Ｏ，Ｃ。A semiconductor device having a multilayer wiring structure according to the present invention is shown in FIG.
As shown in d), the plasma CVD oxide film 4 and S, O, C are used as the glabellar insulating film between the first aluminum wiring layer 3 and the second aluminum wiring layer 6.
膜５と気相成長酸化膜７の３層構造とするものである。It has a three-layer structure consisting of a film 5 and a vapor-grown oxide film 7.
これにより、半導体基板１や絶縁膜２と接する第１層目
をプラズマＣＶＤ酸化膜２とすることにより、これらの
間の残留ストレスが小さくなる。As a result, by using the plasma CVD oxide film 2 as the first layer in contact with the semiconductor substrate 1 and the insulating film 2, the residual stress between them is reduced.
それとともに、平坦化に有効なＳ、Ｏ，Ｃ，膜５とも熱
膨張係数もそれ程異なることがないので、両者の密着性
もよい。In addition, since the thermal expansion coefficients of the S, O, C, and film 5, which are effective for planarization, are not so different, the adhesion between them is also good.
さらに、気相成長酸化膜７の存在により、Ｓ、Ｏ。Furthermore, due to the presence of the vapor-phase grown oxide film 7, S, O.
Ｇ、膜５とアルミニウム配線Ｎ６が直接接することもな
い。G, there is no direct contact between the film 5 and the aluminum wiring N6.
次に、本発明の半導体装置の製造方法を第１図を参照し
つつ説明する。Next, a method for manufacturing a semiconductor device according to the present invention will be explained with reference to FIG.
（１）通常の方法で形成された半導体基板１と絶縁膜２
上に膜厚約１μｍの第１のアルミニウム配線層３のパタ
ーンを形成する（第１図（ａ）参照）。(1) Semiconductor substrate 1 and insulating film 2 formed by a normal method
A pattern of a first aluminum wiring layer 3 having a thickness of about 1 μm is formed thereon (see FIG. 1(a)).
（２）次にプラズマ気相成長装置内に該基板１を配置し
、Ｎ、○＋Ｓ ｉ Ｈ４ガス系雰囲気中でプラズマ酸化
シリコン膜（Ｓ ｉ Ｏｚ膜）４を着膜温度３３０℃、
着膜時の圧力１．ｏトル、６０Ｗの条件で膜厚１．０μ
ｍ成膜する。(2) Next, the substrate 1 is placed in a plasma vapor phase growth apparatus, and a plasma silicon oxide film (S i Oz film) 4 is deposited at a deposition temperature of 330° C. in an N, O+S i H4 gas atmosphere.
Pressure during film deposition1. Film thickness: 1.0μ under the conditions of 60W and 60W
m film is formed.
次にエタノールで溶かしたガラス材料をスピンコーター
で回転塗布してＳ、Ｏ，Ｃ，膜５を得る。Next, a glass material dissolved in ethanol is spin-coated using a spin coater to obtain an S, O, C film 5.
このＳ、０．Ｇ、膜５の塗布は４０００ｒ、ｐ、ｍ、で
１５秒間の回転塗布を行い、窒素雰囲気中で４００’Ｃ
１５分間焼成することによって所望のＳ、０．Ｇ。This S, 0. G. Film 5 was coated by spin coating at 4000r, p, m for 15 seconds and heated at 400'C in a nitrogen atmosphere.
By baking for 15 minutes, the desired S, 0. G.
膜５を得る。A membrane 5 is obtained.
Ｓ、Ｏ，Ｇ、膜５は基板表面の第１のアルミニウム配線
層３によって形成される凹部に主に形成されるので、成
膜後の基板表面は凹凸の少ない平坦な形状となる（第１
図（ｂ）参照）。Since the S, O, and G films 5 are mainly formed in the recesses formed by the first aluminum wiring layer 3 on the substrate surface, the substrate surface after film formation has a flat shape with few irregularities (first
(See figure (b)).
（３）更にこの基板１を常圧気相成長装置で酸化シリコ
ン膜７を膜厚約０．２μｍで成膜する（第１図（Ｃ）参
照）。(3) Furthermore, a silicon oxide film 7 is formed on this substrate 1 to a thickness of about 0.2 μm using an atmospheric pressure vapor deposition apparatus (see FIG. 1(C)).
（４） 次に通常の方法でこれら３層構造の層間絶縁
膜の所定部分をＲＩ Ｅ （Ｒｅａｃｔｉｖｅ Ｉｏｎ
Ｅｔｃｈｉｎｇ）法によってエツチングして接続孔を
形成する。(4) Next, predetermined portions of these three-layer interlayer insulating films are subjected to RIE (Reactive Ion) using the usual method.
A connecting hole is formed by etching using a method (Etching).
次に第２のアルミニウム配線層６を例えばスパッタリン
グで形成し、所望の形状にパターニングする（第１図（
ｄ）参照）。Next, a second aluminum wiring layer 6 is formed by sputtering, for example, and patterned into a desired shape (see FIG.
d)).
本実施例ではＳ、Ｏ，Ｇ、膜５は一層塗りで説明したが
、本発明はこれに限られず多層塗りも可能である。In this embodiment, the S, O, G, and films 5 are described as being coated in one layer, but the present invention is not limited to this, and multilayer coating is also possible.
また第３層目の気相成長酸化膜７は常圧法で成膜したが
、プラズマ法、減圧法、光ＣＶＤ法で成膜しても同様の
効果を得ることができる。Further, although the third layer vapor-grown oxide film 7 was formed by a normal pressure method, the same effect can be obtained by forming the film by a plasma method, a reduced pressure method, or a photo-CVD method.
さらにこの気相成長酸化膜７として、本実施例は酸化シ
リコン膜について説明したが、本発明はこれに限られず
、ＰＳＧ膜（Ｐｈｏｓｐｈｏ−３ｉｌｉｃａｔｅＧｌａ
ｓｓ膜、リンをドープしたシリコン酸化膜）を使用する
こともできる。これにより、気相成長酸化シリコン膜の
場合と同様の効果があると同時に耐クラツク性が向上し
、ナトリウムイオンなどのアルカリイオンに対するゲッ
ター効果も期待できる。Further, as the vapor-phase grown oxide film 7, although a silicon oxide film has been described in this embodiment, the present invention is not limited to this.
ss film, phosphorus-doped silicon oxide film) can also be used. As a result, it can be expected to have the same effect as that of a vapor-grown silicon oxide film, improve crack resistance, and also have a getter effect on alkali ions such as sodium ions.
本発明は多層配線構造を有する半導体装置の配線層間の
層間絶縁膜をプラズマＣＶＤ酸化膜、Ｓ。The present invention uses a plasma CVD oxide film, S, as an interlayer insulating film between wiring layers of a semiconductor device having a multilayer wiring structure.
０、Ｇ、膜、気相成長酸化膜の３層構造とすることによ
り、絶縁膜２を形成した基板１と２層目の層間絶縁膜で
あるＳ、０．Ｇ、膜との熱膨張係数のちがいによるスト
レスの影響がなくなること、Ｓ、Ｏ，Ｃ，膜と接する層
間絶縁膜が酸化膜のため両者の密着性もよくなり、部分
的にはがれるという問題点もなくなる。0, G, film, and a vapor-phase grown oxide film, the substrate 1 on which the insulating film 2 is formed and the second interlayer insulating film S, 0. G, the effect of stress due to the difference in thermal expansion coefficient with the film is eliminated, S, O, C, the interlayer insulating film in contact with the film is an oxide film, which improves the adhesion between the two, and the problem of partial peeling. It also disappears.
さらに、Ｓ、Ｏ，Ｇ、膜を酸化膜でオーバーコートする
ためＳ、Ｏ，Ｃ，膜のアル旦ニウム配線層への悪影響も
改善でき、全体として平坦な眉間絶縁膜が形成されるの
で、多層配線の信頼性が著しく向上した。Furthermore, since the S, O, and G films are overcoated with an oxide film, the negative effects of the S, O, and C films on the aluminum wiring layer can be improved, and an overall flat glabella insulating film is formed. The reliability of multilayer wiring has been significantly improved.
また本発明の製造方法により、低温で良質の層間絶縁膜
を形成することができる。Further, by the manufacturing method of the present invention, a high quality interlayer insulating film can be formed at low temperature.
第１図は本発明の実施例を示す製造工程説明図、第２図
、第３図は従来例説明図である。
■ −基板、 ２ ・・・・絶縁膜、３−第１の
アル旦ニウム配線層、
４ ・−気相成長酸化膜、
５−−−− Ｓ、０．Ｇ、膜、
６− 第２のアル壽ニウム配線層、
７− 気相成長酸化膜、
気相成長窒化膜、
プラズマ窒化膜。FIG. 1 is a manufacturing process explanatory diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are explanatory diagrams of a conventional example. -Substrate, 2...Insulating film, 3-First aluminum wiring layer, 4...Vapor-phase growth oxide film, 5----S, 0. G, film, 6- second aluminum wiring layer, 7- vapor grown oxide film, vapor grown nitride film, plasma nitride film.
Claims (2)
層の間の層間絶縁膜として、プラズマ気相成長法による
酸化膜を第１層とし、塗布焼成酸化膜を第２層とし、気
相成長酸化膜を第３層とする３層構造からなる絶縁膜を
用いることを特徴とする半導体装置。(1) In a semiconductor device having a multilayer wiring structure, as an interlayer insulating film between wiring layers, an oxide film formed by plasma vapor deposition is used as the first layer, and a coated and fired oxide film is used as the second layer. A semiconductor device characterized by using an insulating film having a three-layer structure in which a film is a third layer.
有する半導体基板上に第１の配線層を形成後、プラズマ
気相成長法による酸化膜、回転塗布焼成法による塗布焼
成酸化膜、気相成長法による酸化膜を順次形成し、次に
第２の配線層を形成することを特徴とする半導体装置の
製造方法。(2) In a semiconductor device having multilayer wiring, after forming a first wiring layer on a semiconductor substrate having an insulating film, an oxide film is formed by plasma vapor phase epitaxy, a coated and fired oxide film is formed by spin coating and firing, and then vapor phase growth is performed. 1. A method for manufacturing a semiconductor device, comprising sequentially forming an oxide film using a method, and then forming a second wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20784790A JPH0362554A (en) | 1990-08-06 | 1990-08-06 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20784790A JPH0362554A (en) | 1990-08-06 | 1990-08-06 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0362554A true JPH0362554A (en) | 1991-03-18 |
Family
ID=16546514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20784790A Pending JPH0362554A (en) | 1990-08-06 | 1990-08-06 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0362554A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5308415A (en) * | 1992-12-31 | 1994-05-03 | Chartered Semiconductor Manufacturing Pte Ltd. | Enhancing step coverage by creating a tapered profile through three dimensional resist pull back |
| US5604380A (en) * | 1993-10-07 | 1997-02-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a multilayer interconnection structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60132344A (en) * | 1983-12-20 | 1985-07-15 | Nec Corp | Semiconductor device |
| JPS62193265A (en) * | 1986-02-20 | 1987-08-25 | Toshiba Corp | Manufacture of semiconductor device |
| JPS63142A (en) * | 1986-06-19 | 1988-01-05 | Toshiba Corp | Manufacture of semiconductor device |
-
1990
- 1990-08-06 JP JP20784790A patent/JPH0362554A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60132344A (en) * | 1983-12-20 | 1985-07-15 | Nec Corp | Semiconductor device |
| JPS62193265A (en) * | 1986-02-20 | 1987-08-25 | Toshiba Corp | Manufacture of semiconductor device |
| JPS63142A (en) * | 1986-06-19 | 1988-01-05 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5308415A (en) * | 1992-12-31 | 1994-05-03 | Chartered Semiconductor Manufacturing Pte Ltd. | Enhancing step coverage by creating a tapered profile through three dimensional resist pull back |
| US5604380A (en) * | 1993-10-07 | 1997-02-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a multilayer interconnection structure |
| DE19509203B4 (en) * | 1993-10-07 | 2004-06-17 | Mitsubishi Denki K.K. | Semiconductor device with a multilayer interconnect structure and method of manufacturing the same |
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