JPH01268356A - Multiscanning crt display device - Google Patents

Multiscanning crt display device

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Publication number
JPH01268356A
JPH01268356A JP9732388A JP9732388A JPH01268356A JP H01268356 A JPH01268356 A JP H01268356A JP 9732388 A JP9732388 A JP 9732388A JP 9732388 A JP9732388 A JP 9732388A JP H01268356 A JPH01268356 A JP H01268356A
Authority
JP
Japan
Prior art keywords
circuit
transistor
frequency
horizontal
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9732388A
Other languages
Japanese (ja)
Other versions
JP2573024B2 (en
Inventor
Norio Imaizumi
今泉 教男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
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Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP63097323A priority Critical patent/JP2573024B2/en
Publication of JPH01268356A publication Critical patent/JPH01268356A/en
Application granted granted Critical
Publication of JP2573024B2 publication Critical patent/JP2573024B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Synchronizing For Television (AREA)
  • Details Of Television Scanning (AREA)

Abstract

PURPOSE:To obtain an oscillation output signal as a continuous signal by constituting a horizontal oscillating circuit of a differential oscillating circuit and applying a voltage corresponding to the horizontal synchronizing signal frequency to the base of one transistor TR. CONSTITUTION:A horizontal oscillating circuit 3 consists of the differential oscillating circuit consisting of first and second TRs 4 and 8, and a voltage corresponding to the horizontal synchronizing signal frequency from a frequency- voltage converting circuit 2 is applied to the base of the first TR 4. Thus, the free-run frequency of the horizontal oscillating circuit is continuously changed, and the circuit is locked to the horizontal synchronizing signal having a wide-range frequency because the output signal of a phase comparing circuit 13 is applied to the base of the second TR 8.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は、通常のテレビジョン放送の水平同期信号に比
べ、高い周波数の水平同期信号を発生するコンピュータ
等からの映像信号を受像することが出来るマルチ走査形
CRT表示装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention is directed to receiving video signals from computers, etc. that generate horizontal synchronizing signals of a higher frequency than horizontal synchronizing signals of normal television broadcasting. This invention relates to a multi-scan CRT display device that can perform

(ロ)従来の技術 NTSC式方式のTV放送では水平周波数(水平同期信
号周波数)が15.75kHz程度に定められているが
、高解像度のコンピュータの出力映像信号では水平周波
数が20kHz以上のものがある。そのような水平周波
数の異なる種々の映像信号を単一の受像機で受像出来る
マルチ走査形TV受像機が特開昭61−242172号
公報に記載されている。前記公報に記載されたマルチ走
査形TV受像機によれば、水平周波数を周波数−電圧変
換回路によって20kHz以下、20〜30kHz。
(b) Conventional technology In TV broadcasting using the NTSC system, the horizontal frequency (horizontal synchronization signal frequency) is set at approximately 15.75 kHz, but the output video signal of a high-resolution computer has a horizontal frequency of 20 kHz or more. be. A multi-scan TV receiver capable of receiving such various video signals having different horizontal frequencies with a single receiver is described in Japanese Patent Laid-Open No. 61-242172. According to the multi-scan TV receiver described in the publication, the horizontal frequency is reduced to 20 kHz or less, 20 to 30 kHz, by a frequency-voltage conversion circuit.

30kHz以上というように判別し、その判別出力に応
じて水平発振回路の時定数回路の時定数を切換えている
。前記時定数回路の各時定数は、各周波数の範囲のフリ
ーラン周波数に対応する値となっているので、水平発振
回路はそれぞれの周波数範囲の中心となるフリーラン周
波数で発振することが出来る。その為、前記水平発振回
路は、高い周波数の水平同期信号にも十分にロックする
ことが出来、種々の映像信号を受信することが出来る。
It is determined that the frequency is 30 kHz or more, and the time constant of the time constant circuit of the horizontal oscillation circuit is switched according to the determined output. Since each time constant of the time constant circuit has a value corresponding to a free run frequency in each frequency range, the horizontal oscillation circuit can oscillate at a free run frequency that is the center of each frequency range. Therefore, the horizontal oscillation circuit can sufficiently lock even high-frequency horizontal synchronization signals and can receive various video signals.

(ハ)発明が解決しようとする課題 しかしながら、前記公報に記載された方法を用いると、
時定数を切換えなければならないので、切換えの瞬間に
発振出力信号が不連続になってしまうという問題がある
。又、容量の異なるコンデンサを準備し、それらをスイ
ッチで切換えなければならず、素子数が増加してしまう
。特に前記時定数回路を構成するコンデンサはIC(集
積回路)の外付けとなるので、IC化に際しても問題で
ある。
(c) Problems to be solved by the invention However, if the method described in the above publication is used,
Since the time constant must be switched, there is a problem in that the oscillation output signal becomes discontinuous at the moment of switching. Furthermore, it is necessary to prepare capacitors with different capacities and switch between them, which increases the number of elements. In particular, since the capacitor constituting the time constant circuit is externally attached to an IC (integrated circuit), it is also a problem when integrated into an IC.

(ニ)課題を解決するための手段 本発明は、上述の点に鑑み成きれたもので、水平同期信
号とフライバックパルスとの位相比較を行なう位相比較
回路と、該位相比較回路の出力信号を平滑する平滑回路
と、該平滑回路の出力信号に応じて発振周波数が制御さ
れる水平発振回路と、前記水平同期信号の周波数変化に
応じて前記水平発振回路のフリーラン周波数を変化させ
る為の制御信号を発生する周波数−電圧変換回路とを備
えるマルチ走査形CRT表示装置において、前記水平発
振回路をエミッタが共通接続された第1及び第2トラン
ジスタを有する差動型発振回路で構成し、前記第1トラ
ンジスタのベースに前記周波数−電圧変換回路の出力信
号を印加し、フリーラン周波数の調整を行なうとともに
、前記第2トランジスタのベースに前記平滑回路の出力
信号を印加し、発振周波数の調整を行なうようにしたこ
とを特徴とする。
(d) Means for Solving the Problems The present invention has been achieved in view of the above points, and includes a phase comparison circuit that performs a phase comparison between a horizontal synchronization signal and a flyback pulse, and an output signal of the phase comparison circuit. a horizontal oscillation circuit whose oscillation frequency is controlled according to the output signal of the smoothing circuit; and a horizontal oscillation circuit for changing the free run frequency of the horizontal oscillation circuit according to a frequency change of the horizontal synchronization signal. In a multi-scan CRT display device comprising a frequency-voltage conversion circuit that generates a control signal, the horizontal oscillation circuit is configured with a differential oscillation circuit having first and second transistors whose emitters are commonly connected, The output signal of the frequency-voltage conversion circuit is applied to the base of the first transistor to adjust the free run frequency, and the output signal of the smoothing circuit is applied to the base of the second transistor to adjust the oscillation frequency. It is characterized by what it does.

(*)作用 本発明によれば、水平発振回路を第1及び第2トランジ
スタから成る差動型発振回路で構成し、周、波数−電圧
変換回路からの水平同期信号周波数に応じた電圧を前記
第1トランジスタのベースに印加しているので、前記水
平発振回路のフリーラン周波数を連続的に変化させるこ
とが出来る。
(*) Effect According to the present invention, the horizontal oscillation circuit is constituted by a differential oscillation circuit consisting of first and second transistors, and the voltage according to the horizontal synchronizing signal frequency from the frequency and wave number-voltage conversion circuit is applied to the horizontal oscillation circuit. Since the voltage is applied to the base of the first transistor, the free run frequency of the horizontal oscillation circuit can be changed continuously.

又、前記第2トランジスタのベースに位相比較回路の出
力信号を印加しているので、発振周波数を調整すること
が出来る。
Furthermore, since the output signal of the phase comparison circuit is applied to the base of the second transistor, the oscillation frequency can be adjusted.

(へ)実施例 第1図は、本発明の一実施例を示す回路図で、(1)は
TV放送やコンピュータからの広範囲に渡る水平同期信
号が印加される入力端子、(2)は前記入力端子(1)
からの水平同期信号の周波数に応じた電圧を発生する周
波数−電圧変換回路、(≦)は前記周波数−電圧変換回
路(2)め出力電圧がベースに印加される第1トランジ
スタ(4)、電源(+Vcc)とアースとの間に直列接
続された抵抗り5)及びコンデンサ(6)から成る充放
電回路(ヱ)、前記抵抗(5〉及びコンデンサ(6)の
接続中点にベースが接続され、エミッタが前記第1トラ
ンジスタ(4)のエミッタに接続された第2トランジス
タ(8)、前記第1及び第2トランジスタ(4)及び(
8)の共通エミッタにエミッタが接続された第3トラン
ジスタ(9)、該第3トランジスタ(9)のベースにバ
イアスを印加する基準電圧発生回路(す)等を備え、前
記周波数−電圧変換回路(2)の出力電圧に応じてフリ
ーラン周波数が制御される水平発振回路、(11)は前
記水平発振回路(塁)の出力信号に応じて偏向コイル(
工2)に偏向電流を供給する水平偏向回路、(13)は
前記入力端子(1)からの水平同期信号と前記偏向コイ
ル(12〉からのフライバックパルスとの位相比較を行
なう位相比較回路、及び(14)は前記位相比較回路(
13)からの誤差出力を平滑し、平滑した直流電圧に応
じて前記水平偏向回路整)の発振周波数を制御する平滑
回路である。
(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. (1) is an input terminal to which a wide range of horizontal synchronization signals from TV broadcasts and computers are applied; Input terminal (1)
(≦) is a frequency-voltage conversion circuit that generates a voltage according to the frequency of a horizontal synchronization signal from the frequency-voltage conversion circuit (2); a first transistor (4) to which the output voltage is applied to the base; A charging/discharging circuit (2) consisting of a resistor (5) and a capacitor (6) connected in series between (+Vcc) and the ground, the base being connected to the connection midpoint of the resistor (5) and the capacitor (6). , a second transistor (8) whose emitter is connected to the emitter of the first transistor (4), the first and second transistors (4) and (
The frequency-voltage conversion circuit (8) includes a third transistor (9) whose emitter is connected to the common emitter of the third transistor (9), a reference voltage generation circuit (S) for applying a bias to the base of the third transistor (9), etc. (2) is a horizontal oscillation circuit whose free run frequency is controlled according to the output voltage; (11) is a deflection coil (11) according to the output signal of the horizontal oscillation circuit (base);
(13) is a phase comparison circuit that performs a phase comparison between the horizontal synchronizing signal from the input terminal (1) and the flyback pulse from the deflection coil (12); and (14) is the phase comparator circuit (
This is a smoothing circuit that smoothes the error output from 13) and controls the oscillation frequency of the horizontal deflection circuit according to the smoothed DC voltage.

まず、水平発振回路(りの発振動作について説明する。First, the oscillation operation of the horizontal oscillation circuit will be explained.

電源が投入されると、抵抗(5)を介してコンデンサ(
6)が充電され、第2トランジスタ(8)のベース電圧
は徐々に上昇する。第3トランジスタ(9)のベース(
点A)の電圧VNは、周波数−電圧変換回路(2)の出
力端(点B)の電圧V、に比べ十分高くなるように第1
抵抗乃至第3抵抗(15)乃至(17)の抵抗値が設定
されている。
When the power is turned on, the capacitor (
6) is charged, and the base voltage of the second transistor (8) gradually increases. The base of the third transistor (9) (
The voltage VN at point A) is set so that it is sufficiently higher than the voltage V at the output terminal (point B) of the frequency-voltage conversion circuit (2).
The resistance values of the resistors to the third resistors (15) to (17) are set.

その為、電源投入直後は第1及び第2トランジスタ(4
)及び(8)がオフし、第3トランジスタ(9〉がオン
している。前記第2トランジスタ(8)がオフであると
、トランジスタ(18)がオフとなり、充放電回路(Z
)の充放電を切換える第1切換回路として動作するトラ
ンジスタ〈19〉がオフ、又基準電圧発生回路(す)の
出力電圧を切換える第2切換回路として動作するトラン
ジスタ(20)がオフとなる。
Therefore, immediately after the power is turned on, the first and second transistors (4
) and (8) are turned off, and the third transistor (9> is turned on. When the second transistor (8) is turned off, the transistor (18) is turned off, and the charging/discharging circuit (Z
) is turned off, and the transistor (20) is turned off, which operates as a second switching circuit to switch the output voltage of the reference voltage generation circuit (2).

そして、前記コンデンサ(6)への充電が進み、第2ト
ランジスタ(8)のベース電圧が点Aの電圧v、iを超
えるようになると、第2トランジスタ(8)がオンし第
1及び第3トランジスタ(4)及び(9)がオフする。
Then, when the charging of the capacitor (6) progresses and the base voltage of the second transistor (8) exceeds the voltage v, i at point A, the second transistor (8) is turned on and the first and third Transistors (4) and (9) are turned off.

前記第2トランジスタ(8)がオンすると、トランジス
タ(18)がオンし、トランジスタ(19)及び(20
)がオンする。トランジスタ(19〉がオンすると、コ
ンデンサ(6)は抵抗(21)及び前記トランジスタ(
19)のコレクタ・エミツタ路を介して放電を開始する
ので、第2トランジスタ(8)のベース電圧は徐々に低
下する。
When the second transistor (8) is turned on, the transistor (18) is turned on, and the transistors (19) and (20) are turned on.
) turns on. When the transistor (19) is turned on, the capacitor (6) connects the resistor (21) and the transistor (
19), so that the base voltage of the second transistor (8) gradually decreases.

一方、トランジスタフ20)がオンすると点Aには第1
及び第2抵抗(15)及び(16)の抵抗値に応じた電
圧v、’が発生する。該電圧v□′の値は点Bの電圧v
Lに比べても小さい値(VH’ < VH)に設定され
ている。その為、第2トランジスタ(8)のベース電圧
が放電によって電圧vH以下になっても第3トランジス
タ(9)はオフしている。そして、放電が更に進ミ第2
トランジスタ(8)のベース電圧が点Bの電圧■1以下
まで達すると、第1トランジスタ(4)がオンし、第2
及び第3トランジスタ(8)及び(9)がオフする。す
ると、トランジスタ(18)がオフしトランジスタ(1
9〉及び(20)がオフする。前記トランジスタ(20
)がオフすると点A(7)電圧は初期状態と同じ電圧九
に復帰する。又、前記トランジスタ(19)がオフする
と、コンデンサ(6)の放電が停止する。その結果、初
期状態と同じ状態になり、コンデンサ(6)は再び抵抗
(5)からの電流によ−って充電され、以降この動作を
繰り返えす。
On the other hand, when the transistor OFF 20) is turned on, the first
And voltages v,' are generated according to the resistance values of the second resistors (15) and (16). The value of the voltage v□′ is the voltage v at point B
It is set to a value smaller than L (VH'< VH). Therefore, even if the base voltage of the second transistor (8) becomes lower than the voltage vH due to discharge, the third transistor (9) remains off. Then, the discharge progresses further and the second
When the base voltage of the transistor (8) reaches the voltage at point B 1 or less, the first transistor (4) turns on and the second transistor (4) turns on.
And the third transistors (8) and (9) are turned off. Then, transistor (18) turns off and transistor (1
9> and (20) are turned off. The transistor (20
) is turned off, the voltage at point A (7) returns to voltage 9, which is the same as the initial state. Furthermore, when the transistor (19) is turned off, the capacitor (6) stops discharging. As a result, the state is the same as the initial state, the capacitor (6) is charged again by the current from the resistor (5), and this operation can be repeated thereafter.

従って、水平発振回路(良〉の端子(22ンには第2図
の実線の如く上限値が電圧■8に又下限値が電圧vLに
規定された発振のこぎり波形を得ることが出来る。  
  ” 第2図の前記発振出力信号の下限値は、点Bの電圧■、
によって定まっている。ここで、前記1圧V、の値を太
きく LVt’(V+、’>VL)とすれば発振のこぎ
り波形の下限値が高くなり、その発振周波数は第2図の
点線aに示される如く高くなる。又前記電圧VLの値を
小さく()/L□(VL□<Vt)とすれば発振のこぎ
り波形の下限値が低くなり、その発振周波数は点線すに
示される如く低くなる。従って、水平発振回路(良)の
フリーラン周波数を周波数−電圧変換回路(2)の出力
電圧によって任意に定めることが出来る。
Therefore, at the terminal (22) of the horizontal oscillation circuit (good), it is possible to obtain an oscillating sawtooth waveform whose upper limit is defined as the voltage 8 and the lower limit is defined as the voltage vL, as shown by the solid line in FIG.
” The lower limit value of the oscillation output signal in Fig. 2 is the voltage at point B,
It is determined by Here, if the value of the above-mentioned 1 pressure V is made larger LVt' (V+, '>VL), the lower limit value of the oscillating sawtooth waveform will become higher, and the oscillation frequency will become higher as shown by the dotted line a in Figure 2. Become. If the value of the voltage VL is made small ( )/L□ (VL□<Vt), the lower limit value of the oscillating sawtooth waveform becomes low, and the oscillation frequency becomes low as shown by the dotted line. Therefore, the free run frequency of the horizontal oscillation circuit (good) can be arbitrarily determined by the output voltage of the frequency-voltage conversion circuit (2).

次に水平発振回路(3)の発振周波数を求める。Next, find the oscillation frequency of the horizontal oscillation circuit (3).

まず、充電期間Tcにおけるコンデンサ(6)の端子電
圧■。は、抵抗(5)に流れる電流を■とするとVc”
Vcc  Rot・I        −−−−−・・
・−−−−(1)〔ただし、Rotは抵抗(5)の抵抗
値〕となり、Q=C・V、  1=dQ/dtより電流
工はl−Ce+dVc/dt         +++
**+m++at  (2)〔ただし、CHIはコンデ
ンサ(6)の容量〕となる。ここで第(2)式を第(1
)式に代入し整理すると、 VCC=ROI(ColdVc/dt)+VC・−・−
・・−−−−(3)となる。
First, the terminal voltage (■) of the capacitor (6) during the charging period Tc. If the current flowing through the resistor (5) is ■, then Vc”
Vcc Rot・I --------・・
・---(1) [However, Rot is the resistance value of resistor (5)], and from Q=C・V, 1=dQ/dt, the electrician is l-Ce+dVc/dt +++
**+m++at (2) [However, CHI is the capacitance of capacitor (6)]. Here, equation (2) is converted into equation (1)
) and rearranging, VCC=ROI(ColdVc/dt)+VC・−・−
...---(3).

又、放電期間T、における抵抗(5〉に流れる電流をi
l、コンデンサ(6)の放電電流をi2、抵抗(21)
に流れる電流をi、とすれば、 i3w i1+ i、          ・・・・・
・・・・・・・ (4)となり、第(4)式は次式の如
く示される。
Also, the current flowing through the resistance (5) during the discharge period T is i
l, the discharge current of the capacitor (6) is i2, the resistor (21)
If the current flowing through is i, then i3w i1+ i, ...
(4), and the equation (4) is expressed as the following equation.

〔ただし、R11は抵抗(21)の抵抗値〕ここで、第
(5〉式を整理すると、 vec−co+Rat(dvc/at)+(Ro+/R
*++1)vc・・・・・・・・・・・・ (6)゛ となる。そして、発振出力信号の上限値を■0、下限値
を■1とし、充放電期間を求めると、充電期間Toは となり、放電期間TDは ・・・・・・・・・・・・ (8) となる。従って発振周波数fHは となる。ここで第(7)式及び第(8)式の下限値vL
は、周波数−電圧変換回路(2)の出力電圧に応じて定
まり、第(7)式及び第(8)式の値に応じて発振周波
数fHが定まるので、前記周波数−電圧変換回路(2)
の出力電圧に応じて水平発振回路(旦)のフリーラン周
波数f、を制御することが出来る。
[However, R11 is the resistance value of resistor (21)] Here, rearranging equation (5), vec-co+Rat(dvc/at)+(Ro+/R
*++1)vc・・・・・・・・・(6)゛. Then, when the upper limit value of the oscillation output signal is set to ■0 and the lower limit value is set to ■1, and the charging and discharging period is calculated, the charging period To becomes, and the discharging period TD becomes... (8 ) becomes. Therefore, the oscillation frequency fH becomes. Here, the lower limit value vL of equations (7) and (8)
is determined depending on the output voltage of the frequency-voltage conversion circuit (2), and the oscillation frequency fH is determined according to the values of equations (7) and (8).
The free run frequency f of the horizontal oscillation circuit can be controlled according to the output voltage of the horizontal oscillation circuit.

さて、水平偏向回路(11)は、波形整形回路(24)
からの発振出力信号に応じて偏向コイル(12)に偏向
電流を供給し、ブラウン管(図示せず)における電子ビ
ームの偏向動作を制御する。前記偏向コイル(12〉の
上端に発生するフライバックパルスは、位相比較回路(
13)の一方の入力端子に印加される。又、その他方の
入力端子には水平同期信号が印加されるので、両信号の
位相比較が行なわれ、その誤差出力が平滑回路(ロ)で
平滑される。
Now, the horizontal deflection circuit (11) is the waveform shaping circuit (24)
A deflection current is supplied to the deflection coil (12) according to the oscillation output signal from the oscillation output signal, thereby controlling the deflection operation of the electron beam in the cathode ray tube (not shown). The flyback pulse generated at the upper end of the deflection coil (12) is sent to the phase comparator circuit (12).
13). Further, since a horizontal synchronizing signal is applied to the other input terminal, a phase comparison between the two signals is performed, and the error output thereof is smoothed by a smoothing circuit (b).

そして、前記平滑回路(14)の出力直流電圧が抵抗(
23)を介してコンデンサ(6)の上端に印加される。
Then, the output DC voltage of the smoothing circuit (14) is applied to the resistance (
23) to the top of the capacitor (6).

位相差に応じて前記出力直流電圧が上昇すれば、前記コ
ンデンサ(6)への充電電流の値が増加するので発振出
力信号の周波数は高くなる。又逆に前記出力直流電圧が
下降すれば、前記充電電流の値が低下するので前記周波
数は低くなる。従って、水平発振回路(塁)は水平同期
信号の位相に同期して発振するようになる。
If the output DC voltage increases in accordance with the phase difference, the value of the charging current to the capacitor (6) increases, so the frequency of the oscillation output signal increases. Conversely, if the output DC voltage decreases, the value of the charging current decreases, so the frequency decreases. Therefore, the horizontal oscillation circuit (base) oscillates in synchronization with the phase of the horizontal synchronization signal.

つまり、第4図の回路においては、周波数−電圧変換回
路(2)の出力電圧に応じて水平発振回路(良)のフリ
ーラン周波数を調整した後、平滑回路(ロ)の出力電圧
によってその発振周波数を定めている。その為、前記水
平発振回路(塁)は広範囲の周波数の水平同期信号にロ
ックすることが可能となる。
In other words, in the circuit shown in Fig. 4, after adjusting the free run frequency of the horizontal oscillation circuit (good) according to the output voltage of the frequency-voltage conversion circuit (2), the oscillation frequency is adjusted according to the output voltage of the smoothing circuit (b). The frequency is determined. Therefore, the horizontal oscillation circuit (base) can lock onto horizontal synchronizing signals having a wide range of frequencies.

(ト)発明の効果 以上述べた如く本発明に依れば、水平発振回路を差動型
発振回路で構成し、発振のこぎり波形の下限値を定める
一方のトランジスタのベースに水平同期信号周波数に応
じた電圧を印加しているので、前記水平発振回路のフリ
ーラン周波数を到来する水平同期信号周波数に応じて最
適な値に設定することが出来る。又、フリーラン周波数
の設定をスイッチによらず連続的に切換えることが出来
るので、切換えの際にも発振出力信号を連続な形で得る
ことが出来る。
(G) Effects of the Invention As described above, according to the present invention, the horizontal oscillation circuit is configured with a differential type oscillation circuit, and the base of one transistor that determines the lower limit value of the oscillating sawtooth waveform is connected to the base of the horizontal synchronizing signal according to the frequency of the horizontal synchronizing signal. Since the same voltage is applied, the free run frequency of the horizontal oscillation circuit can be set to an optimal value according to the frequency of the incoming horizontal synchronizing signal. Further, since the setting of the free run frequency can be changed continuously without using a switch, the oscillation output signal can be obtained in a continuous form even when changing.

更に本発明に依れば時定数の切換えを必要としないので
、複数の時定数回路が不要となり素子数の削減が計れ、
IC化にも最適となる。
Furthermore, according to the present invention, there is no need to switch the time constant, so multiple time constant circuits are not required, and the number of elements can be reduced.
It is also ideal for IC implementation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例を示す回路図、及び第2図
は第1図の説明に供する為の波形図である。 (1)・・・入力端子、 (2)・・・周波数−電圧変
換回路、 (塁)・・・水平発振回路、 り4)・・・
第1トランジスタ、 (Z)・・・充放電回路、 (8
)・・・第2トランジスタ、 (9)・・・第3トラン
ジスタ、 (功〉・・・基準電圧発生回路、 (13)
・・・位相比較回路、 (14)・・・平滑回路、 (
19)・・・トランジスタ、 (20)・・・トランジ
スタ。
FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining FIG. 1. (1)...Input terminal, (2)...Frequency-voltage conversion circuit, (base)...Horizontal oscillation circuit, 4)...
First transistor, (Z)...charging/discharging circuit, (8
)...Second transistor, (9)...Third transistor, (Work)...Reference voltage generation circuit, (13)
...phase comparison circuit, (14) ...smoothing circuit, (
19)...transistor, (20)...transistor.

Claims (4)

【特許請求の範囲】[Claims] (1)水平同期信号とフライバックパルスとの位相比較
を行なう位相比較回路と、該位相比較回路の出力信号を
平滑する平滑回路と、該平滑回路の出力信号に応じて発
振周波数が制御される水平発振回路と、前記水平同期信
号の周波数変化に応じて前記水平発振回路のフリーラン
周波数を変化させる為の制御信号を発生する周波数−電
圧変換回路とを備えるマルチ走査形CRT表示装置にお
いて、前記水平発振回路をエミッタが共通接続された第
1及び第2トランジスタを有する差動形発振回路で構成
し、前記第1トランジスタのベースに前記周波数−電圧
変換回路の出力信号を印加し、フリーラン周波数の調整
を行なうとともに、前記第2トランジスタのベースに前
記平滑回路の出力信号を印加し、発振周波数の調整を行
なうようにしたことを特徴とするマルチ走査形CRT表
示装置。
(1) A phase comparison circuit that compares the phase of the horizontal synchronization signal and the flyback pulse, a smoothing circuit that smoothes the output signal of the phase comparison circuit, and an oscillation frequency that is controlled according to the output signal of the smoothing circuit. In a multi-scan CRT display device comprising a horizontal oscillation circuit and a frequency-voltage conversion circuit that generates a control signal for changing the free run frequency of the horizontal oscillation circuit in accordance with a frequency change of the horizontal synchronization signal, The horizontal oscillation circuit is constituted by a differential oscillation circuit having first and second transistors whose emitters are commonly connected, and the output signal of the frequency-voltage conversion circuit is applied to the base of the first transistor, and the free run frequency is A multi-scan CRT display device, characterized in that the output signal of the smoothing circuit is applied to the base of the second transistor to adjust the oscillation frequency.
(2)前記水平発振回・路内の第1トランジスタのベー
スに印加される電圧が発振のこぎり波形の下限値を定め
るようにしたことを特徴とする請求項第1項記載のマル
チ走査形CRT表示装置。
(2) The multi-scan CRT display according to claim 1, wherein the voltage applied to the base of the first transistor in the horizontal oscillation circuit determines the lower limit value of the oscillating sawtooth waveform. Device.
(3)前記水平発振回路内の第1及び第2トランジスタ
の共通エミッタにエミッタが接続された第3トランジス
タを設け、該第3トランジスタのベースに印加される基
準電圧に応じて発振のこぎり波形の上限値を定めるよう
にしたことを特徴とする請求項第2項記載のマルチ走査
形CRT表示装置。
(3) A third transistor is provided whose emitter is connected to the common emitter of the first and second transistors in the horizontal oscillation circuit, and the upper limit of the oscillation sawtooth waveform is determined according to the reference voltage applied to the base of the third transistor. 3. The multi-scan CRT display device according to claim 2, wherein a value is determined.
(4)水平同期信号周波数に応じた電圧がベースに印加
される第1トランジスタと、電源とアース間に直列接続
された抵抗とコンデンサから成る充放電回路と、エミッ
タが前記第1トランジスタのエミッタに共通接続される
とともにベースが前記抵抗及びコンデンサの接続中点に
接続された第2トランジスタと、2つの基準電圧を発生
する基準電圧発生回路と、該基準電圧発生回路の出力電
圧がベースに印加されるとともに、前記第1及び第2ト
ランジスタの共通エミッタにエミッタが接続された第3
トランジスタと、前記第2トランジスタの出力信号に応
じて前記充放電回路の充放電を切換える第1切換回路と
、前記第2トランジスタの出力信号に応じて前記基準電
圧発生回路の出力電圧を切換える第2切換回路とから成
り、前記第1トランジスタのベース電圧に応じてフリー
ラン周波数を調整するようにした水平発振回路を有する
ことを特徴とするマルチ走査形CRT表示装置。
(4) a first transistor to which a voltage according to the horizontal synchronization signal frequency is applied to the base; a charging/discharging circuit consisting of a resistor and a capacitor connected in series between a power supply and ground; and an emitter connected to the emitter of the first transistor; a second transistor that is commonly connected and whose base is connected to the connection midpoint of the resistor and the capacitor; a reference voltage generation circuit that generates two reference voltages; and an output voltage of the reference voltage generation circuit that is applied to the base. and a third transistor whose emitter is connected to the common emitter of the first and second transistors.
a first switching circuit that switches charging/discharging of the charging/discharging circuit according to an output signal of the second transistor; and a second switching circuit that switches the output voltage of the reference voltage generating circuit according to the output signal of the second transistor. A multi-scan CRT display device comprising a horizontal oscillation circuit comprising a switching circuit and a horizontal oscillation circuit whose free run frequency is adjusted according to the base voltage of the first transistor.
JP63097323A 1988-04-20 1988-04-20 Multi-scan CRT display Expired - Lifetime JP2573024B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63097323A JP2573024B2 (en) 1988-04-20 1988-04-20 Multi-scan CRT display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63097323A JP2573024B2 (en) 1988-04-20 1988-04-20 Multi-scan CRT display

Publications (2)

Publication Number Publication Date
JPH01268356A true JPH01268356A (en) 1989-10-26
JP2573024B2 JP2573024B2 (en) 1997-01-16

Family

ID=14189276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63097323A Expired - Lifetime JP2573024B2 (en) 1988-04-20 1988-04-20 Multi-scan CRT display

Country Status (1)

Country Link
JP (1) JP2573024B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155417A (en) * 1990-05-28 1992-10-13 Mitsubishi Denki Kabushiki Kaisha S-shaped correction capacitor switching device for automatic tracking monitor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5491051U (en) * 1977-12-08 1979-06-27
JPS6350165A (en) * 1986-08-19 1988-03-03 Mitsubishi Electric Corp Horizontal defiecting circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5491051U (en) * 1977-12-08 1979-06-27
JPS6350165A (en) * 1986-08-19 1988-03-03 Mitsubishi Electric Corp Horizontal defiecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155417A (en) * 1990-05-28 1992-10-13 Mitsubishi Denki Kabushiki Kaisha S-shaped correction capacitor switching device for automatic tracking monitor

Also Published As

Publication number Publication date
JP2573024B2 (en) 1997-01-16

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