JPH01273336A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH01273336A
JPH01273336A JP10327888A JP10327888A JPH01273336A JP H01273336 A JPH01273336 A JP H01273336A JP 10327888 A JP10327888 A JP 10327888A JP 10327888 A JP10327888 A JP 10327888A JP H01273336 A JPH01273336 A JP H01273336A
Authority
JP
Japan
Prior art keywords
wiring
external force
wiring layer
semiconductor integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10327888A
Other languages
Japanese (ja)
Inventor
Tadao Katanosaka
片野坂 直生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP10327888A priority Critical patent/JPH01273336A/en
Publication of JPH01273336A publication Critical patent/JPH01273336A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To fix a wiring layer of an upper layer against an external force and to prevent a short circuiting between wiring layers, by a structure wherein an insulating layer under the wiring layer is formed in an irregular configuration. CONSTITUTION:An insulating layer 2 deposited on a semiconductor substrate 1 is provided with recess parts 6 thereon so that the insulating layer 2 is formed in an irregular configuration. It is assumed that an external force is applied to a wiring layer 3a along a direction P1. In this case, since the wiring layer 3a has a large resistance to the external force due to the formation of the recess parts 6, the wiring layer 3a is prevented from shifting. Accordingly, the wiring layer 3a and a wiring layer 3b do not form a short circuit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit.

〔従来の技術〕[Conventional technology]

半導体集積回路の高集積度化に伴い、多層配線構造と配
線の微細化が進められている。また、多量生産とコスト
低減の点から、樹脂封止型が広く採用されている。
BACKGROUND OF THE INVENTION As semiconductor integrated circuits become more highly integrated, multilayer interconnect structures and interconnect miniaturization are progressing. Furthermore, from the standpoint of mass production and cost reduction, the resin-sealed type is widely adopted.

第3図(a)、(b)は従来の半導体集積回路の一例の
平面図及びc−c’線断面図である。
FIGS. 3(a) and 3(b) are a plan view and a sectional view taken along line cc' of an example of a conventional semiconductor integrated circuit.

素子領域が形成された半導体基板1に絶縁膜2を設け、
コンタクト部を開口し、配線3a、3bを設けた後、絶
縁膜4で覆う。しかる後、樹脂で封止する。この樹脂封
止において、配線3と樹脂との熱膨張率の相異、樹脂が
固化する時の収縮により配線3に外力P1.P2が加わ
る。
An insulating film 2 is provided on a semiconductor substrate 1 on which an element region is formed,
After the contact portion is opened and wirings 3a and 3b are provided, it is covered with an insulating film 4. After that, it is sealed with resin. In this resin sealing, an external force P1. P2 is added.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

半導体集積回路において、一つの配線3aと他の配線3
bとが、大きく離れている場合にはそれ程大きな問題に
ならないが、少ししか離れていない場合には問題を生じ
る。
In a semiconductor integrated circuit, one wiring 3a and another wiring 3
If they are far apart from each other, this will not be a big problem, but if they are only a little apart, a problem will arise.

第4図(a)、(b)は従来の半導体集積回路配線にお
ける問題点を説明するための平面図及びD−D’線断面
図である。
FIGS. 4(a) and 4(b) are a plan view and a sectional view taken along the line DD' for explaining problems in conventional semiconductor integrated circuit wiring.

熱膨張率の差、または樹脂が固化する時、P1方向から
外力が加わった場合、配線3bは底部が外力方向に対し
て大きいため、大きな抵抗力を示す。ところがP2方向
から外力が加わった場合、外力方向に対して配線底部が
小さいため、配線3b下の絶縁膜が平坦であった場合、
たやすく配線3bが移動する。一方、配線3aは絶縁膜
に穴をあけ、下層とコンタクトをとっているため、外力
に対して抵抗力が大きく移動しない。よって第4図(a
)に示すように、配線3aと3bとが短絡したり、第4
図(b)のように、配!3aにより配線3bの下層との
コンタクトが押し上げられ配線3bと下層とが非接触状
態になり回路動作が不良になってしまうという問題を生
ずる。
When an external force is applied from the P1 direction due to a difference in coefficient of thermal expansion or when the resin solidifies, the wiring 3b exhibits a large resistance force because the bottom portion is larger in the direction of the external force. However, when an external force is applied from the P2 direction, the bottom of the wiring is small with respect to the direction of the external force, so if the insulating film under the wiring 3b is flat,
The wiring 3b moves easily. On the other hand, since the wiring 3a makes a hole in the insulating film and makes contact with the lower layer, the resistance force does not change significantly against external force. Therefore, Figure 4 (a
), the wiring 3a and 3b may be short-circuited, or the fourth
As shown in figure (b), the distribution! 3a pushes up the contact between the wiring 3b and the lower layer, resulting in a non-contact state between the wiring 3b and the lower layer, resulting in poor circuit operation.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路は、上層の配線が外力に対して
移動することを防ぐ為に、下層の絶縁膜に凹凸をつけた
ものである。
In the semiconductor integrated circuit of the present invention, the lower layer insulating film is made uneven in order to prevent the upper layer wiring from moving due to external force.

いる。There is.

〔実施例〕〔Example〕

第1図(a>、(b)は本発明の第1の実施例の平面図
およびA−A’線断面図である。
FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of the first embodiment of the present invention.

本実施例では、半導体基板1の上に形成した絶縁WA2
に凹部6を設け、絶縁膜2の表面に凹凸をつけている。
In this embodiment, an insulating WA2 formed on a semiconductor substrate 1 is used.
A recess 6 is provided in the insulating film 2 to make the surface of the insulating film 2 uneven.

今、P方向から外力が加わったとする。この場合、配線
3aは凹部6の形成により外力に対して大きな抵抗力を
持つため、配線の移動に耐える。
Suppose now that an external force is applied from the P direction. In this case, the wiring 3a has a large resistance against external force due to the formation of the recess 6, so that it can withstand movement of the wiring.

従って配線3aと3bとが短絡することはない。Therefore, the wirings 3a and 3b will not be short-circuited.

第2図(a)、(b)は本発明の第2の実施例の平面図
及びB−B’線断面図である。
FIGS. 2(a) and 2(b) are a plan view and a sectional view taken along the line BB' of a second embodiment of the present invention.

この第2の実施例は、配線が絶縁膜4を介して二層に設
けられている。配線7aに沿って絶縁膜4にコンタクタ
用開口部を複数個設けることにより、絶縁膜4に凹凸を
つけた効果をもたせている。
In this second embodiment, wiring is provided in two layers with an insulating film 4 interposed therebetween. By providing a plurality of contactor openings in the insulating film 4 along the wiring 7a, the insulating film 4 has an uneven effect.

今、P工方向から外力が加わったとする。この場合、上
層配線7a、7bは各々の下層とのコンタクトがあるな
め、外力に対し、配線の移動に耐える大きな抵抗力をも
つ。
Suppose now that an external force is applied from the P direction. In this case, since the upper layer wirings 7a and 7b are in contact with their respective lower layers, they have a large resistance against external forces to withstand movement of the wirings.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、絶縁股上に凹凸をつけ
たので、外力に対し上層の配線を固定できる効果がある
As explained above, the present invention has an effect in that the upper layer wiring can be fixed against external forces because the insulating crotch is uneven.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、(b)は本発明の第1の実施例の平面図
及びA−A’線断面図、第2図(a)。 (b)は本発明の第2の実施例の平面図及びB−B′線
断面図、第3図(a)、(b)は従来の半導体集積回路
の一例の平面図及びc−c’線断面図、第4図(a)、
(b)は従来の半導体集積回路の配線における問題点を
説明するための平面図及びD−D’線断面図である。 1・・・半導体基板、2・・・絶縁膜、3.3a、3b
・・・配線、4・・・絶縁膜、5.5a、5b・・・コ
ンタクト部、6・・・凹部、7a、7b・・・上層配線
、8・・・絶縁膜、P、、P2・・・外力。
FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line A-A' of the first embodiment of the present invention, and FIG. 2(a). (b) is a plan view and a sectional view taken along line B-B' of the second embodiment of the present invention, and FIGS. 3(a) and 3(b) are a plan view and c-c' of an example of a conventional semiconductor integrated circuit. Line sectional view, Fig. 4(a),
(b) is a plan view and a sectional view taken along the line DD' for explaining problems in wiring of a conventional semiconductor integrated circuit. 1... Semiconductor substrate, 2... Insulating film, 3.3a, 3b
... Wiring, 4... Insulating film, 5.5a, 5b... Contact portion, 6... Concave portion, 7a, 7b... Upper layer wiring, 8... Insulating film, P, , P2. ...external force.

Claims (1)

【特許請求の範囲】[Claims]  素子領域が形成されている半導体基板に絶縁層と配線
とが形成されて成る半導体集積回路において、前記配線
の下の絶縁層に凹凸を設けたことを特徴とする半導体集
積回路。
1. A semiconductor integrated circuit comprising an insulating layer and wiring formed on a semiconductor substrate on which an element region is formed, characterized in that the insulating layer under the wiring is provided with projections and depressions.
JP10327888A 1988-04-25 1988-04-25 Semiconductor integrated circuit Pending JPH01273336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10327888A JPH01273336A (en) 1988-04-25 1988-04-25 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10327888A JPH01273336A (en) 1988-04-25 1988-04-25 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH01273336A true JPH01273336A (en) 1989-11-01

Family

ID=14349889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10327888A Pending JPH01273336A (en) 1988-04-25 1988-04-25 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH01273336A (en)

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