JPH0127520B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to its wiring structure.

Conventionally, Ge-
Taking advantage of the reversible electrical switching characteristics of amorphous semiconductors such as Se-Te, they have been put to practical use in some memory devices and switch circuit devices.

However, since it has been found that the switching characteristics of conventional amorphous semiconductor devices are accompanied by changes in the crystal structure, doubts have arisen about their reliability as switching elements, and the current situation is that this has not necessarily led to the expansion of practical use. . Ge in amorphous semiconductors
Amorphous semiconductors based on have low specific resistance. Therefore, if this is used for wiring, the leakage current will be large even when the wiring is disconnected (OFF), making it impractical. On the other hand, the resistivity of amorphous silicon is
The leakage current is high at 10 ⁷ to ^{10 10} Ω ^- cm, and the leakage current is small even when connected with amorphous silicon.

However, as a characteristic of amorphous semiconductor,
The present inventor has discovered that there are not only reversible electrical characteristics but also irreversible electrical characteristics, and by utilizing these irreversible characteristics, they can be put to practical use as highly reliable storage devices. .

That is, the inventors of the present invention sandwiched amorphous Si1 between electrodes 2 and 3 as schematically shown in FIG. 1, and when taking the voltage-current characteristics, as shown in FIG. , the current increases nonlinearly, switches from state A to state B at a certain threshold voltage T, and thereafter, even if a reverse voltage is applied, this state does not return to the original state, and irreversible switch characteristics are obtained. I found it.

The above amorphous Si1 is produced by implanting As, P, B, etc. ions into polycrystalline Si obtained by the CVD method, or by implanting As, P, B, etc. into a CVD polycrystalline Si film doped with an inert gas such as Ar. In the completely amorphous state obtained by ion implantation, or in the incomplete or semi-amorphous state in the middle of the completion, amorphous Si etc. containing impurities obtained by vacuum evaporation etc. The irreversible switch characteristics as shown in FIG. 2 could be obtained by any of the manufacturing methods.

The threshold voltage T of the irreversible switch characteristic shown in Fig. 2 decreases as the thickness of the amorphous Si film decreases, and also decreases as the impurity concentration in the amorphous Si film increases, resulting in a quasi-amorphous state rather than a fully amorphous state. had a lower value.

To explain the above phenomenon, the amorphous state
By passing an electric current through Si, the impurities contained in amorphous Si are activated by heat, and the short-range regularity of amorphous Si changes to long-range regularity due to heat, causing crystallization. It is thought that amorphous Si, which was initially a poor conductor, is transformed into crystalline Si, which is a good conductor. This phenomenon is caused by the addition of the two processes of ionization and crystallization mentioned above, but there are intermediate stages in this state, which cause the threshold voltage and current value of the V-I characteristic to differ. When applying voltage in a pulsed manner, shortening the pulse width (time) allows the characteristics to be maintained in the intermediate state.
It is also possible to switch in a short time by increasing the pulse voltage.

The present invention utilizes the irreversible switching action of such an amorphous semiconductor to provide a semiconductor memory device exclusively for electrical writing. The object of the present invention is to provide a read-only semiconductor memory device that can perform read-only operations.

The basis of the present invention for achieving the above object is that an irreversible amorphous semiconductor layer is formed on a first electrode wiring formed on a substrate, and a second electrode is formed on the irreversible amorphous semiconductor layer. A wiring layer is formed, and an irreversible amorphous semiconductor layer is formed at least at the intersection of the first electrode wiring layer and the second electrode wiring layer.

The present invention will be specifically described below, including Examples.

3 and 4 are schematic views showing the basic configuration of the present invention, and FIGS. 5 and 6 are sectional views showing specific examples of the present invention.

FIG. 3 is an example showing the basic concept of the present invention, in which metal electrode wirings l _x1 , l _x2 , l _y1 , and l _y2 are arranged so as to intersect in the X direction and the Y direction, and irreversible Amorphous semiconductor D11, D21, D1
2, D22 are arranged in a sandwich pattern. In this case, for example, if voltage is applied to the extraction electrodes V _y1 and V _x1 to the electrodes l _y1 and l _x1 , D11
initially had a poor conduction state, but becomes a good conduction state, and the other D21, D12, and D22 remain in a poor conduction state. For example, when D11 is "1",
D21, D12, and D22 are in a state where information of "0" is written. Like this D21, D12, D
In order to write information to 22, voltages are applied in the X direction and Y direction of the electrodes connected to each intersection.

FIG. 4 is another example showing the basic concept of the present invention, in which electrodes l _x1 , l _x2 , l _y1 , and l _y2 are disposed above and below the surface of the amorphous semiconductor film D, intersecting in the X and Y directions, Similarly to the above, when a voltage is applied to, for example, V _x1 and V _y1 , the amorphous semiconductor film at the intersection becomes a well-conductive state. In this case, since the amorphous semiconductor film itself is a poor conductor, adjacent intersections are not affected by the intersection of the electrodes to which voltage is applied.

FIG. 5 is a sectional view showing an embodiment of the present invention, in which a diffusion wiring layer 1 formed on the surface of a Si substrate 11 is shown.
2 and 13, and an amorphous semiconductor film 15 and an Al electrode wiring layer 16 are formed through contact holes made in an insulating film 14 formed thereon.
The diffusion wiring layers 12 and 13 correspond to X in the conceptual diagram of FIG.
The direction wiring and the Al electrode wiring 6 correspond to the Y direction wiring, and the amorphous semiconductor portion at the intersection thereof acts as a storage portion.

FIG. 6 shows an embodiment in which the conceptual diagram of FIG.
The amorphous semiconductor layers 25 and 26 are partially formed through the contact holes made in the contact hole, and the Al electrode wiring layer 27 is formed.
2 and 23 correspond to the X-direction wiring in FIG. 3, and the Al electrode wiring 27 corresponds to the Y-direction wiring, and the amorphous semiconductor film portions 25 and 26 at the intersection thereof act as a memory section.

Although a Si substrate is used as the substrate, the substrate may be an insulating substrate such as glass or sapphire, and electrode wiring may be formed thereon.

In addition, the amorphous semiconductor layer is
It may be formed on the surface of the semiconductor substrate by performing ion implantation treatment from above the diffusion wiring layer No. 3.

By creating a non-reversible amorphous semiconductor device which is sandwiched between the X and Y wiring lines formed on the surface of the substrate in a sandwich-like manner, it is possible to achieve low voltage and higher integration in the vertical direction of the device. Furthermore, by utilizing the irreversibility of amorphous silicon, a simple structure can be put to practical use as a circuit changeover switch for a programmable array.

[Brief explanation of drawings]

FIG. 1 shows a basic configuration diagram of the present invention, and FIG. 2 shows its basic electrical characteristics. 3 and 4 are schematic views showing the basic configuration of the present invention, and FIGS. 5 and 6 are sectional views showing specific examples of the present invention. 1, D11, D21, D12, D22, D, 1
5, 25...Amorphous semiconductor part, 2, 3, l _x1 ,
l _x2 , l _y1 , l _y2 , 12, 13, 16, 22, 23,
27... Electrode wiring, 11, 21... Substrate, 14, 24
...Insulating film.

Claims (1)

[Claims] 1. A semiconductor device having at least a first wiring layer and a second wiring layer, wherein the first wiring layer and the second wiring layer are connected by amorphous silicon. A semiconductor device characterized by: