JPH0127631B2 - - Google Patents

Description

[Detailed description of the invention]

When you connect a TV camera to a VTR and record, you can do so by operating a switch from the camera side.
It allows you to control the start and stop of a VCR. In such a device, when recording a video signal by fading it in and out, conventionally the level of the video signal was manually adjusted and a VTR control switch was operated at the same time. However, with this method,
The operation is complicated because two operations are performed at once, and there is a risk of erroneous operation. Another disadvantage was that the fade-in and fade-out times were not constant. In view of these points, the present invention is designed to enable fade-in and fade-out with a simple configuration. By the way, when performing a fade-in, the video signal is set to the minimum level, the VTR is started in this state, and then the level of the video signal is gradually increased.
In addition, when fading out, the level of the video signal is gradually lowered, and after it reaches the minimum level,
Stop the VCR. The present invention attempts to automatically perform such operations using a so-called microcomputer. An embodiment of the present invention will be described below with reference to the drawings. In Figure 1, light from subject 1 is transmitted to lens 2.
At the same time, horizontal and vertical synchronizing signals are supplied from the synchronizing signal generator 4 to the imaging tube 3, and a video signal is extracted from the imaging tube 3. This video signal is supplied to the encoder 5, where white balance and other corrections are performed. Further, this video signal is supplied to a mixing circuit 7 through a gain control circuit 6, and a synchronization signal, a burst signal, etc. from a synchronization signal generator 4 are added thereto, and outputted to a video output terminal 8. And the signal from this output terminal 8 is
It is supplied to the video input terminal of the VTR 20. Further, correction of the video signal in the encoder 5, etc. is performed using a microcomputer. That is, 9 is a microcomputer, and this computer 9 has a central processing circuit (CPU) 91,
A read-on memory (ROM) 92 in which operating programs for the CPU 91 are written, a random access memory (RAM) 93 for storing data, etc.
It is composed of an input/output circuit 94 and the like. and
The CPU 91, ROM 92, and RAM 93 are connected by an address bus line 95, a data bus line 96, and a control bus line 97, respectively. Also, between the CPU 91 and the input/output circuit 94 are a data bus line 95 and a control bus line 9.
Connected at 6. Note that these are composed of one-chip LSI. The computer 9 is supplied with the signal from the synchronization signal generator 4 and the signal from the encoder 5 to form a correction signal for white balance adjustment, etc., and this correction signal is supplied to the encoder 5. Furthermore, an arbitrary voltage from a volume 10 for setting a fade time is supplied to a comparator circuit 11. At the same time, the first stored content of the RAM 93 of the computer 9 is supplied to the DA conversion circuit 12 to be converted into an analog signal, and this signal is supplied to the comparison circuit 11. By supplying this comparison output to the computer 9, the voltage set by the volume 10 is AD converted and read into the first memory address of the RAM 93. Also, the contents of the second memory address of RAM93 are DA
A sampling pulse from the computer 9 is supplied to the sampling hold circuit 13 through the conversion circuit 12, and a voltage corresponding to the contents of the address is formed. This voltage is supplied to the gain control circuit 6. Further, a switch 14 for controlling the start/stop of the VTR 2 is connected to the computer 9, and the output terminal of the computer 9 is connected to the T-type flip-flop 1.
It is connected to the trigger terminal of 5. Then, the signal obtained at the Q output terminal of the flip-flop 15 is supplied to the computer 9, and the signal obtained at the Q output terminal of the flip-flop 15 is supplied to the computer 9.
6 is output. A signal from this terminal 16 is supplied to an external control terminal of the VTR 20, and the VTR 20 is driven while this signal is at a high potential. Further, a standby signal from the VTR 20 that is at a low potential when the VTR 20 is in the standby state is supplied to the reset terminal of the flip-flop 15 through the terminal 17 and further through the inverter 18. The following programs are stored in the ROM 92. The process will be explained below according to the flowchart shown in FIG. In the figure, when the program starts, it is determined in step [1] whether or not the switch 14 is turned on, and as long as it is not turned on, step [1] is repeated. When the switch 14 is turned on, the program proceeds to step [2] and the fade in/fade out program is executed. In other words, in step [2], volume 1
The voltage set at 0 is AD converted and sent to RAM93.
is read into the first memory address of . Next, in step [3], it is determined whether the read voltage is greater than or equal to a predetermined value. If the value is below the predetermined value, step [4]
A trigger signal is supplied to the flip-flop 15. Furthermore, in step [5], the gain control circuit 6
A digital value that maximizes the gain of , for example "FF" (however, the number in "" indicates a hexadecimal value, F = 15) is set in the second memory address of the RAM 93, This digital value is output and DA
The signal is supplied to a sampling hold circuit 13 through a conversion circuit 12. Then, in step [6], a sampling pulse is supplied to the sampling hold circuit 13, and the program is stopped. If the voltage is greater than a predetermined value in step [3], the process proceeds to step [7], where it is determined whether the output signal of the flip-flop 15 is at a high potential. When the output signal is at a low potential, the fade-in program from step [8] onwards is executed. That is, in step [8], the digital value "00" that minimizes the gain of the gain control circuit 6 is set in the second memory address, and this digital value is outputted and sent to the sampling and holding circuit 13 through the DA conversion circuit 12. Supplied. and step

At [9], a sampling pulse is supplied to the sampling hold circuit 13. Next, in step [10], a trigger pulse is supplied to the flip-flop circuit 15. Further, in step [11], a delay of (contents of the first memory address)×N (ms) is performed. Thereafter, in step [12], the contents of the second memory address are incremented by "1", and this digital value is output and supplied to the sampling and holding circuit 13 through the DA conversion circuit 12. Then, in step [13], a sampling pulse is supplied to the sampling hold circuit 13. Further, in step [14], it is determined whether the contents of the second memory address have become "FF" or not, and if not, the process returns to step [11]. When the content of the second memory address becomes "FF", the program is stopped. Further, when the output signal is at a high potential in step [7], the fade-out program in step [15] and subsequent steps is executed. That is, in step [15], a delay of (contents of the first memory address)×N (ms) is performed. Thereafter, in step [16], the contents of the second memory address are subtracted by "1", and this digital value is output and supplied to the sampling and holding circuit 13 through the DA conversion circuit 12. Then, in step [17], a sampling pulse is supplied to the sampling hold circuit 13. Further, in step [18], it is determined whether the contents of the second memory address have become "00" or not, and if not, the process returns to step [15]. When the contents of the second memory address become "00", the process proceeds to step [4] and the flip-flop 1
5 is supplied with a trigger signal. Further, in step [5], "FF" is set in the second memory address, and in step [6], the corresponding voltage is sampled and held, and the program is stopped. Therefore, in this circuit, when the switch 14 is turned on while the VTR 20 is stopped, the gain of the gain control circuit 6 is minimized, and then the signal at the VTR control terminal 16 is set to a high potential. Then, the gain of the gain control circuit 6 is increased every time set by the volume 10. Further, when the switch 14 is turned on while the VTR 20 is being driven, the gain of the gain control circuit 6 is lowered every time set by the volume 10, and after the gain is minimized, the VTR control terminal 16 is turned on.
signal is brought to a low potential. Further thereafter, the gain of the gain control circuit 6 is returned to the maximum. In this case, the number of stages in which the gain is changed is 256 from "00" to "FF", and this gain changes by 1 at every time set by the volume 10.
Since it changes step by step, by adjusting the volume 10, the length of time required for fade-in and fade-out can be determined. Furthermore, when the voltage set by the volume 10 is less than a predetermined value, the flip-flop 15 is immediately inverted without performing fade-in or fade-out, and the gain of the gain control circuit 6 is maximized. In this way, the video signal is faded in and faded out, and according to the present invention,
By setting the fade-in and fade-out times in advance with the volume, you can then automatically fade in and out by simply operating the VTR's control switch. Further, by adjusting the volume, the fade-in and fade-out times can be set arbitrarily, and the set time can always be kept at a constant value unless the volume is readjusted. It is also possible to adjust the volume during recording to make the fade-in and fade-out times different. It is also possible to supply a gain control signal to a gain control circuit of an audio signal system (not shown) to simultaneously fade in and out the image and audio.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an example of the present invention, and FIG. 2 is a diagram for explaining the same. 1 is a subject, 3 is an image pickup tube, 4 is a synchronization signal generator, 5 is a color encoder, 6 is a gain control circuit,
9 is a microcomputer, 10 is a time setting volume, 11 is a comparison circuit, 12 is a DA conversion circuit, 13 is a sampling hold circuit, and 14 is a
A VTR control switch, 15 a flip-flop circuit, and 20 a VTR.

Claims (1)

[Claims] 1. Retrieving the video signal from the imaging means through the gain control circuit and supplying the value stored in the first storage address of the first storage device to the gain control circuit through the DA conversion circuit and the sample hold circuit, In a method for controlling a television camera, the gain of the gain control circuit is controlled according to the value, and a control signal for controlling the operation of an external storage device is formed. None, this setting signal is stored in the second memory address of the first memory device, and when the recording start signal is supplied, the content stored in the first memory address of the first memory device becomes the gain. The gain of the control circuit is set to a minimum value, and then the control signal is set to a signal that causes the external recording device to enter a recording state, and the contents of the first storage address of the first storage device are The gain of the gain control circuit is increased at a predetermined timing according to the content stored in the second storage address of the first storage device, a fade-in operation is performed, and the recording end signal is output. When supplied, the contents of the first memory address of the first memory device are decreased at the predetermined timing, and the contents of the first memory address of the first memory device control the gain of the gain control circuit. After the fade-out operation is performed at the minimum value, the control signal is set as a signal that causes the external recording device to stop, and these operations are stored in a second storage device by the central processing circuit. A method of controlling a television camera according to a program provided.