JPH01276338A - Input/output emulating mechanism - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] "Purpose of invention" (Industrial application field) The present invention relates to an input/output crabmeat rate mechanism.

(Conventional technology) In recent years, due to advances in semiconductor technology, microprocessors,
Peripheral control LSIs and memory IJ LSIs have become available at relatively low prices. By appropriately combining these LSIs, a computer system with relatively high performance can be provided. On the other hand, standard OS has appeared in software as well.
This provided an environment in which a considerable number of distributed software packages could be distributed in Europe.

(Problems to be Solved by the Invention) Incidentally, in the above-mentioned computer system, the contents of input/output registers (parameters) may be changed to accommodate functional expansion. For this reason, software that was running on the hardware before expansion may no longer work properly.

To solve this problem, programmatic emulation of modified input/output registers is performed.

When a specific input/output register is IO-written, the hardware logic section issues an interrupt to the CPU. The emulation program started by the interrupt learns the address and gutter of the IO-written register from the CPU's registers, etc., and converts it to the correct value.

Then, the IO write is performed again to prevent malfunctions due to European extensions, and to maintain compatibility with conventional hardware due to function extensions.

However, if you follow the emulation described above, the CPU
When performance is improved and speed is increased, an interrupt is generated to the CPU after IO write to a specific processor, and IO is repeated until the emulation program starts running. A problem arises in that the write is performed and the information of the first IO write is lost.

The present invention has been made based on the above-mentioned circumstances, and uses a high-speed CPU, etc., to disturb the order of the information of multiple process zero writes performed before starting the emulated zologram. IO that remembers and is partially incompatible with the previous version
The purpose of this invention is to provide an input/output emulation mechanism that makes register writes compatible with software emulation.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a data bus and an address bus that retain the contents of a data bus and an address bus during input/output write to a specific register.
Address buffer and IO from CPU to IO register
Constantly monitors writes and writes IOs to certain IO registers
It detects that it is a write, issues an interrupt to the CPU, prompts the execution of the emulation program, and operates the buffer counter. In response to this, it is equipped with a buffer counter that indicates the next location on the buffer where all the contents of the data address bus should be stored, and data was set from a certain conventional user program to the input/output register of the function expansion. In this case, input/output addresses and data are memorized according to the order in which they were written.
The feature is that emulation is performed by a program.

(Function) According to the above configuration, when data is set to a specific IO register, the address value of the register on the address bus and data bus at that time.

A data value is stored in a data address buffer, where the location on the data address buffer is indicated by a buffer counter. The hardware logic section constantly monitors IO writes from the CPU to IO registers, determines whether there is any IO write to a specific register, and if there is, writes the current address bus and data to the data address buffer. It sends the contents of the bus, updates the buffer counter, and sends an interrupt signal to the CPU. This allows certain IO
When writing IO to a register, the address and data are stored in the order in which they were written.

As a result, it is possible to trace the multiple 0 writes to the IO registers performed from the first I'O write to the start of the emulation program, which could not be handled by conventional methods.

(Example) Hereinafter, examples of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, l is a CPU, which writes data into an IO register according to its program. Receives an interrupt (arrow) from the hardware logic section, which will be described later. 2 is an IO register, which is connected to CPU I via an address bus (dotted line) and a data bus (solid line). 3 is a hardware logic section. The hardware logic unit 3 performs IO from the CPU I to the IO register 2.
It monitors writes, and when an IO write to a specific IO register occurs, it sends the data and the contents of the address bus to the buffer and updates the buffer counter. A buffer counter 4 changes the storage address in both the data and address buffers under update control from the hardware logic section 3. Reference numeral 5 denotes an address buffer, which stores the value on the address bus sent from the hardware logic section 3 at the location indicated by the buffer counter. Or receive reading from the CPU. Reference numeral 6 is a data buffer, which stores the value on the data bus sent from the hardware logic unit 3 to the location indicated by the buffer counter. Or receive reading from the CPU.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. CPU 1 in the figure performs IO by user program etc.
Data is set (■0 write) for the resoster 2. The hardware logic unit 3 determines that the register is a register that performs emulation. The hardware logic unit 3 performs the following operations. Tsumushi, CPU
The contents of the address bus and data bus between IO register 2 and IO register 2 are transferred to address buffer 5. Send to data buffer 6,
It is stored in the location indicated by the buffer counter 4. Also, the buffer counter 4 is updated in preparation for the next IO write.

Further, at the same time as the above operation, an interrupt is issued to the CPU 7.

Address buffer 5. The storage of data in data buffer 6 continues until the inventive mechanism is disabled by the emulation program. The CPU 1 transfers control to the Chemie rate program in response to an interrupt from the hardware logic section 3. The CPU I uses an emulation program to control the address spacer, 5. The register address and data stored in the data buffer 6 at the time of writing 0 are read out and re-set to the register.

If it is determined by the buffer counter 4 that emulation of all IO-written registers has been completed, the emulation program is terminated and execution of the user program is continued.

"Effects of the Invention" As explained above, according to the present invention, it is possible to trace IO writes to the IO register performed multiple times from the first IO write to the start of the emulation program, which could not be handled by conventional methods. Then a tortoise is formed.

In addition, it is possible to provide software necessary for making data sets to IIO registers, which are partially incompatible with previous ones, compatible with software emulation.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. 1...CPU, 2...I/O register, 3...No-doware logic section, 4...Buffer counter,
5...Address buffer, 6...Data buffer.

Claims (1)

[Claims] A data/address buffer that holds the contents of the data bus and address bus during input/output writes to a specific register, and a data/address buffer that constantly monitors IO writes from the CPU to IO registers. A hardware logic section detects this, issues an interrupt to the CPU, prompts the execution of the emulation program, and operates the buffer counter.The hardware logic section receives update operations from this hardware logic section, and updates the next data on the buffer. It is equipped with a buffer counter that indicates the location where the contents of the address bus should be stored, and when data is set from a certain conventional user program to the input/output register of the function expansion, data is input according to the written order. An input/output emulation mechanism that stores output addresses and data and performs emulation using a program.