JPH01278143A - Noise eliminating circuit for clock - Google Patents

Abstract

PURPOSE:To avoid the occurrence of data reading errors by reproducing a clock free from superposed noises without affecting the waveform of the clock. CONSTITUTION:A synchronizing means 10 performs its synchronizing process without producing any inconvenience even though a 1st clock transmitted from a transmitting part and superposed with noises is asynchronous with a 2nd clock. Gate means 12 and 13 produce signals free from the influence of the noises superposed on the 1st clock from the signal received from the means 10 and the signal obtained by delaying said signal of the means 10 via a delay means 11. A reproduction manes 14 reproduces the clock having no disturbance to read of data and delayed by about several cycles of the 2nd clock above the time of the 1st clock out of the signals free from the noise influence and received from both means 12 and 13. Thus it is possible to prevent data reading errors produced at a receiving part.

Description

[Detailed Description of the Invention] [Summary] Clock noise that prevents data reading errors by removing noise that is superimposed on the clock when data is transferred by sending a clock and data in parallel on an interface. Regarding the elimination circuit, the purpose of preventing data reading errors is to connect the interface between the transmitting section and the receiving section so that the transmitting section sends out the clock and data in parallel, and the receiving section captures the data at the point where the clock changes. In the device, a first signal obtained by synchronizing the clock with a second clock having a higher frequency than the clock and a period longer than the width of the noise superimposed on the clock, and a second signal whose phase is inverted from the first signal. a synchronizing means for generating a second signal and generating a portion on the first and second signals in which the signal level corresponding to one cycle of the second clock is inverted corresponding to the position of noise superimposed on the clock; , a delay means for generating a third signal obtained by delaying the first signal by one cycle of the second clock, and a fourth signal whose phase is inverted from the third signal; a first gate means for generating a signal from which the influence of noise has been removed from the signal; a second gate means for generating a signal from which the influence of noise has been removed from the second signal and the fourth signal;
The apparatus includes a reproducing means for reproducing a clock obtained by removing noise superimposed on the clock from a signal sent by the first gate means and the second gate means.

[Industrial application field]

The present invention relates to a device that transmits a clock and data in parallel on an interface to transfer data, and more particularly to a clock noise removal circuit that removes noise superimposed on the clock to prevent data reading errors from occurring.

In information processing devices and the like, the transmitter sends a clock and data in parallel to the wiring that connects the interface between the transmitter and the receiver, and the receiver receives the data, for example, at the rising edge of the clock. When noise is superimposed on this clock, cracks occur in the clock waveform, and when data is captured at the rising edge generated by this waveform crack, the transferred data is read at a timing that is not in a state where it can be read accurately. There may be cases where accurate data cannot be read.

Therefore, it is necessary that the noise superimposed on the clock be removed in the receiving section without affecting the waveform of the clock.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional technique, and FIG. 5 is a diagram illustrating signals of a synchronous interface circuit.

The transmitter 1 and the receiver 2 each include a synchronous interface circuit, and the transmitter 1 sends a clock and data to the receiver 2. In this synchronous interface circuit, data is transferred as shown in FIG. 5 (al), and a clock as shown in FIG. It is sent out at a timing that positions it in the center.

By the way, noise is superimposed on this clock, and as shown in Fig. 5 (C
), when a crack occurs in the waveform, data may be read in response to the rising edges (■ or ◎) generated by the waveform crack. If data is read at such timing, normal data may not be read.

For this reason, conventionally, a filter that combines a resistor 4 and a capacitor 3 is used in the interface circuit that receives the clock of the receiver 2, which absorbs noise higher in frequency than the clock, and the reading circuit does not react to small noise. That's what I was doing.

[Problem to be solved by the invention]

As mentioned above, conventionally, noise was removed using a filter consisting of a combination of resistor 4 and capacitor 3, but if the noise is large, it is necessary to increase the capacitance of capacitor 3; In this case, the clock waveform becomes distorted and the data cannot be read accurately, so there is a problem that large noise cannot be removed.

In view of these problems, the present invention prepares a new lock with a period longer than the width of the noise to be removed in the receiver 2, and creates a signal obtained by synchronizing the noise-superimposed clock with the new lock. a delay means for delaying the signal sent by the synchronization means by one cycle of the new lock; a gate means for creating a signal unaffected by noise; The purpose of this invention is to provide a circuit equipped with a reproducing means for regenerating the clock from which the noise has been removed, to remove noise without affecting the clock waveform, and to prevent data reading errors from occurring.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

A second clock is input from terminal A, which has a higher frequency than the noise-superimposed clock sent by the transmitter and has a period longer than the width of the noise. Further, from terminal B, the first clock sent by the transmitter and on which noise is superimposed is input.

The synchronizing means 10 generates a first signal obtained by synchronizing a first clock manually inputted from terminal B with a second clock inputted from the terminal, and a second signal whose phase is inverted from that of this first signal.
The first signal is sent to the delay means 11 and the gate means 12, and the second signal is sent to the gate means 13.

The delay means 11 creates a third signal obtained by delaying the first signal by one cycle of the second clock, and a fourth signal whose phase is inverted from that of the third signal. Gate means 1
2 and a fourth signal to the gate means 13.

The gate means 12 uses the first signal and the third signal sent out by the synchronization means 10 and the delay means 11, respectively, to create a signal from which the influence of noise superimposed on the first clock is removed, The gate means 13 uses the second signal and the fourth signal sent out by the synchronization means 10 and the delay means 11, respectively, to create a signal from which the influence of noise superimposed on the first clock is removed, and reproduces the signal. The signals are sent to the means 14 respectively.

The reproduction means 14 reproduces a clock from which noise has been removed from the signals sent out by the gate means 12 and 13, and sends it to the terminal.

[Effect]

With the above configuration, the synchronizing means 10 processes the second clock so that there is no problem even if the first clock on which noise is superimposed and sent out by the transmitter is asynchronous, and the gate means 12 and 13 generate a signal from the signal sent out by the synchronization means 10 and the signal delayed by the delay means 11, from which the influence of noise superimposed on the first clock is removed, and the regeneration means 14 generates a signal by removing the influence of noise superimposed on the first clock. In order to regenerate a clock from the signals sent by the means 12 and 13, from which the influence of noise has been removed, although the second clock is delayed by several cycles of the first clock, it does not interfere with data reading.
Even if noise is superimposed on the clock sent out in parallel with the data from the transmitter, it is possible to prevent data reading errors from occurring in the receiver.

[Embodiment] FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.
FIG. 3 is a time chart explaining the operation of FIG. 2.

At the time of initial setting, a reset signal is input from terminal C to the R terminal of D flip-flops 5 and 6 and JK flip-flop 9, and resets D flip-flops 5 and 6 and JK flip-flop 9, respectively.

From terminal B, a clock ■ from the transmitter with noise superimposed on it, as shown in Figure 3 clock ■, is input, and from terminal A, the noise that is higher in frequency than this clock ■ and which is superimposed on this clock ■ and which you want to remove is input. The third period whose period is longer than the width of
A clock ■ as shown in the figure Clock ■ is input.

In the D flip-flop 5, the clock ■ is inputted to the D terminal, and the clock ■ is inputted to the CLK terminal. Therefore, when the clock ■ rises after the clock ■ becomes "1", "1" is sent from the Q terminal as shown in FIG.
When the clock ■ rises after the clock ■ falls, "0" is sent from the Q terminal.

However, if noise is superimposed on the clock ■, and this noise causes waveform cracking as shown in FIG. 3 [phase], the D flip-flop 5 is connected to the Q terminal "0" is sent out for one period of the clock ■. Furthermore, as shown in FIG. 3@, if the clock ■ has a waveform crack due to noise, "1" is sent from the Q terminal for one period of the clock ■, as shown in FIG. 30 as well.

In the D flip-flop 6, the output of the Q terminal of the D flip-flop 5 is inputted to the D terminal, and as shown in FIG.
Corresponding to the level change at the Q terminal of the D flip-flop 5, a signal (2) having the same level change is sent from the Q terminal to the NOR circuit 7 with a delay of one period of the clock (2).

The D flip-flop 6 is connected to the NOR circuit 8 as shown in FIG.
This change means that a signal ■ whose phase is inverted is sent from the terminal, and the D flip-flop 5 sends a signal ■ shown in Figure 3 ■ to the NOR circuit 7, whose phase is inverted. The signal ■ is sent to the NOR circuit 8 from the Q terminal.

Therefore, the NOR circuit 7 sends a signal (2) which is not affected by noise to the J terminal of the JK circuit board 9, as shown in FIG.
Send the signal 2, which is not affected by noise, to the terminal of JK Flip-Flo Knob 9.

A clock ■ is input to the CLK terminal of the JK flip-flop 9, and the JK flip-flop 9 has a clock ■ as shown in Figure 3.
As shown in FIG. 2, a noise-free clock (2) with the same period as the clock (2) is sent from the Q terminal to the terminal, although it is delayed by several cycles of the clock (2) than the clock (2).

〔Effect of the invention〕

As described above, the present invention reproduces a clock from which noise superimposed on the clock has been removed without giving any shape to the clock waveform, thereby making it possible to prevent data reading errors from occurring.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a block diagram of a circuit showing an embodiment of the present invention, Fig. 3 is a time chart explaining the operation of Fig. 2, and Fig. 4 is a block diagram of the principle of the present invention.
The figure is a block diagram explaining a conventional technique, and FIG. 5 is a diagram explaining signals of a synchronous interface circuit. In the figure, 1 is a transmitter, 2 is a receiver, 3 is a capacitor, 4 is a resistor, 5.6 is a D flip-flop, 7.8 is a NOR circuit, 9 is a JK flip-flop, 10
11 is a delay means, 12 and 13 are gate means, and 14 is a reproduction means. ku m Hard water technique j2g Rabbit sun and moon ゛'mouth/Nfuromine 4 Diagram synchronized type in 2 face Kasumirou state language Σ theory υ Tsukizuro Zutei 5
(2)

Claims (1)

[Claims] Connecting the interfaces of the transmitting section and the receiving section, causing the transmitting section to send a clock and data onto the interface in parallel, and the receiving section using the changing point of the clock as a reference,
In the data capturing device, a first signal obtained by synchronizing the clock with a second clock having a higher frequency than the clock and a period longer than the width of noise superimposed on the clock; A second signal whose phase is inverted from that of the signal is created, and a signal corresponding to one period of the second clock is generated on the first and second signals corresponding to the position of the noise superimposed on the clock. a synchronizing means (10) that generates a portion where the signal level is inverted; a third signal obtained by delaying the first signal sent by the synchronizing means (10) by one period of the second clock; A delay means (1
1), and a first gate means (12) for generating a signal from which the influence of the noise is removed from the first signal and the third signal sent out by the synchronization means (10) and the delay means (11), respectively. and a second gate means (13) for generating a signal from which the influence of the noise is removed from the second signal and the fourth signal sent out by the synchronization means (10) and the delay means (11), respectively; Reproducing means (14) for reproducing a clock obtained by removing noise superimposed on the clock from the signals sent by the first gate means (12) and the second gate means (13), and receiving the clock from the transmitter. What is claimed is: 1. A clock noise removal circuit, characterized in that a clock from which noise superimposed on the received clock has been removed is regenerated, and the clock is supplied to the receiving section.