JPH01280936A - Coding/decoding processing control system - Google Patents

Abstract

PURPOSE:To prevent noise due to fluctuation of synchronization of a received coded data by transferring a coded data from a reception buffer to a 1st data area if the 1st data area is not in use and transferring the coded data from the reception buffer to a 2nd data area when the 1st data area is busy. CONSTITUTION:When an interruption flag is set before the start of coding processing, a coded data is transferred from the reception buffer 3 to the 1st data area 4. When an interrupt flag is set before decoding processing, if the 1st data area 4 is idle, the coded data is transferred and transferred to the 2nd data area 5 when not idle and the coded data is transferred from the 2nd data area 5 to the 1st data area 4 by the end of decoding processing. Thus, the memory capacity is saved and the fluctuation of frame synchronization of the received coded data due to the state change of a transmission line is absorbed by the 1st and 2nd data areas 4, 5, then the generating of noise is prevented.

Description

[Detailed Description of the Invention] [Summary] Regarding a code/decoding processing control method that performs coding and decoding using one digital signal processing processor, the work area is expanded to eliminate noise caused by fluctuations in synchronization of received coded data. The first digital signal processing system includes one digital signal processing buffer, a transmission buffer, and a reception buffer. A second data area is provided, and an interrupt flag is set each time one frame of encoded data is received and accumulated in the reception buffer, and the digital signal processor starts encoding processing at the rising edge of the frame signal. , send the encoded data to the transmitter
In addition to the first signal, when the encoded data is read from the first data area and the decoding process is started at the falling edge of the frame signal, and the interrupt flag is set before the start of the encoding process, the first When the encoded data is transferred from the reception buffer to the data area 1 and the interrupt flag is set before the start of the decoding process, if the first data area is unused, the first data area is Transferring encoded data from the reception bar to a data area, and when the first data area is in use, transferring encoded data from the reception bar to the second data area;
Reset each interrupt flag. Further, the encoded data is configured to be transferred from the second data area to the first data area upon completion of the decoding process.

[Industrial application field]

The present invention relates to a code/decoding process control system that performs encoding and decoding using one digital signal processor.

In the system of highly efficient encoding and transmission of audio signals, image signals, etc., in order to simplify and downsize the equipment on the subscriber side,
A method has been adopted in which one digital signal processor is used to perform encoding and decoding. In such an encoding/decoding process control system, it is desired that the encoding and decoding processes be performed economically without noise generation.

[Conventional technology]

FIG. 6 is an explanatory diagram of a system configuration that performs encoding processing and decoding processing using one digital signal processing processor (DSP) 31 as described above, and 32 is a transmitting/receiving section;
33 is a memory, 34 is an A/D converter, 35 is a D/A converter, 36 is a hybrid circuit (H), 37 is a telephone,
38 is a sending buffer (SBF), 39 is a receiving buffer (RBF), and 40 is a switching network.

The analog audio signal from the telephone 37 is sent to the A/D converter 3.
4, the signal is converted into a digital signal and sent to the digital signal processing processor 31, where it is highly efficiently encoded on a frame-by-frame basis. One frame of the audio signal is, for example, l 5
ms or 32 ms, and if the audio signal is sampled at 8 KHz, the number of samples will be 128 or 256.

Also, if one sample is 8 bits, then 64 Kb/
The bit rate is s.

The digital signal processing processor 31 has the aforementioned 64K
A high-efficiency encoding process is performed to compress the b/s audio data to 16 K b/s or 8 K b/s using adaptive predictive coding, etc., and the encoded data is temporarily stored in the transmission buffer 38. , read out at a constant speed, send it out, and transmit it to the other subscriber via exchange y440.

Also, the encoded data transmitted from the other subscriber via the switching network 40 is received and stored in the reception buffer 39, and an interrupt request IRQ is sent to the digital signal processing processor 31 upon reception of ① frames. Digital signal processing processor 3
1 reads encoded data from the reception buffer 39 in response to this interrupt request IRQ, performs decoding processing, adds the decoded data to the D/A converter 35, converts it into an analog audio signal, and sends it through the hybrid circuit 36. and add it to telephone 37.

FIG. 7 is a diagram explaining the above-mentioned processing timing, in which (a) shows a frame signal, (b) shows an encoding process, and (C) shows a decoding process. Encoding processing is started by the rising edge of the frame signal, and decoding processing is started by an interrupt request IRQ upon reception of one frame of encoded data, as described above. In FIG. 7, an interrupt request IR is sent during the encoding process.
Indicates the case where Q is added, the encoding process is interrupted by the interrupt request IRQ, the decoding process is started as shown in tc+, and when the decoding process is finished, the encoding process is restarted. .

FIG. 8 is a flowchart of a conventional example, in which it is determined whether or not the frame signal is rising, and if it is a rising edge, the encoding process is 0.
Start. Then, it identifies whether there is an interrupt request or not, and if there is no interrupt request, it continues the encoding process, and if there is an interrupt request, it interrupts the encoding process and starts the decoding process [phase]. . When this decoding process is completed, the encoding process is restarted [phase].

[Problem to be solved by the invention]

By having a configuration in which one digital signal processing processor 31 performs encoding processing and decoding processing,
The configuration can be small and economical. However, on the encoding processing side, it is necessary to secure a memory area for storing input data until it is processed, and a memory area for requesting data for the next frame for protection in the event of an interrupt. Due to interrupt requests during the encoding process, a memory area is required to save data during the encoding process.Therefore, it is necessary to secure a large work area for the encoding process, and for this reason, a large capacity memory is required. There was a flaw that made it necessary.

Furthermore, although the encoding process can be started in synchronization with the frame signal, the decoding process must be started in synchronization with the frame of the received encoded data. A fluctuation of several microseconds occurs in frame synchronization of received encoded data. There was a drawback that noise was generated due to fluctuations in frame synchronization.

For example, when the encoding process is started as shown in (bl) by the rising edge of the frame signal shown in (al) in FIG. 9, and an interrupt request IRQ is added in synchronization with the falling edge of this frame signal, that is, When the frame signal of the encoding process and the frame of the received encoded data are synchronized, the decoding process starts as shown in (C), and the decoding process Pl ends before the next frame signal rises. , by outputting the decoded data as shown in fd) at the rising edge of the frame signal, continuity with the decoded data of the previous frame is maintained.

(- However, due to fluctuations in the frame synchronization of the received encoded data, the interrupt request IRQ may be added late from the falling edge of the frame signal, as shown by the dotted arrow. In this case, (el The decryption process will start as shown,
When the end timing is after the rise of the frame signal, the decoded data of the previous frame is repeatedly output in the shaded part of fl, and the decoded data is output when the decoding process ends. , the decoded data in the shaded portion is 1, and does not have continuity, so it becomes noise when converted to an analog audio signal.

An object of the present invention is to prevent noise caused by fluctuations in the synchronization of received encoded data without enlarging the work area.

[Means to solve the problem]

The encoding/decoding processing control method of the present invention starts the encoding processing at the rising edge of a frame signal, and starts the decoding processing at the falling edge of the frame signal, and will be explained with reference to FIG.

In the coding/decoding processing control method that includes one digital signal processing processor 1, transmission buffer 2, and reception buffer 3 and switches between coding processing and decoding processing at a fixed time, the first method is as follows. Second data areas 4 and 5 are provided, and an interrupt flag is set each time encoded data for one frame is received and accumulated in the reception buffer 3, and the digital signal processing processor 1 performs encoding at the rising edge of the frame signal. Processing is started, and encoded data is read out from the first data area 4 at the falling edge of the frame signal, and decoding processing is started.

Also, if the interrupt flag is set before the encoding process starts,
When the encoded data is transferred from the reception buffer 3 to the first data area 4 and the interrupt flag is reset, and when the interrupt flag is set before the start of the decoding process, the first data area 4 is When in use, encoded data is transferred from reception buffer 3 to first data area 4 to reset the interrupt flag, and when first data area 4 is in use, encoded data is transferred from reception buffer 3 to first data area 4. The encoded data is transferred from the reception buffer 3 to reset the interrupt flag. Further, upon completion of the decoding process, encoded data is transferred from the second data area 5 to the first data area 4.

[Effect]

The first and second data areas 4.5 can be formed in the internal memory or external memory of the digital signal processing processor 1, and receive data from the reception buffer 3 to the first data area 4 or the second data area 5. Transfer the encoded data from the second data area 5 to the first data area 4
It has a configuration to transfer encoded data to.

Further, the digital signal processor 1 starts the encoding process at the rising edge of the frame signal, and the decoding process at the falling edge of the frame signal, regardless of fluctuations in the frame synchronization of the received encoded data. The decoding process is performed by reading encoded data from the first data area 4. Also, receive buffer 3
When one frame of encoded data is received, an interrupt flag is set. The digital signal processing processor 1 is
This il+include flag controls data transfer between the reception buffer 3 and the data areas 4 and 5. That is, when the interrupt flag is set before the start of the encoding process, the encoded data is transferred from the reception buffer 3 to the first data area 4, and when the interrupt flag is set before the start of the decoding process. determines whether the first data area 4 is in use,
If it is in use, the encoded data is transferred from the reception buffer 3 to the first data area 4, and if it is in use, the encoded data is transferred from the reception buffer 3 to the second data area 5. Then, upon completion of the transfer, the interrupt flag is reset.

Furthermore, since the decoding process is performed by reading the encoded data from the first data area 4, the encoded data in the second data area 5 is transferred to the first data area 4 upon completion of the decoding process.

Therefore, fluctuations in the frame synchronization of received encoded data are absorbed by the first and second data areas, eliminating the generation of noise and preventing interruption of the encoding process. There is no need to secure an area for this purpose.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, where II is a digital signal processing processor, 12 is a transmitter/receiver, 13 is an external memory, 14 is an A/D converter, 15 is a D/A converter, and 16 is a The hybrid circuit includes a telephone set 17, a transmitting buffer 18, a receiving buffer 19, and first and second data areas 20 and 21. Although this embodiment shows the case where the first and second data areas 20.21 are formed in the external memory 13, it is also possible to form them in the internal memory of the digital signal processing processor 11.

The digital signal processor 11 starts encoding processing for band compression of the digital signal converted by the A/D converter 14 at the rising edge of the frame signal, and adds encoded data to the transmission buffer 18 . Also, upon the fall of the frame signal, encoded data is read out from the first data area 20 to start decoding processing, and the decoded data is added to the D/A converter 15 and converted into an analog audio signal.

Also, the reception buffer 19 sets an interrupt flag every time it receives one frame of encoded data. When the digital signal processor 11 identifies the setting of the interrupt flag, it causes the encoded data to be transferred from the reception buffer 19 to the first or second data area 20.21 by direct memory access control or the like. In this case, when the interrupt flag is set before the start of the encoding process, the data is transferred to the first data area 20, and when the interrupt flag is set before the start of the decoding process, the first data If the area 20 is unused (if the decoding process of the previously transferred encoded data has been completed and the encoded data has not been accumulated), the data is transferred to this first data area 20, and this If the first data area is not unused (unless the decoding process of the previously transferred encoded data has not been completed), it is transferred to the second data area 21 and allocated upon completion of transfer in each case. The included flag is reset. Then, the encoded data transferred to the second data area 21 is transferred to the first data area 20 when the decoding process of the encoded data transferred to the first data area 20 is completed.

FIG. 3 is a flowchart of an embodiment of the present invention, in which it is determined whether the frame signal is rising or not, and if it is rising, the interrupt flag is determined (2). If the interrupt flag is not set (L''), start the encoding process as is.

Also, if the interrupt flag is set (“H”), the first
Transfer the encoded data from the reception buffer 19 to the data area 20 of (2). Then reset the interrupt flag■
.

When the encoding process ends and the frame signal falls, the decoding process starts. In that case, the interrupt flag is first determined (2). If the interrupt flag is not set (L''), read the encoded data from the first data area 20 and perform decoding processing, or if the interrupt flag is set (``H''), Determine whether or not the first data area 20 is unused. If it is unused, transfer the encoded data from the reception buffer 19 to the first data area 20.
■Reset the interrupt flag. If the data area 20 of the writer 1 is in use, the encoded data is transferred from the reception buffer 19 to the second data area 21 [phase], the interrupt flag is reset, and the decoding process is performed @.

After the decoding process is completed, it is determined whether or not the second data area 21 has been used. If 0° has been used, the encoded data is transferred to the first data area 20. Then, return to the first step ■.

FIG. 4 is an explanatory diagram of the operation of the embodiment of the present invention, in which fa) is a frame signal, (b) is the first data area 20, (C
) is the second data area 21, (dl indicates decoded data, and 1a, 2a, 6a, 7a, and 3b).

4b and 5b show examples of setting timings of interrupt flags corresponding to frame numbers 1 to 7 of received encoded data, respectively, where a shows after the fall of the frame signal and b shows after the rise of the frame signal. That is, this shows a case where there is fluctuation in frame synchronization of received encoded data. Also (b), (
cl, 1 to 7 in (d) correspond to frame numbers 1 to 7 of the received encoded data, respectively.

The relationship between the frame signal and the encoding and decoding processes is as shown in (al) and (b) in Figure 5, the encoding process starts when the frame signal rises, and the decoding process starts when the frame signal falls. This means that the encoding process will not be interrupted due to an interrupt occurring during the encoding process as in the conventional example.Therefore, there is no need to reserve an area for the save data. This allows you to minimize the work area.

When the interrupt flag is set at the timing 1a shown in FIG. 4(a) due to the reception of the encoded data of frame number 1, after the decoding process is started by the fall of the frame signal, Since this is before the start of the encoding process, the interrupt flag is determined at the next rising edge of the frame signal (see step (2) in FIG. 3). Therefore, this encoded data is transferred to the first data area 20 and decoded at the next falling edge of the frame signal, and the decoded data of frame number l is transferred to the next rising edge of the frame signal.
(Output as shown in dl.

Also, when the interrupt flag is set at timing 2a, it is before the encoding process starts, and the encoded data of frame number 2 is also transferred to the first data area 20, and the next falling edge of the frame signal The decoding process is started, and at the next rising edge of the frame signal, the decoded data of frame number 2 is outputted next to the decoded data of frame number 1, as shown in (dl).

Also, if the frame synchronization phase of the encoded data of frame number 3 advances compared to the frame synchronization phase of the encoded data of frame number 1.2, and the interrupt flag is set at timing 3b, the decoding process starts. Since it has been set previously, it is determined whether the first data area 20 is unused (see step 3 in FIG. 3). In this case, the first
Since the encoded data of frame number 2 has been transferred to the second data area 20, the encoded data of frame number 3 is transferred to the second data area 21. Therefore, the first and second data areas 20.21 have frame numbers 2.
This means that 3 encoded data are stored.

When the decoding process of the encoded data of frame number 2 is completed, the encoded data of frame number 3 is transferred from the second data area 21 to the first data area 20. Also, receiving the encoded data of frame number 4,
When the interrupt flag is set at timing b, the encoded data is transferred to the second data area 21 based on a determination before the start of the decoding process. Similarly, when encoded data of frame number 5 is received, the second data area 21
will be transferred to.

If the frame synchronization of the encoded data of the next frame number 6 is delayed and the interrupt flag is set at timing 6a, the encoded data will be stored in the first data area 20 as in the case of frame number 1.2. is transferred. Then, the decoding process is started at the falling edge of the frame signal, and the decoded data is output at the next rising edge. As shown in (dl), fluctuations in the frame synchronization of the received encoded data are absorbed and decoding data can maintain continuity.

Although the above-mentioned embodiment shows the case of highly efficient encoding of an audio signal, it can also be applied to the case of highly efficient encoding for transmitting/receiving an image signal.

〔Effect of the invention〕

As explained above, according to the present invention, encoding processing and decoding processing are switched at regular intervals and performed by one digital signal processing processor 1. In this case, the first . When a second data area 4.5 is provided and an interrupt flag is set each time one frame of encoded data is received in the reception buffer 3, and the interrupt flag is set before the encoding process starts. transfers the encoded data from the reception buffer 3 to the first data area 4, and if the interrupt flag is set before the decoding process, the encoded data is transferred to the first data area 4 if it is empty. Data is transferred, if it is not empty, it is transferred to the second data area 5, and when the decoding process is completed, the encoded data is transferred from the second data area 5 to the first data area 4. Digital signal processing Since no interruption is performed during the encoding process by the processor 1, there is no need to secure an area for save data, and there is an advantage that the memory capacity can be reduced.

Also, fluctuations in the frame synchronization of received encoded data due to changes in the state of the transmission path, etc.
This has the advantage of preventing the generation of noise.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a flowchart of an embodiment of the present invention, and FIG. 4 is an explanatory diagram of the operation of an embodiment of the present invention. Fig. 5 is an explanatory diagram of switching between frame signals and encoding/decoding processing, Fig. 6 is an explanatory diagram of the system configuration, Fig. 7 is an explanatory diagram of processing timing of the conventional example, Fig. 8 is a flowchart of the conventional example, and Fig. 9 1 is a diagram illustrating the influence of fluctuations in synchronization in a conventional example. 1 is a digital signal processing processor, 2 is a transmitting buffer, 3 is a receiving buffer, 4 and 5 are first . This is the second data area.

Claims (1)

[Claims] A digital signal processing processor (1), a transmission buffer (2), and a reception buffer (3) are provided, and the digital signal processing processor (1) performs encoding and decoding processing. In a code/decoding process control method that switches over at a fixed time, first and second data areas (4, 5) are provided, and each time one frame of encoded data is received and stored in the reception buffer (3), the data area is allocated. The digital signal processing processor (1) starts the encoding process at the rising edge of the frame signal, adds the encoded data to the transmission buffer (2), and starts the encoding process at the falling edge of the frame signal. When the encoded data is read from the first data area (4) and the decoding process is started, and the interrupt flag is set before the start of the encoding process, the encoded data is read out from the first data area (4). Transfer encoded data from the reception buffer (3) and reset the interrupt flag, and when the interrupt flag is set before the start of the decoding process, the first data area (4) is unused. state, the reception buffer (3) is stored in the first data area (4).
) to reset the interrupt flag, and if the first data area (4) is in use, the receive buffer (3) is transferred to the second data area (5).
), the interrupt flag is reset, and upon completion of the decoding process, the encoded data is transferred from the second data area (5) to the first data area (4). Characteristic encoding/decoding processing control method.