JPH01282795A - memory circuit - Google Patents

Abstract

PURPOSE:To arrange a memory element in a matrix and to attain a data access in a raw direction and a column direction without executing address conversion or data conversion, etc., by providing a means to access plural memories in the raw direction with continuous addresses and a means to access the memories in the column direction. CONSTITUTION:Plural memories RAM 00-RAM 77, which are arranged in the matrix, respectively input the addresses in the raw direction and column direction and in correspondence to the addresses, data in the raw direction or the column direction are inputted and outputted. A raw access means 11 accesses the plural memories RAM 00-RAM 77 in the raw direction by the continuous addresses and a column access means 15 accesses the memories in the column direction by the continuous addresses. Thus, the memory elements RAM 00-RAM 77 are arranged in the matrix and the access can be executed in the raw direction and column direction by the continuous addresses without executing the special address conversion or data conversion, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit that can be accessed in a matrix format by changing the write direction and the read direction.

[Prior Art] In recent years, with the increase in the capacity of semiconductor memories, it has become possible to store digital image data for multiple sides inputted from a scanner or the like as is, and to perform image data conversion such as data compression and density conversion. Many processing devices are now available on the market.

[Problem to be Solved by the Invention] However, the image memory of such devices usually consists of linear addresses that correspond to the data bus of the CPU that accesses the memory, and each bit of one word of such memory The image data stored in , for example, is composed of continuous pixel rows in the main scanning direction of the document. Therefore, when reading the image data stored in this image memory in the sub-scanning direction for data conversion such as rotation of the image data, it is necessary to read out the image data for multiple lines in the main-scanning direction. , and then create a pixel data string in the sub-scanning direction (vertical direction) based on the predetermined bit (pixel) data of the plurality of rows. Furthermore, when writing in the sub-scanning direction, it is necessary to similarly perform troublesome data conversion and address conversion.

In this way, in order to write or read image data specific to image data, it is necessary to access many addresses. On the other hand, when image data written in the sub-scanning direction is read out in the main-scanning direction,
There were problems such as an increase in the number of memory accesses and an increase in the time required to rearrange data.

The present invention has been made in view of the above conventional example, and provides a memory circuit in which memory elements are arranged in a matrix and data can be accessed in the row and column directions without special address conversion or data conversion. The purpose is to

[Means for Solving the Problems] In order to achieve the above object, the memory circuit of the present invention has the following configuration. That is, a plurality of memories arranged in an n×m matrix, each of which receives addresses in the row direction and column direction,
means for inputting and outputting data in a row or column direction corresponding to the address; row access means for accessing the plurality of memories in the row direction at consecutive addresses; and row access means for accessing the plurality of memories in the row direction at consecutive addresses. A column access means for accessing in the column direction is provided.

[Operation] In the above configuration, each of the plurality of memories arranged in an n×m matrix receives an address in the row direction and column direction, and inputs/outputs data in the row or column direction in accordance with the address. do. The row access means can access these multiple memories in the row direction using consecutive addresses, and the column access means can access these multiple memories in the column direction using consecutive addresses.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of the memory circuit (Figs. 1 to 4)] Fig. 1 is a circuit diagram showing the configuration of the memory circuit 101 of the embodiment, and Fig. 2 shows the structure of each memory circuit element arranged in the matrix of Fig. 1. FIG. 2 is a circuit diagram showing the configuration.

FIG. 3 is a diagram showing the connection between the memory circuit 101 and the control circuit 100 of this embodiment. Note that the following description will be made regarding the case where image data consisting of 4096 (main scanning) x 8192 (sub scanning) pixels shown in FIG. 4 is processed.

In FIG. 3, reference numeral 100 outputs address signals, data signals, etc. to the memory circuit 101 of the embodiment;
1, and is used as a work area for a CPU such as a microprocessor, a ROM that stores the CPU control program and various data shown in the flowcharts of Figures 5 and 6, and the CPU. It is equipped with RAM, etc. 102 is a 22-bit address bus (AO-A21) output from the control circuit 100 to the memory circuit 101, 103 is an 8-bit data bus (Do-D7) of the control circuit 10o, and 104 is an address bus (AO-A21) output from the control circuit 100 to the memory circuit 101. This is a read/write (R/W) signal output to the circuit 101, and is output at a low level when data is written to the memory circuit 101. 105 is the control circuit 10
0 to the memory circuit 101 (horizontal/vertical (H/
V) signal to move the memory circuit 101 in the row direction (main scanning direction)
When accessing, it is output at high level, and when accessing in the column direction (sub-scanning direction), it is output at low level.

FIG. 1 is a circuit diagram showing the configuration of a memory circuit 101 according to an embodiment, and parts common to those in FIG. 3 are indicated by the same symbols.

In the figure, 10 is a RAM with a capacity of 512k x 1 bit.
In this memory circuit 101, 64 circuits are arranged in an 8×8 matrix. In this matrix arrangement, the RAM circuits in the first row are RAM00-RAMO7,
The circuits on the second row are shown as RAMs 10 to 17, and the circuits up to the eighth row are shown as shown in the figure. 11 inputs A9 to All of the address bus 102, and inputs the H/V signal 105.
is at a high level (memory access in the main scanning direction), they are decoded and stored in the row direction buffer 12 (GO~
G7) is a decoder that outputs enable signals 17ENO to EN7.

Reference numeral 12 denotes an 8-bit buffer connected to the data bus 103, which is labeled with symbols from Go on the first row to 07 on the eighth row, corresponding to each row of the RAM circuit group arranged in the matrix. It shows. When the corresponding enable signal (ENO to EN7) is enabled (high level), each of these buffers outputs data on the data bus 103 to the corresponding RAM circuit row, or outputs data from the corresponding RAM circuit row. It is output to bus 103. 13 is R
Address data in the row direction (main scanning direction) of the AM circuit group,
14 is address data in the column direction (sub-scanning direction) of the RAM circuit group.

15 inputs and decodes Al0-Al2 of the address bus, and when the H/V signal 105 is low level (memory access in the sub-scanning direction), the buffer 18 in the column direction (Go'
~G7') enable signal ENO'
~EN7' This is a decoder that outputs the signal 16. 18 is an 8-bit buffer connected to the data bus 103;
Symbols from GO' in the first column to G7' in the eighth row are shown corresponding to the columns of the RAM circuit group arranged in the matrix. Each of these buffers outputs the data on the data bus 103 to the RAM circuit of the corresponding column when the corresponding enable signal (ENO' to EN7') is enabled (high level), or outputs the data from the RAM circuit of the corresponding column. data is output to the data bus 103.

FIG. 2 is a block diagram showing the circuit configuration of the RAM circuit 1o.

2o is a memory element having a capacity of 512k×1 bit, which inputs a 19-bit address signal 26 and inputs/outputs a 1-bit data signal 21. 25 is memory element 2
This enable signal 25 enables access to the memory element 20 when the signal 25 is at a high level.

21 is a selector that switches between address data 13 and 14 and outputs it as an address signal 26;
is at high level (during access in the main scanning direction), address data AO-A8 and A12 to A21 are input as the address signal 26, and access in the sub-scanning direction (H/V
When the signal is low level, address data 14 (A12
~A21 and AO~A9) are output as address signals 26.

22 and 23 are two-way 1-bit buffers, respectively.
When the R/W signal 104 is at high level (during reading), n
One bit data is output from A to nB and from mA to mB, and when the R/W signal 104 is at low level (during writing), it is output from nB to nA and from mB to mA.

24 is an O that enables the memory element 20 during access in the main scanning direction (when ENn is at a high level) or during access in the sub-scanning direction (when ENm' is at a high level).
This is an R circuit. Note that data is written to the memory element 20 when the enable signal 25 is at a high level and the R/W signal 104 is at a low level, and data is read from the memory element 20 when the R/W signal 104 is at a high level.

Here, the memory element 20 is shown as RAMnm, but n
represents the number of rows (0 to 7) in Figure 1, and m represents the number of columns in each row (0
-7) are shown. Therefore, for example, if the memory element 20 shown in FIG. 2 is RAM01 in FIG. 1, n=o,
When m=1, the bidirectional buffer 22 is enabled by ENO when accessed in the row direction (main scanning direction), and inputs and outputs the data bus D1. Further, when accessing in the sub-scanning direction, when ENI' is output, the bidirectional buffer 23 inputs and outputs Do of the data bus in response to a read or write signal. In this way, RAM n m is enabled when the n-th row and m-column are accessed, and Dm of the data bus 103 is enabled when accessing in the main scanning direction, and Dm of the data bus 103 is enabled when accessing in the sub-scanning direction.
Input/output Dn data of 3.

FIG. 4 is a diagram showing image data 41 stored in the memory circuit 101 of FIG. 1, and this image data is 4096×81
It is composed of 92 pixels.

In this embodiment, a portion of pixel data 40 composed of 8×8 pixels (each pixel is binary data) is stored in 64 RAM00-RAM77 in FIG.
For example, the address “
Stored as 0".

Furthermore, these 64 pixel matrix 40 are shifted in the main scanning direction (horizontal direction) and the sub-scanning direction (vertical direction), respectively, and these 64 pixels of 8×8 are each shifted in the same way to RA. M00-Stored in RAM77.

That is, the H/V signal is set to high level, and the address bus 10
If all 2 are set to "0" and written, only Go of the buffer 12 is enabled, so the pixels on the first line (00-0
7) is stored at address "0" of RAM00-RAM○7. Thereafter, in the same manner, the pixel data of the first line is sequentially stored in the addresses "0" to "511" of each memory element of RAM00 to RAM07. next,
When the address of the address bus 102 reaches address "512", A9 becomes "1", so only G1 of the buffer 12 is enabled. As a result, the pixel data of the second line in the main scanning direction (pixel 10 to pixel 1.4095) is stored in the RAM.
It is stored at addresses "0" to "511" of l0-17.

Therefore, for example, when image data 41 is stored sequentially in the main scanning direction, pixel (00) is stored at address "0" of memory element 20 of RAM0O, and pixel (00) is stored at address "0" of memory element 20 of RAM0O.
1” has an image (08), and address “2” has a pixel (1
6) and so on, and the address “51
When pixel (0,4088) is stored at address 1”, 8×
This means that 4096 pixels (pixel data for 8 main scanning lines) are stored in the memory circuit 101. Furthermore, pixel data from the 9th line to the 16th line is stored in RAM0O-07 (7
) When pixel data of 512 bits is stored in each memory element of 64 RAM circuits from address "512" to address "1023", 8192 bits as shown in FIG.
(Line) All of the image data 41 of 4096 pixels are stored in the memory circuit 101.

Next, for example, if you want to read out 8 pixels in the vertical pixel column (pixels 00, 10, 20..., 70) of the pixel matrix 40 in FIG. 4, set the H/V signal 1o5 to low level and The bus 102 is all set to "0", the R/W signal is set to high level, and the memory circuit 101 is read. As a result, only ENO' becomes high level and buffer 1
One byte of data is read from GO' of No.8. At this time, pixel OO is from RAM0O, pixel 01 is from RAM0
1, pixel data for one column is output one after another. For example, when it is desired to read the second pixel column (pixels O1 to O71), only the AIO of the address bus is set to "1" and read in the same manner. Furthermore, pixel row 42 (pixel 08
~ pixel 78), address bus 102
It is sufficient to set only A13 to "1" and read in the sub-scanning direction (H/V=low level).

As is clear from FIG. 2, the address input in the main scanning direction is AO-A8. The address input in the sub-scanning direction is AI3-A21 at the bottom and AO-A9 above it, but this accesses the pixel column from pixel OO to pixel 70 in the sub-scanning direction. Next, the lower pixel row 43 (pixel 80 to pixel 150) is accessed, and so on, 8 pixels are sequentially accessed in the sub-scanning direction (downward in FIG. 4).
When accessing one pixel at a time, the addresses output to the address bus 102 are designed such that continuous linear addresses starting from "0" need only be output.

[Explanation of write and read processing of control unit (Figs. 5 and 6)
Figure) Fig. 5 shows the memory circuit 10 by the control circuit 100 of the embodiment.
1 is a flowchart showing the process of writing the image data 41 shown in FIG. 4 in the main scanning direction, and FIG. It is a flowchart which shows the process of reading in a scanning direction.

When writing image data, address bus 1 is set in step S1.
"0" is output to 02, and 8 in the main scanning direction is output in step S2.
Enter pixel data. It is assumed that this pixel data is input sequentially from the upper left of the image data 41. In step S3, the horizontal/vertical signal (H/V) 105 is set to high level, and in step S4, the R/W signal is set to low level to write 8 pixel data. When the 8 pixel data in the main scanning direction is written in this way, in step S5 the address bus 1 is
02 is incremented by 1, and in step S6 it is determined whether the address to be output to the address bus is 4 megabytes or more. If it is not 4M or more, the process returns to step S2 and proceeds to the next image data storage process. Thus address bus 102
When the value of is carried up from A21 to A22, all of the image data 41 in FIG. 4 is stored in the memory circuit 101.

Next, the read process will be described. In step S10, an address of "0" is output to the address bus 102, and in step Sll, the H/V signal 105 is set to low level. When reading is performed by setting the R/W signal to a high level in step S12, an 8-bit pixel column in the vertical direction indicated by pixels (00 to 70) in FIG. 4 is read out. In step S13, the value of address bus 102 is incremented by 1, and in step S14, it is determined whether the address of address bus 102 is 4 Mbytes or more.

If it is less than 4M, the process returns to step S12 and the image data is read out. As a result, the next pixel column 43 is read out, and in the same manner, eight pixels are sequentially read out in the vertical direction.
When the leftmost column of pixels (8192 pixels) is read out,
Image data can be read out successively in the sub-scanning direction, such as from pixels in the second row.

Note that the circuit configuration of the memory circuit 101 of this embodiment is the fourth one.
This is done for the purpose of processing the image data in the figure, and may be changed as appropriate depending on the number of pixels of the image data to be processed.

Further, in this embodiment, the address bus, data bus, etc. that are accessed in the main scanning direction, and the address bus and data bus that are accessed in the sub-scanning direction are shown in common, but the present invention is not limited to this, and each RAM circuit It is also possible to configure the memory element with a dual-port RAM so that accesses in the main scanning direction and addresses in the sub-scanning direction can be accessed independently by different CPUs. Further, in this embodiment, writing is performed in the main scanning direction and reading is performed in the sub-scanning direction, but it is of course possible to write in the sub-scanning direction and read out in the main scanning direction.

FIG. 7 is a diagram showing an example of address connection to the multiplexer 21 of another embodiment, and FIG. 8 is a diagram showing an example of address bus connection of the decoder 15. By connecting in this way, the above-mentioned FIG. The pixel data written in the memory circuit 101 as explained in 1. Access to pixel columns can be performed using consecutive addresses.

Furthermore, in this embodiment, data access in the main scanning (row) direction and data access in the sub-scanning (column) direction are performed using the same number of bits, but for example, data access in the row direction is performed using 16 bits, and data access in the column The number of bits accessed in the row direction and column direction may be changed, such as accessing with 8 bits in the direction. Note that in this case, the configuration is a 16×8 matrix.

Furthermore, in this embodiment, each pixel data consists of 2 bits of 1 bit.
Although the case of value data is shown, the present invention is not limited to this. For example, if the capacity of the memory element 20 in FIG. 2 is 512k×2
If the data bus of the control unit 100 is made 16 bits by configuring the buffers 22 and 23 as 2-bit buffers, the multivalued image data shown in FIG. 1, in which each pixel in FIG. can be stored in the circuit.

As explained above, according to this embodiment, it is possible to provide a memory circuit that can be accessed with continuous addresses in both the row and column directions, and, like image data, can be accessed in both the main scanning direction and the sub-scanning direction. This is particularly effective when processing data that is accessed by changing the direction of access.

[Effects of the Invention] As explained above, according to the present invention, memory elements are arranged in a matrix and can be accessed with consecutive addresses in the row and column directions without special address conversion or data conversion. There is.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the configuration of the memory circuit of the embodiment; FIG. 2 is a circuit diagram showing the configuration of the RAM; FIG. 3 is a block diagram showing the connection between the control circuit and the memory circuit of the embodiment; 4 is a diagram showing an example of image data of the embodiment, FIG. 5 is a flowchart showing a process of writing the image data of FIG. 4 into the memory circuit in the main scanning direction by the control circuit of the embodiment, and FIG. A flowchart showing the process of reading out image data written to the memory circuit in the sub-scanning direction by the write process shown in the flowchart in the figure. FIG. In the figure, 10...RAM circuit, 11.15...decoder, 12.18...buffer, 13.14...address data, 16.17...enable signal, 20...
...Memory element, 21...Multiplexer, 22.2
3... Decoder, 24... OR circuit, 25... Enable signal, 100... Control circuit, 101... Memory circuit, 102... Address bus, 103... Data bus, 104...・Read/write signal (R/W)
, 105 . . . horizontal/vertical signals (H/V). Patent applicant: Canon Co., Ltd. Figure 3 Figure 5 Figure 6 Figure 51 Figure 7 Figure 80

Claims (1)

[Claims] A plurality of memories arranged in an n×m matrix, each of which receives addresses in the row direction and column direction,
means for inputting and outputting data in a row or column direction corresponding to the address; row access means for accessing the plurality of memories in the row direction at consecutive addresses; and row access means for accessing the plurality of memories in the row direction at consecutive addresses. A memory circuit comprising column access means for accessing in the column direction.