JPH01284899A - Voice synthesizing device - Google Patents

Abstract

PURPOSE:To improve the operability and the processing speed by providing a command circuit for commanding a read-out start of one group of voice data, continuous read-out of plural groups of voice data and repeated read-out of one group of voice data. CONSTITUTION:A word/phrase selecting signal is inputted to a counter 32 of a command circuit 30 through a latch circuit 12, and transferred as an address designating signal to a sentence constitution and storage device 38. The counter 32 holds this signal until a continuous read-out instructing signal of the next word is sent from a control circuit 36. In response to this signal, the device 38 reads out the corresponding start address, end address, repetition frequency code and end code, and outputs them to an address counter 16, a comparator 40, the control circuit 36 and an end code detector 42, respectively. Subsequently, when the counter 16 receives a head address, while counting it up, this signal is sent as a command signal of a read-out start to a data storage device 18, and supplied to the comparator 40 provided on a sentence constituting circuit 34 of the command circuit 30, as well. From the device 18, voice data corresponding to the address is read out successively.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a speech synthesis device having a sentence generation function.

(Prior Art) As a conventional typical speech synthesis device, for example, the device disclosed in Japanese Patent Publication No. 59-9078 filed by the present applicant, or
There are devices having a configuration as shown in the block diagram in FIG. 2, etc. The typical conventional device shown in FIG. 2 includes an input terminal 10 for receiving a word selection signal externally specified by an operator or an external control device (not shown), and a terminal 10 for receiving a word selection signal externally specified by an operator or an external control device (not shown), and a terminal 10 for receiving a word selection signal externally specified by an operator or an external control device (not shown). A latch circuit 12 that holds the word, an address selection storage device 1f14, an address counter 16 that sequentially outputs address signals corresponding to the word selection signal, and an address counter 16 that sequentially outputs address signals corresponding to the word selection signal. , a data storage device 118 that outputs audio data in response to these address signals, a speech synthesis circuit 20 that decodes the audio data, and converts the decoded signal into an analog signal and outputs it. D/A output as a voice synthesis signal from terminal 24
A converter 22 is provided.

The address selection storage device M14 mentioned above is the data storage device 1.
This is a memory device in which starting addresses corresponding to multiple words of audio data stored in 8 are stored in advance, and each starting address is assigned to an address of this address selection storage device 14.

In the conventional device having such a configuration, when a word selection signal for selecting one word from among a plurality of words prestored in the data storage device is input as an address code to the input terminal 10 by an external operation, this address is After the code is temporarily stored in the latch circuit 12, it is input to the address selection memory device=18.

The address selection storage device 14 outputs the first address of the word to be selected, which corresponds to the address code, to the data storage device 18 via the address counter 16. On the other hand, when this first address is supplied to the address counter 16, this The counter 16 starts counting up at an appropriate time interval set in advance, and sequentially outputs other addresses necessary for this word following the first address, and outputs the encoded data of a certain word corresponding to this first address. All audio data is read out. These sequentially read voice data are supplied to the voice synthesis circuit 20, which converts the decoded voice synthesis signal into D.
The audio signal is configured to be outputted from an output terminal 24 as an analog audio output via a /A converter 22.

(Problem to be Solved by the Invention) However, in the conventional speech synthesis device having such a configuration, the data storage device 1118 stores speech data of a plurality of words with addresses assigned to each one, so that external When a word selection signal is input from , only one word starting from the corresponding start address is read out.

Therefore, in order to read out a plurality of required words in succession and synthesize a sentence into speech, or to read out one word repeatedly, it is necessary to use the operator's operation or by connecting the external control device l to the input terminal 10. It is necessary to input a different or the same word/phrase selection signal from the outside each time, and as a result, the conventional device has problems of poor operability and slow processing speed.

The present invention has been made in view of these problems, and therefore, an object of the present invention is to provide a speech synthesis device that is easy to operate and has a high processing speed.

(Means for Solving the Problems) In order to achieve this object, the present invention provides an address counter that sequentially outputs address signals corresponding to word selection signals from the outside, and a speech synthesis signal of multiple words. In a speech synthesis device comprising a data storage device in which a plurality of groups of speech data to be decoded are respectively stored and outputting speech data in response to these address signals, a speech synthesis device is provided at a stage before the address counter that outputs speech data in response to a word selection signal. hand,
A command circuit is provided which outputs a command signal for instructing the data storage device to start reading a group of audio data, continuously reading a plurality of groups of audio data, and repeatedly reading a group of audio data via an address counter. It is characterized by

In carrying out the present invention, the command circuit preferably includes a text storing a start address and an end address of a plurality of groups of audio data, continuous readout command data of a plurality of groups of audio data, and repeated readout command data of a group of audio data. a sentence composition circuit having a composition storage device I; a counter for specifying the start address of a word corresponding to a word selection signal; and a counter for sequentially specifying the start address of a word following this word for each instruction signal; and the above-mentioned start address. , an end address, continuous read command data, and repeated read command data from the above-mentioned sentence structure storage device, and a control circuit for outputting an instruction signal from the command circuit.

(Operation) As described above, according to the speech synthesis device of the present invention, the order of synthesizing each sentence to generate a series of continuous or repeated sentences through speech synthesis is predetermined, and the order of synthesizing each sentence is determined in advance, Since the structure is such that the audio data of each sentence can be read out in sequence, there is no need for the operator to give repeated or continuous reading commands, or to provide an external control bag for that purpose, as in the past. Easy to operate and fast processing speed.

(Embodiments) Hereinafter, embodiments of the speech synthesis device of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the speech synthesis device of the present invention. In this figure, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

4. In the data storage device 18 of the speech synthesis circuit of the present invention, a plurality of groups of speech data corresponding to individual words are stored, as in the conventional case, and a start address and a corresponding address are assigned to each group of speech data. The following address is assigned as a read address.

Figure 3 shows the read address (address) of this data storage device.
FIG. 3 is a diagram showing an example of data contents.

In addition, in the following explanation 1, S indicates the start address (first address), and E indicates the end address (end or final address). In this example, the word "Kora" is used at addresses 81 to E1, and similarly, , addresses 82 to E2 store the word "wake up", addresses 83 to E3 store voice data such as "already", and so on.

In the speech synthesis circuit of the present invention, the address counter 16 is provided at a stage upstream of the address counter 16 for instructing the data storage device 18 to start reading out a group of audio data, to continuously read out a plurality of groups of audio data, and to repeatedly read out a group of audio data. A command circuit 30 is provided.

Briefly, the above-mentioned command circuit 30 is preferably composed of a counter 32, a sentence composition circuit 34, and a control circuit 36. These compositions will be explained below.

In this embodiment, the counter 32 is connected between the latch circuit 12 and the sentence structure memory table [34]. When the latch circuit 12 is not used, this counter 32 is directly connected to the input terminal 1.
It can also be connected to 0. When this counter 32 receives the word selection signal from the input terminal 10, it reads out the read address in response to this signal, in this case, the start address of the first word to be read out from the data storage device 118 and synthesized into speech. An address signal for designation is output to the sentence composition circuit 34.

This sentence composition circuit 34 stores basic data, which will be described later, for giving instructions as to the order in which the audio data stored in the data storage device M18 should be read out in order to compose a sentence. This circuit outputs these basic data accordingly.

Although this circuit 34 is not limited to the configuration of this embodiment, it mainly includes a song sentence structure storage device 38 provided between the counter 32 and the address counter 16. In addition, as required, sentence structure memory table W
! 38 and the address counter 16 and outputs the result to the control circuit 36, and an end code detection circuit 42 provided between the sentence structure storage device 38 and the control circuit 36 may be provided. .

The sentence structure storage device 38 stores basic data for reading voice data, that is, the start address and end address of a plurality of groups of voice data, each corresponding to a plurality of words to be synthesized, and a plurality of groups. Continuous read command data for audio data and repeated read command data for a group of audio data are stored, respectively. In this case, the order of synthesizing six words to generate a sentence consisting of a series of consecutive words or repeated words through speech synthesis is determined in advance, and the audio data of each word is created according to this determined order of word combinations. Each readout address, such as the first address and subsequent addresses, is sequentially stored in the sentence structure storage device 38 so that each voice data can be read out. Each time, a repetition code indicating the number of repetitions and an end code indicating whether to continue to the next audio data are added to the read address as command data and stored.

FIG. 4 shows an example of the data structure of the sentence structure storage device=38, taking address n as an example. That is, each n(n
is an integer), the start (first) address and end (
A read address called an end (or final) address, a repeat count code, and an end code are stored.

FIG. 5 is a diagram showing, as an example, the addresses and their data contents when the addresses n in FIG. 4 are addresses 1 to 12. In this embodiment, addresses 1 are sequentially filled with start addresses S4, . End address E4. Repeat count code “O”
, an end code "]" is stored, which corresponds to the sentence "Hey" as shown in Figure 3. Similarly, address 2 has an S
2. E2. ro, , +, ro'', and S4.
E4. rO+,M'', and S2. E2. rl”
, rl'' at address 5, and S5. E5. roJ, rl" and S2.roJ, rl" at address 6. E2. "r2", "ro", . . . are stored sequentially. Note that the repetition number codes "0", "1", and "2" are the same word and therefore mean that the audio data is not repeated, is repeated only once, and is repeated twice. Also, the end code "0" means only this word and no continuation words, and "
1" means that there is a continuation word to form a sentence.

The control circuit 36 is basically a circuit for causing the entire speech synthesis device to perform a predetermined operation at a predetermined timing, and outputs a control signal to each component, and in the case of this embodiment, Roughly speaking, the above-mentioned start address, end address, end code that is continuous read command data, and repeat code that is repeat read command data are read from the above-mentioned sentence structure storage device [38, and the start address and end address are read out from the sentence structure storage device [38]. The address and repeated read command data are output as address signals to the address counter 16, and the continuous read command data are output as an instruction signal to the counter 32.

Roughly speaking, the comparator 40 is connected to the output sides of the sentence structure storage device 38 and the address counter 16, and compares the end address, which is the basic data from the sentence structure storage device 38, and the address, which is the output from the address counter 16. Compare, detect -ht of both outputs, and send the detection signal to the control circuit 36.
This is a circuit that gives

Furthermore, the end code branching circuit 42 is connected to the sentence structure memory device M3.
receives the end code, which is the basic data stored in 8, and determines whether it is "0", which means the end of the sentence,
If it is "○", this circuit outputs a signal to that effect to the control circuit 36.

operating layer Next, an example of the operation of this speech synthesis device will be explained.

First, it is assumed that a word selection signal "3" specifying address 3 in FIG. 5, for example, is input to the input terminal 10 by an external operation by an operator. This signal "3" is taken into the counter 32 of the command circuit 30 through the latch circuit 12, and the counter 32 transfers the signal "3" to the sentence structure storage device M38 as an address designation signal.

The counter 32 holds this addressing signal "3" until an instruction signal is sent from the control circuit 36 instructing continuous reading of the next word.

The sentence construction circuit M38 receives this address designation signal [3].
In response to this signal "3", address 3 in FIG.
basic data, that is, the start (head) address S4,
The end (end or final) address E4, repetition number code "O" and end code "1" are read out, and these basic data S4. E4. rQJ and "1" are output to the address counter 16, comparator 40, control circuit 36 and end code detector 42, respectively.

Next, when the address counter 16 receives the first address S4, it outputs this address signal S4, and then sequentially outputs address signals (S4+1) from this address signal S4 while counting up.

(S4+2), . . . are output.

These address signals are sent to the data storage device 18 as a command signal to start reading, and are also supplied to a comparator 40 provided in the sentence construction circuit 34 of the command circuit 30. Therefore, from the data storage table=18, these address signals S4. The audio data corresponding to the addresses specified by S4+1.34+2° . . . are sequentially read out.

The comparison circuit 40 also receives address signals S4. S4+1°S4+2.
When an address signal that matches the end address E4 sent from the sentence structure storage device 38 is first sent, a -defeat signal is output to the control circuit 36, and control is controlled by receiving this match signal. A stop signal is sent from the circuit 36 to the address counter 16 to temporarily stop counting up. This stop causes data storage device 18 to output all address signals S4. S4+1. S4+2. ..., E4
The encoded voice data from 84 to E4 is output to the next stage for voice synthesis. Therefore, speech synthesis,
As can be understood from FIG. 3, an audio signal of the word "nee" corresponding to addresses 34 to E4 is generated from the analog-converted output terminal 24.

After that, the control circuit 36 detects that the repetition number code from the sentence structure storage device 13 is "0", and then, since the end code is "1", the end code detection circuit 42 detects this word. It is detected that the audio data of the next word is successively read. Therefore, the control circuit 36
sends an instruction signal to the counter 32 to instruct the counter 32 to count up, and outputs an address designation signal specifying the start address for continuous reading of the next word at address 4.

Upon receiving this address signal, the sentence structure storage device 38 stores the basic data S2°E4, 1.18 in the same manner as described above.
The signals are sent to the address counter 16, comparator 40, control circuit 36, and end code detection circuit 42, respectively. Therefore, the address counter 16 sends the addresses 82 to E2 to the data storage device 118, from which the corresponding audio data is read out, synthesized into audio, then converted into an analog signal, and output from the output terminal 24, as can be understood from FIG. , a voice saying "Wake up" will be heard.

When a group of voice data corresponding to this address 4 is voice synthesized and generated once as one word, the control circuit 36 determines that the repetition number code of this address 4 is "1".
, and repeatedly sends read command data to the address counter 16 to reset the contents of the address counter 16 to the start address S2 of address 4. Then, the address counter 16 outputs the address signals of addresses 82 to E2 again while counting up, reads out the voice data corresponding to the word "wake" from the data storage device 18, and similarly outputs the voice data corresponding to the word "wake" from the output terminal 24. Outputs the voice "Te". In the case of this embodiment as well, the end code is "1" and no information is received from the end code detection circuit 42 indicating that reading has ended, so an instruction signal is sent to read out the next word continuously. is sent to the counter 32, and the value of the counter is set to 5.

Subsequently, this address designation signal "5" is sent to the sentence structure storage device t38, and in a similar manner, the start address S5.5 of address 5 in FIG. End address E5. The repeat count code “0” and the end code “]” are read out.
Voice data corresponding to this is successively outputted from the data storage device M18, and a voice synthesized signal "you" is output from the output terminal 24.
Occurs twice. Then, the counter 32 is counted up to "6".

Similarly, at address 6, the start address is 82, the end address is E2, and the repeat count code is "2", so
The output terminal 24 generates "wake up" three times. Also, since the end code is rQJ, after that,
The control circuit 36 ends not only the continuous reading of the words in the - series but also the repeated reading of these words, and puts the entire apparatus in a standby state for the input of the next word selection signal.

Similarly, when address 1 in FIG. 5 is designated by the word selection signal, the output terminal 24 is
The voice of the sentence ``Hey, wake up'' is generated. Similarly, when the address 7 is specified, the sentence ``Hey, you, wake up, wake up, wake up.'' is generated.

In this way, the speech synthesis device of the present invention can continuously generate multiple words from the words stored in the data storage device with a single word selection input, and can also generate the same word over and over again. It can also be generated. Further, since the command circuit is configured to store command data for continuous reading, repeated reading, etc. in advance and use the command data, it is also possible to reduce the storage capacity of audio information in the data storage device.

The present invention is not limited to the above-described embodiment; for example, unlike the configuration shown in FIG.
If the end code detection circuit 42 is not provided, an addressing signal is sent from the counter 32 in response to the word selection signal to the sentence structure storage device! It is also possible to read all of the basic data described above by the control circuit 36 at the same time that the data is input to the counter 38, and to have the control circuit 36 output the respective signals to the counter 32 and the address counter 16.

(Effects of the Invention) As is clear from the above description, the speech synthesis device of the present invention can be used to learn how to read speech data and perform speech synthesis, such as reading out speech data, repeated reading, and continuous reading. Since it is equipped with a command circuit that determines, the order of synthesizing six words to generate a series of continuous or repeated words through speech synthesis is determined in advance, and the sound of each word is synthesized in the order according to the combination of sentences. Since the structure allows the data to be read out, the operator can issue repeated or continuous read commands as in the past.
Alternatively, there is no need to provide an external control device M for this purpose, and therefore the operability is good and the processing speed is fast.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the speech synthesis device of the present invention, Fig. 2 is a block diagram showing a typical conventional speech synthesis device, and Fig. 3 explains an example of data in a data storage device. FIGS. 4 and 5 are diagrams for explaining an example of the data structure of the sentence structure storage device. 10...Input terminal, 12...Latch circuit +
6--Address counter, 18--Data storage device 20--Speech synthesis circuit, 22--D/A converter 24--Output terminal, 30--Command circuit 32---Counter, 34 ... Sentence structure circuit 36 ... Control circuit, 3rd day ... Sentence structure storage device 40 ... Comparator 42 ... End code detection circuit. Patent applicant Oki Electric Industry Co., Ltd. Example of data content of data storage device Figure 3 Figure 4

Claims (2)

[Claims] (1) An address counter that sequentially outputs address signals corresponding to word selection signals from the outside, and multiple groups of voice data each decoded into a voice synthesis signal of multiple words are stored, and a counter that responds to these address signals. In the speech synthesis device, the speech synthesis device includes a data storage device that outputs speech data by using
A command circuit is provided which outputs a command signal for instructing the data storage device to start reading a group of audio data, continuously reading a plurality of groups of audio data, and repeatedly reading a group of audio data via an address counter. A speech synthesizer featuring: (2) The command circuit includes the start address and end address of multiple groups of audio data,
a sentence construction circuit having a sentence construction storage device storing continuous readout command data for a plurality of groups of audio data and repeated readout command data for a group of audio data; a counter that sequentially specifies the start address of the word following the word for each signal; and a counter that reads the start address, end address, continuous read command data, and repeated read command data from the sentence structure storage device and outputs the command signal from the command circuit. The speech synthesis device according to claim 1, further comprising a control circuit for outputting the output.