JPH0128507B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bipolar semiconductor integrated circuit device.

Reducing the element area in the manufacture of semiconductor integrated circuit devices not only improves the integration density, but also
Enables high-speed operation by reducing parasitic capacitance.

FIG. 1 shows an example of a method of manufacturing a conventional bipolar semiconductor integrated circuit device, which is currently the most practical method for improving the integration density.

First, as shown in FIG. 1A, an N ⁺ buried layer 2 is formed on a P-type silicon substrate 1, and then an N-type epitaxial layer 3 is formed on the silicon substrate 1.

Next, a thermally grown silicon oxide film 4 and a silicon nitride film 5 are deposited on selected surfaces of the epitaxial layer 3.
A mask layer 6 for selective oxidation is formed. Then, the epitaxial layer 3 without the silicon nitride film 5 on its surface is etched to form a groove 7. Here, the depth of the groove 7 is set so that even if an oxide film with increased volume is formed in the groove portion in the next oxidation step, the substrate surface remains substantially flat.

When the substrate shown in FIG. 1A is oxidized, an isolation oxide film 8 is formed as shown in FIG. 1B, and a mask layer 6 is formed.
A collector region 3' made of the epitaxial layer 3 and a collector electrode extraction region 3'' are formed below.

Next, as shown in FIG. 1C, after removing the mask layer 6, an N ⁺ region (deep collector region) for reducing collector resistance is formed in the collector electrode extraction region 3''.
A P ⁺ region (side base region) 10 for reducing base resistance is further formed in the collector region 3'.

Next, as shown in FIG. 1D, a P-type main base region 11 is formed in the collector region 3'.

Next, as shown in FIG. 1E, openings 12 and 13 for collector and emitter contacts are formed by a well-known etching method, and then an N ⁺ emitter region 14 is formed in the main base region 11.

Then, as shown in FIG. 1F, after forming a contact hole in the base, electrodes 15, 16, and 17 made of wiring metal are formed.

In such a bipolar semiconductor integrated circuit device, the base regions 10 and 11 and the emitter region 14 are reduced in size by creating an opening for making ohmic contact between the side base region 10 and the electrode 15, and by making an ohmic contact between the emitter region 14 and the electrode 16. Silicon oxide film 18 existing between the openings to be contacted
limited by the dimensions of This silicon oxide film 1
8 is determined by the distance b between the electrodes 15 and 16 shown in FIG.
It is determined by the sum of the dimension a extending by the mask alignment error margin for electrode pattern formation, that is, 2a+b.

However, in the conventional method shown in FIG. 1, the extraction electrodes 15 and 16 are formed directly above the side base region 10 and emitter region 14;
It is difficult to reduce the dimensions of the base regions 10, 11 and the emitter region 14, which limits the reduction in the area of the base regions 10, 11 and the emitter region 14.

This invention has been made in view of the above points, and provides a method for manufacturing a semiconductor integrated circuit device that can significantly reduce the base and emitter regions, as well as the entire device, and enables high-speed operation at the same time as high integration. The purpose is to

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram showing an embodiment of the present invention.
In this embodiment, the same steps as the conventional method are used up to the formation of the isolation oxide film and the removal of the mask layer therefor. Therefore, a description of the step of forming the isolation oxide film and the step of removing the mask layer therefor will be omitted here, and the state after the mask layer removing step is shown in FIG. 3A. In FIG. 3A, 21 is a P-type silicon substrate, 22 is an N ⁺ buried layer, 23 ₁ is a collector region (first region) made of an N-type epitaxial layer, and 23 ₂ is a collector electrode made of the same epitaxial layer. The extraction region 24 is an isolation oxide film.

After forming the isolation oxide film 24 and removing the mask layer therefor, next, a first polycrystalline silicon layer 26 is formed on the entire surface of the silicon substrate 21.
2000 to 6000Å thick, and then the first
A mask for selective oxidation is applied to predetermined portions of the first polycrystalline silicon layer 26 on the surface of the first polycrystalline silicon layer 26, that is, on the side base formation area, the base extension part, and the resistor formation area (not shown). Layers 27 ₁ and 27 ₂ are formed. The mask layers 27 ₁ and 27 ₂ are composed of a two-layer film having a thin silicon oxide film on the bottom and a silicon nitride film on the top. (See FIG. 3B) Next, selective oxidation of the first polycrystalline silicon layer 26 is performed using mask layers 27 ₁ and 27 ₂ . When this selective oxidation is performed, the first layer immediately below the mask layers 27 ₁ and 27 ₂
The first polycrystalline silicon layer 26 still remains as polycrystalline silicon layers 26 ₁ and 26 ₂ , but the first polycrystalline silicon layer 26 having no mask layer on its surface becomes a thermally grown silicon oxide film 28 . (See FIG. 3C) Subsequently, after removing the mask layers 27 ₁ and 27 ₂ ,
Approximately 10 ¹⁵ to 10 ¹⁶ cm ^-2 of P is added to the polycrystalline silicon layers 26 ₁ and 26 ₂ by means such as ion implantation.
A type impurity such as boron is introduced. Thereafter, heat treatment is performed to form P ⁺ type side base regions (second regions) 29 ₁ and 29 ₂ in the collector region 23 ₁ directly under the polycrystalline silicon layers 26 ₁ and 26 ₂ . (See FIG. 3D) Next, after removing the entire silicon oxide film 28,
Oxidation treatment is performed at a low temperature of approximately 700℃ or higher. As a result, the polycrystalline silicon layer 2 containing high concentration of impurities
The surfaces of 6 ₁ and 26 ₂ are covered with a thick silicon oxide film 30 ₁ ,
On the other _hand , thin silicon oxide films 31 ₁ and 31 ₂ are grown on the surfaces of the collector region 23 ₁ and the collector electrode extraction region 23 ₂ . (See Figure 3E) After that, N is applied to the collector electrode extraction area ₂₃₂ .
The collector electrode extraction region ₂₃₂ is filled with N ⁺ by selectively introducing a type impurity, for example, phosphorus, by approximately 10 ¹⁶ cm ^-2 by means such as ion implantation, and performing heat treatment in a non-oxidizing atmosphere. N ⁺ region reaching layer 22, i.e. deep collector region 25
shall be. Subsequently, a P-type impurity, such as boron, is ion-implanted into the collector region 23 through the thin silicon oxide film ₃₁ by means such as ion implantation of approximately 10 ¹⁴ cm ^-2 .
₁ and heat-treated again in a non-oxidizing atmosphere, the P type main base region (third region) 32 is formed in the collector region 23 ₁ and the P ⁺ type side base regions 29 ₁ , 29 _2. Extend and form. At this time, boron is also diffused into the deep collector region 25 at the same time.
5 has already been diffused with a high concentration of N-type impurity, so no P-type region is formed. (See Figure 3F.) Next, the thin silicon oxide film 31 is immersed in a silicon oxide film etching solution.
₁ and 31 ₂ are removed to expose the surfaces of the P-type main base region 32 and the like, while the thick silicon oxide films 30 ₁ and 30 ₂ are left in a slightly reduced thickness state. Thereafter, a second polycrystalline silicon layer 33 is grown on the entire surface of the silicon substrate 21, that is, on the surfaces of the silicon oxide films 30 ₁ and 30 ₂ , the main base region 32, the deep collector region 25, the isolation oxide film 24, and the like. (See Figure 3G) After that, the second
An N-type impurity such as arsenic is introduced into the polycrystalline silicon layer 33 of about 10 ¹⁶ cm ^-2 . Next, the second
By selectively removing the polycrystalline silicon layer 33 , the second polycrystalline silicon layer 33 is left only in necessary portions such as the surfaces of the main base region 32 and the deep collector region 25 . In FIG. 3H, the second polycrystalline silicon layer 33 left on the surface of the main base region 32 is shown as a polycrystalline silicon layer ₃₃₁ , and the second polycrystalline silicon layer 33 left on the surface of the deep collector region 25 is shown as a polycrystalline silicon layer 331. The silicon layer 33 is shown as a polycrystalline silicon layer 33 ₂ . After that, an insulating film 34 such as a silicon oxide film is grown on the entire surface of the silicon substrate 21 and heat-treated, so that N from the polycrystalline silicon layer 33 ₁ is added to the main base region 32 .
The type impurity is diffused and the emitter region (fourth region)
35 is formed in main base region 32 .
(See FIG. 3H.) Thereafter, contact holes are opened by conventional means (not shown) and metal wiring is formed, thereby completing the bipolar semiconductor integrated circuit device.

FIG. 4 is an example of a plan view of the main part of the semiconductor integrated circuit device completed in this way, and shows a polycrystalline silicon layer 2 for forming a base contact.
6 ₁ and 26 ₂ are connected to each other and drawn out to the outside of the active element region. In the example of FIG. 4, the polycrystalline silicon layers 26 ₁ and 26 ₂ are connected in a U-shape, but they may be connected in a square-shape. Furthermore, it goes without saying that the polycrystalline silicon layers 33 ₁ and 33 ₂ for forming emitter and collector contacts can also be drawn out of the active element region if necessary.

According to the embodiments described above, the following effects can be obtained.

By self-alignment, the spacing between the electrode lead-out portions of the emitter region 35 and the base regions 29 ₁ , 29 ₂ , 32 is set to submicron, that is, as shown in FIG. 3H.
The base electrode can be reduced by the thickness of the silicon oxide films 30 ₁ and 30 ₂ shown in FIG.
Polycrystalline silicon layer 26 ₁ containing type impurities,
Since both are connected by 26 ₂ and brought out to the outside of the active element region, the emitter region 35 and base regions 29 ₁ , 29 ₂ , 32 and the entire element can be miniaturized to the utmost without reducing wiring alignment margin. , it is possible to achieve high integration, and furthermore, it is possible to simultaneously form a polycrystalline silicon resistor with almost no parasitic capacitance, and together with this, it is possible to achieve high speed and low power consumption.

In the conventional method, three masking steps are required to form the main base region, side base region, and emitter region, but according to the embodiment, selective oxidation of the first polycrystalline silicon layer 26 and second masking step are required to form the main base region, side base region, and emitter region. Only two masking steps for selectively removing the polycrystalline silicon layer 33 are required, which simplifies the process.

In the above embodiment, oxide film isolation was used for element isolation, but an isolation method such as PN isolation or a combination of PN isolation and oxide film isolation may also be used.

Further, a second polycrystalline silicon layer 33 is formed using non-doped polycrystalline silicon, and thereafter, a second polycrystalline silicon layer 33 is formed using non-doped polycrystalline silicon.
However, the second polycrystalline silicon layer 33 is formed using polycrystalline silicon containing a high concentration of N-type impurity, such as arsenic, in advance. Good too.
Furthermore, the selective removal of the second polycrystalline silicon layer 33 can be replaced by selective oxidation, in which case,
A process of introducing impurities after selective oxidation is desirable.

In addition, in the embodiment, the side base regions 29 ₁ ,
29 ₂ is arranged in the collector region 23 ₁ , the emitter region 35 may be brought closer to the isolation oxide film 24 and one of the side base regions 29 ₁ and 29 ₂ may be eliminated. In this way, the surface area of the base emitter region can be further reduced significantly.

As is clear from the above description, in the method for manufacturing a semiconductor integrated circuit device of the present invention, a first polycrystalline silicon substrate is formed on a silicon substrate of an opposite conductivity type, which has a first region of one conductivity type that serves as a collector on the surface. After forming a layer and selectively oxidizing it, a second region of an opposite conductivity type that becomes a side base is formed within the first region through a step of introducing impurities of an opposite conductivity type into the first polycrystalline silicon layer. After removing the silicon oxide film caused by the selective oxidation, silicon oxide films with different thicknesses are again formed on the surface of the first polycrystalline silicon layer and the exposed surface of the first region, and in this state,
A third region of the opposite conductivity type, which becomes the main base, is extended into the second region within the first region through a step of introducing an impurity of opposite conductivity type into the first region through a thin silicon oxide film on the first region. After that, the thin silicon oxide film is removed and a second polycrystalline silicon layer is formed on the thick silicon oxide film and the surface of the third region, and a polycrystalline silicon layer of one conductivity type is formed in the third region to serve as an emitter. It forms four areas. Therefore, the base and emitter regions, as well as the entire device, can be significantly reduced, allowing for higher integration, improved characteristics such as high-speed operation, and lower power consumption. Furthermore, the process is also greatly simplified. In particular, according to the method of the present invention, after removing the selectively oxidized silicon oxide film, a thin silicon oxide film is formed on the surface of the first region exposed thereby, and at the same time, a thick silicon oxide film is formed on the surface of the first polycrystalline silicon layer. The opening for forming the emitter is formed by forming a silicon oxide film and then removing only the thin silicon oxide film in self-alignment using the difference in film thickness, which simplifies the process. In addition, the distance between the emitter and base electrode lead-out parts can be reduced to the thickness of the silicon oxide film remaining at the end of the first polycrystalline silicon layer, and the distance between the emitter electrode lead-out part and the base electrode lead-out part can be significantly reduced. can be converted into The manufacturing method of the present invention having such effects can be applied to so-called ECL, STTL,
The present invention can be widely used in manufacturing methods for high-density, high-speed bipolar semiconductor integrated circuit devices using IIL or a mixture thereof.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an example of a conventional method for manufacturing a bipolar semiconductor integrated circuit device, and FIG. 2 is a cross-sectional view showing a part of the device according to the conventional method.
FIG. 3 is a sectional view showing an embodiment of the method for manufacturing a semiconductor integrated circuit device of the present invention, and FIG. 4 is a plan view showing the main parts of the device obtained by the embodiment. 21... P-type silicon substrate, 23 ₁ ... collector region, 26... first polycrystalline silicon layer, 26 ₁ , 2
6 ₂ ... polycrystalline silicon layer, 27 ₁ , 27 ₂ ... mask layer, 28 ... thermally grown silicon oxide film, 29 ₁ , 29 ₂
...P ⁺ type side base region, 30 ₁ , 30 ₂ ... thick silicon oxide film, 31 ₁ ... thin silicon oxide film, 3
2... P-type main base region, 33... second polycrystalline silicon layer, 33 ₁ ... polycrystalline silicon layer, 35...
Emitsuta area.

Claims (1)

[Claims] 1. A step of preparing a silicon substrate of an opposite conductivity type having a first region of one conductivity type serving as a collector on the surface, a step of forming a first polycrystalline silicon layer on the surface of this silicon substrate, and a step of forming a first polycrystalline silicon layer on the surface of this silicon substrate. forming a mask layer for selective oxidation on a selected surface of the polycrystalline silicon layer; and converting the first polycrystalline silicon layer, which does not have the mask layer on the surface, into a silicon oxide film by selective oxidation; a step of introducing an impurity of an opposite conductivity type into the first polycrystalline silicon layer after removing the mask layer; forming a second region of opposite conductivity type, and removing the silicon oxide film to form a second region of opposite conductivity type;
a step of exposing the surface of the region, and a step of forming a thick silicon oxide film on the surface of the first polycrystalline silicon layer and simultaneously forming a thin silicon oxide film on the surface of the first region by low-temperature oxidation at 700° C. or less. and the first film through the thin silicon oxide film.
A step of introducing an impurity of opposite conductivity type into the region, a step of forming a third region of opposite conductivity type extending into the second region and serving as a main base within the first region, and utilizing a difference in film thickness. and removing the thin silicon oxide film by self-alignment, forming a second polycrystalline silicon layer of one conductivity type on the thick silicon oxide film and the surface of the third region; A method for manufacturing a bipolar semiconductor integrated circuit device, comprising the steps of: forming a fourth region of one conductivity type to serve as an emitter.