JPH038582B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bipolar semiconductor integrated circuit device.

In the manufacturing of bipolar semiconductor integrated circuits,
Reducing the element area not only improves the integration density but also reduces parasitic capacitance, which enables lower power consumption and higher speed operation.

For the above purpose, a number of technologies have been developed in recent years to further significantly reduce the base area of a transistor, which is usually defined by the microfabrication limit of electrode metal and mask alignment margin, by taking out the electrode using polycrystalline silicon. An example of this is shown in Figure 1.

As mentioned above, Figure 1 shows an electrode taken out using self-alignment technology using polycrystalline silicon, and polycrystalline silicon used as a resistor to reduce parasitic capacitance. A step-by-step explanation will be given below.

First, N ⁺ buried diffusion is performed on a P-type substrate using a known technique, and through an N ^- type epitaxial layer growth and oxide film separation process, an N ⁺ layer for reducing collector resistance is applied.
FIG. 1A shows the state after the deep collector region has been diffused until it reaches the N ⁺ buried layer.

That is, in FIG. 1A, 1 is a P ^- type silicon substrate, 2 is an N ⁺ type buried diffusion layer, 3 is an N ^- type epitaxial layer serving as a collector, 4 is an element isolation silicon oxide film, and 5 is an N ^{+ type} buried diffusion layer. This is a deep collector area.

Next, as shown in FIG. 1B, P is selectively added to the surface of the collector layer 3 by a method such as ion implantation.
A type impurity, for example, boron, is introduced to form the main base layer 6.

Subsequently, the surfaces of the main base layer 6 and deep collector region 5 are exposed, and as shown in FIG. 1C,
A polycrystalline silicon layer 7 is grown on the entire surface, and a predetermined portion on the polycrystalline silicon layer 7, that is,
Mask layers 8 ₁ , 8 ₂ , 8 ₃ , for selective oxidation are formed in areas where side base and base electrode extension parts, emitter/collector electrodes, resistors, etc. are planned to be formed.
8 Form ₄ . These mask layers 8 ₁ , 8 ₂ , 8 ₃ , 8 ₄
It consists of a two-layer film in which a silicon nitride film is laminated on a thin silicon oxide film.

_{Next ,} by selective _oxidation treatment _, as _{shown in FIG .} The remaining polycrystalline silicon layer without a mask layer on its surface is replaced with a silicon oxide film 9.

Subsequently, a mask layer 8 ₁ is formed on the side base and base electrode extension portions and the portion where the resistor is formed.
8 ₄ is removed, and a high concentration P-type impurity, such as boron, is introduced into the polycrystalline silicon layers 7 ₁ and 7 ₄ by ion implantation or the like, and a thermal oxidation treatment is performed. At this time, as shown in _FIG .
becomes.

Subsequently, the remaining mask layers 8 ₂ and 8 ₃ are removed,
A high concentration of N-type impurity, for example, arsenic, is introduced into the polycrystalline silicon layers 7 ₂ and 7 ₃ in this portion, and a thermal oxidation treatment is applied to the emitter region 1 in the main base layer 6.
1 (Fig. 1F). At the same time, the side base region 10 is diffused deeper.

_{Thereafter ,} as _shown in FIG.
After performing steps ₄ and 12 ₅ , a semiconductor integrated circuit device is completed. The contact hole is opened in a self-aligned manner by the surrounding thick silicon oxide film 9, and the base electrode is drawn out of the element area by the polycrystalline silicon layer ₇₁ , and a metal wiring ₁₂₁ is formed on it. Connected.

Note that both ends of the emitter region 11 in the direction perpendicular to the plane of the paper are in contact with the isolation oxide film 4, forming a so-called wall emitter structure.

The above manufacturing method is an excellent method that makes it possible to easily form a wall-emitter structure transistor with high breakdown voltage and to significantly reduce the device area by drawing out the base electrode using polycrystalline silicon. It also has disadvantages as listed below.

(1) Since there is a lot of heat treatment between the formation of the main base layer (FIG. 1B) and the formation of the emitter region (FIG. 1F), the main base layer becomes deep.

(2) When removing the mask layer ₈₂ on the emitter region, sufficient overetching was not possible, so a wedge-shaped silicon oxide film (so-called bird's beak) was formed between the polycrystalline silicon layer ₇₂ and the mask layer ₈₂ . s beak) remains, making it difficult to supply sufficient N-type impurities into the polycrystalline silicon layer ₇₂ .

(3) Since the impurity diffusion coefficient in polycrystalline silicon is significantly faster than that in single-crystalline silicon, the N-type impurity introduced into the polycrystalline silicon layer ₇₂ on the emitter region is absorbed into the polycrystalline silicon layer ₇₂ . After becoming uniform, it diffuses into the main base layer 6 to form the emitter region 11, but the polycrystalline silicon layer 7
Since the film thickness of _{No. 2} is thick, a high emitter surface concentration cannot be obtained.

(4) The layer resistance of a polycrystalline silicon layer at a high impurity concentration strongly depends on the film thickness, and becomes higher as the film thickness becomes thinner. Therefore, it is difficult to reduce the resistance of the polycrystalline silicon layer ₇₁ for leading out the base electrode, whose thickness has been reduced by the two oxidation treatments.

(5) Similarly, since the amount of change in the film thickness of the resistor polycrystalline silicon layer ₇₄ is large, the reproducibility of the resistance value is poor.

(6) A high-resistance main base layer 6 is interposed between the emitter region 11 and the side base region 10.

Among the above, due to items (1), (2), and (3), the base width of the transistor becomes wide and the emitter concentration is low, so the injection efficiency is low and it is difficult to obtain a high emitter common current amplification factor h _fe . Therefore, the cutoff frequency f _T cannot be increased.

Furthermore, the base series resistance r _b increases due to items (4) and (6), and both of the above two points deteriorate the high frequency characteristics of the transistor.

In other words, by miniaturizing the elements and using polycrystalline silicon resistors, parasitic capacitance is reduced and the delay time power consumption product is improved in the low power consumption region (low current region), but even if the current is further increased, the delay The time is not reduced as much as with a structure that does not use normal polycrystalline silicon, and for the reason in item (5) above, the characteristics of integrated circuit devices depend sensitively on fluctuations in processing conditions, and stable performance cannot be achieved. It has the disadvantage that it is difficult to obtain.

Furthermore, to improve item (1), low-temperature treatment is required, but if the temperature of the oxidation treatment after introducing P-type impurities (boron) into the polycrystalline silicon layers 7 ₁ and 7 ₄ is lowered, the polycrystalline silicon layer The segregation of impurities into the silicon oxide film that grows from the base increases, increasing the base series resistance r _b and increasing the fluctuation of the resistance value.

In addition, in order to improve items (2) and (3), it is necessary to thicken the oxide film on the polycrystalline silicon layers 7 ₁ and 7 ₄ , which worsens items (4) and (5). invite. As mentioned above, paragraphs (1) to (3), and paragraphs (4) and (5) had contradictory requirements.

This invention was made in consideration of the above points, and has a high emitter grounded current amplification factor (hereinafter referred to as h _fe ), a high cut-off frequency (hereinafter referred to as f _T ), and a low base series resistance (hereinafter referred to as r _{b )} . It is an object of the present invention to provide a method for manufacturing a high-density bipolar type semiconductor integrated circuit device that has a transistor having a transistor having the above characteristics and a stable polycrystalline silicon resistor, and has both low power consumption and high speed.

Embodiments of the method for manufacturing a semiconductor integrated circuit device of the present invention will be described below with reference to the drawings.

FIGS. 2A to 2G are diagrams for explaining the manufacturing process of one embodiment, and among these figures, FIGS.
The same parts are given the same reference numerals and their explanation will be omitted.

FIG. 2A shows a state in which the surface of the epitaxial layer (first region) 3 serving as a collector and the deep collector region 5 are exposed after the formation of the deep collector region 5 is completed in the same manner as in the conventional example. It is.

Next, as shown in FIG. 2B, a polycrystalline silicon layer 7 is grown on the entire surface of the silicon substrate 1 to a thickness of about 2000 to 6000 mm, and a silicon oxide film is formed on the entire surface of this polycrystalline silicon layer 7. A mask layer 8 made of a silicon nitride film is laminated.

_{Subsequently ,} as _{shown in} FIG.
After that, in order to form the main base layer (second region) 6 ₁ , 6 ₂ , a P-type impurity, such as boron, is added to about 10 ¹⁴ cm ^-2 by ion implantation.
It is introduced into the epitaxial layer (first region) 3.
In this case, by selecting an appropriate acceleration energy, the impurity concentration can be increased in the polycrystalline silicon layer 7 in the portion directly below the mask layers 8 ₁ and 8 ₂ and in the epitaxial layer 3 in the portion where the mask layer has been removed. Let it happen. After that, when annealing is performed at a temperature of about 900°C, the main base layer 6 is relatively shallow and has a low concentration (high layer resistance) directly below the mask layers 8 ₁ and 8 ₂ .
₁ is formed, and a deep, high concentration (low layer resistance) main base layer 6 ₂ is formed in the portion where there is no mask layer.

Next, as shown in FIG. 2D, unnecessary portions of the polycrystalline silicon layer 7 are oxidized and converted into a polycrystalline silicon oxide film 9. In this case, the main base layer 6
_1,6 In order not to deepen ₂ , high pressure oxidation etc. are used.
It is desirable to form the silicon oxide film 9 at a low temperature of about 900°C.

Next, the mask layers 8 ₂ and 8 ₃ in the portions where the emitter and collector electrodes will be formed are selectively removed, and N-type impurities are implanted into the removed portions of the polycrystalline silicon layers 7 ₂ and 7 ₃ by ion implantation or the like. , for example arsenic 10 ¹⁶
By introducing it at a high concentration of about cm ^-2 and thermally oxidizing it at a temperature of about 900℃, as shown in Figure 2E,
A thick silicon oxide film is formed on the polycrystalline silicon layers 7 ₂ and 7 ₃ to reduce the thickness of the polycrystalline silicon layers 7 ₂ and 7 ₃ . At this time, N in the polycrystalline silicon layer ₇₂
Some of the mold impurities diffuse into the main base ₆₁ ,
An emitter region (third region) 11 is formed. Note that when removing the silicon oxide film below the mask layers 8 ₂ and 8 ₃ , it is difficult to remove the bird's beak because the surrounding area is covered with a very thick polycrystalline silicon oxide film 9 and the mask layers 8 ₁ and 8 ₄ . You can do enough over-sex.

Next, as shown in FIG. 2F, the remaining mask layers 8 ₁ and 8 ₄ are removed, and the polycrystalline silicon layers 7 ₁ and 7 ₄ are removed.
By introducing a P-type impurity such as boron into the main base layer 6 at a high concentration of about 10 ¹⁵ to 10 ¹⁶ cm ^-2 and performing thermal oxidation treatment at a temperature of about 900°C to 1000°C, the main base layer 6 with a low impurity concentration is formed. ₁ inside the side base area (4th
At the same time, the emitter region (third region) 11 is further deeply diffused and controlled so as to obtain an appropriate h _fe .

Subsequently, as in the conventional example, as shown in FIG. 2G, contact holes are opened and metal wirings 12 ₁ ,
12 ₂ , 12 ₃ , 12 ₄ , and 12 ₅ are applied to complete the semiconductor integrated circuit device.

According to one embodiment as described above, the following advantages can be obtained.

(a) All heat treatments from the formation of the main base layer to before the formation of the emitter region can be performed at a low temperature of about 900°C or less, so the main base layer does not become deep.

(b) When removing the mask layer ₈₂ on the emitter region, sufficient overetching is possible;
Since the bird's beak is removed, N-type impurities can be sufficiently supplied into the polycrystalline silicon layer ₇₂ .

(c) Since the segregation coefficient of N-type impurities such as arsenic is as large as about 10, even after forming a thick oxide film on the surface of the polycrystalline silicon layer ₇₂ , the thickness of most N-type impurities is reduced. The N-type impurity concentration remains in the polycrystalline silicon layer ₇₂ , and thus the emitter region 11 having a high surface concentration can be formed.

(d) The main base layer 6 ₂ between the emitter region and the side base region has a low layer resistance, and the polycrystalline silicon layer 7 ₁ for drawing out the base electrode.
Since the amount of oxidation of the polycrystalline silicon layer 71 is small and the polycrystalline silicon layer ₇₁ is kept thick, it is easy to lower the resistance of the polycrystalline silicon layer 71, so that r _b is small.

(e) Similarly, since there is little change in the thickness of the polycrystalline silicon layer ₇₄ for resistance, the reproducibility of the resistance value is good.

As described above, this embodiment can eliminate all the drawbacks of semiconductor integrated circuit devices manufactured by conventional manufacturing methods, and is suitable for high-speed operation with high h _fe , f _T and low r _b . It is possible to manufacture a semiconductor integrated circuit device with stable performance, low power consumption, high-speed operation, and a polycrystalline silicon resistor with good resistance value reproducibility.

In the above embodiment, a semiconductor integrated circuit device having the structure shown in FIG. Can be applied.

In the above-mentioned embodiment, the shallow main base layer ₆₁ with a low concentration and the deep main base layer ₆₂ with a high concentration were simultaneously formed in FIG. 2C. First, a shallow main base layer ₆₂ with a low concentration is formed _, and then, as shown in _FIG . High concentration and slightly deep main base layer 6 ₂ due to implantation
The same advantages can be obtained even if the resists 13 ₁ to 13 4 are formed, and then the resists 13 1 to _{13 4} are removed, and the same steps as in the manufacturing method of the embodiment shown in FIG. 2 are performed thereafter.

As detailed above, according to the manufacturing method of the present invention, the side base region is formed after the emitter region is formed, and the resistance of the main base layer interposed between the emitter region and the side base region is reduced. As a result, it is possible to form a transistor suitable for high-speed operation and a stable polycrystalline silicon resistor, which also has the effect of having small parasitic capacitance. It can be widely used in manufacturing high-density semiconductor integrated circuit devices.

[Brief explanation of the drawing]

1A to 1G are cross-sectional views showing a conventional method for manufacturing a semiconductor integrated circuit device in order of steps, and FIGS. 2A to G are sectional views showing a method for manufacturing a semiconductor integrated circuit device in order of steps according to an embodiment of the present invention. , FIGS. 3A and 3B are cross-sectional views showing the main parts of a method for manufacturing a semiconductor integrated circuit device according to another embodiment in the order of steps. 1... Silicon substrate, 2... Buried diffusion layer, 3...
...Epitaxial layer, 4...Silicon oxide film, 5
...Deep collector region, _6,61,62 ...Main base layer, _{7,71 to 74} ...Polycrystalline silicon layer, _8,81 to ₈₄ ...Mask layer, 9...Polycrystalline silicon layer Silicon oxide film, 10...Side base region, 11
... Emitter region, 12 ₁ to 12 ₅ ... Metal wiring,
13 ₁ to 13 ₄ ...Resist.

Claims (1)

[Scope of Claims] 1. In a method of manufacturing a bipolar semiconductor integrated circuit device in which an electrode lead-out portion is formed of polycrystalline silicon, the entire surface of a semiconductor substrate of a second conductivity type has a predetermined region of a first conductivity type on the surface thereof. forming a crystalline silicon layer; and on a selected surface of the polycrystalline silicon layer;
forming a mask layer for selective oxidation; using the mask layer, the emitter region and side base region of the semiconductor substrate are reduced in impurity concentration; forming a main base layer of the second conductivity type in which the portion intervening with the planned side base region is highly impurity-concentrated; and forming the polycrystalline silicon layer without the mask layer on the surface by selective thermal oxidation. a step of converting the silicon oxide film into a silicon oxide film; a step of removing a predetermined portion of the mask layer by overetching and removing a bird's beak portion of the silicon oxide film under the mask layer to be removed; and a step of removing the mask layer. a step of introducing a high concentration of a first conductivity type impurity into the polycrystalline silicon layer; and a thermal oxidation treatment to reduce the film thickness of the polycrystalline silicon layer into which the first conductivity type impurity has been introduced; a step of diffusing the first conductivity type impurity into the emitter region of the layer to form a first conductivity type emitter region; a step of completely removing the remaining mask layer; and a second conductivity type impurity diffusion step. A semiconductor integrated circuit comprising the step of: forming a highly doped side base region of a second conductivity type in the main base layer by diffusing it into the side base region of the main base layer. Method of manufacturing the device.