JPH0128554B2 - - Google Patents

Info

Publication number
JPH0128554B2
JPH0128554B2 JP18692980A JP18692980A JPH0128554B2 JP H0128554 B2 JPH0128554 B2 JP H0128554B2 JP 18692980 A JP18692980 A JP 18692980A JP 18692980 A JP18692980 A JP 18692980A JP H0128554 B2 JPH0128554 B2 JP H0128554B2
Authority
JP
Japan
Prior art keywords
signal
modulated
input
phase
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18692980A
Other languages
Japanese (ja)
Other versions
JPS57111158A (en
Inventor
Hideo Ashida
Yasuhiro Yano
Hideki Ikuta
Yoshihiro Ishama
Tetsuji Nakatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18692980A priority Critical patent/JPS57111158A/en
Publication of JPS57111158A publication Critical patent/JPS57111158A/en
Publication of JPH0128554B2 publication Critical patent/JPH0128554B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20Modulator circuits; Transmitter circuits
    • H04L27/2032Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2035Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Description

【発明の詳細な説明】 本発明はマイクロ波帯の反射形位相変調器に係
り特に簡易な構成で高速に動作するFETを用い
た反射形位相変調器に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reflective phase modulator in the microwave band, and particularly to a reflective phase modulator using an FET that has a simple configuration and operates at high speed.

従来マイクロ波帯の反射形位相変調器としては
PINダイオードあるいはシヨツトキ・バリア・ダ
イオードなどの素子が用いられている。前者は被
変調パルス信号によりダイオードの順方向、逆方
向をスイツチングするため、順方向から逆方向に
スイツチングするときに、I層に蓄積された少数
キヤリアが高速変調器の動作を制限すると同時に
順方向に多量の電流を流すために変調パルス増幅
器として大電力を要するという欠点があり、後者
はマイクロ波帯の電力として大きな電力を変調す
ることができないという欠点がある。また両者と
もダイオードであるため、マイクロ波帯の入力信
号と被変調信号とを分離する回路を必要とする。
As a conventional microwave band reflective phase modulator,
Elements such as PIN diodes or shot barrier diodes are used. In the former case, the forward and reverse directions of the diode are switched by a modulated pulse signal, so when switching from the forward direction to the reverse direction, the minority carriers accumulated in the I layer limit the operation of the high-speed modulator and at the same time switch the diode in the forward direction. The latter has the disadvantage that it requires a large amount of power as a modulated pulse amplifier in order to pass a large amount of current through it, and the latter has the disadvantage that it cannot modulate large amounts of power in the microwave band. Furthermore, since both are diodes, a circuit is required to separate the microwave band input signal and the modulated signal.

本発明はこのような従来技術の欠点を除去しよ
うとするもので、変調素子としてFETを用い変
調信号と被変調信号とをそれぞれアイソレートし
た構造で、かつ低電力でドライブ可能なマイクロ
波帯の反射形位相変調器の提供を目的とする。
The present invention aims to eliminate these drawbacks of the conventional technology, and has a structure in which the modulating signal and the modulated signal are isolated using an FET as a modulating element, and is capable of being driven in the microwave band with low power. The purpose of this invention is to provide a reflective phase modulator.

この目的を達成するため本発明のマイクロ波帯
の反射形位相変調器においては、入出力分離回路
の入出力端子以外の端子の終端にFETのドレイ
ン、ソースの一方を接続し、他方を接地しゲート
より被変調パルス信号を印加し該パルス信号で該
分離回路入力端子より加えられた高周波信号を位
相変調し出力端子より変調された高周波信号を取
り出すことを特徴としている。
To achieve this purpose, in the microwave band reflective phase modulator of the present invention, one of the drain and source of the FET is connected to the terminal other than the input/output terminal of the input/output separation circuit, and the other is grounded. It is characterized in that a modulated pulse signal is applied from the gate, the pulse signal phase-modulates the high frequency signal applied from the input terminal of the separation circuit, and the modulated high frequency signal is taken out from the output terminal.

すなわち本発明は、FETのドレイン、ソース
間に直流バイアス電圧を印加しない状態で、ドレ
イン、ソース間のインピーダンスがゲート印加電
圧により変化する特性を利用し、ゲートにパルス
信号(被変調信号)を印加し、マイクロ波帯の信
号を位相変調するものである。
In other words, the present invention utilizes the characteristic that the impedance between the drain and source changes depending on the gate applied voltage, and applies a pulse signal (modulated signal) to the gate without applying a DC bias voltage between the drain and source of the FET. It phase modulates the microwave band signal.

以下図面を用いて本発明を詳細に説明する。 The present invention will be explained in detail below using the drawings.

第1図は本発明の原理を説明するための構成図
であり、伝送線路4の一端と接地導体間にFET
1のドレインDとソースSをそれぞれ接続し、ド
レイン、ソース間に直流バイアスを印加せずに、
かつゲートGに逆バイアスとなるように直流電圧
2を印加している。又3はバイアス調整用の分圧
器である。今ゲート電圧Vgを変化し、ゲート電
圧Vgをパラメータとして、FETの反射係数をイ
ンピーダンスチヤート上にプロツトすると第2図
に示すような特性を示す。すなわちゲート電圧−
1.5〜1.6Vの間では反射波は最少となり、ゲート
電圧を増減させるとそれぞれ反射波の位相はほぼ
180゜の位相差を呈する。
FIG. 1 is a configuration diagram for explaining the principle of the present invention, in which an FET is connected between one end of the transmission line 4 and the ground conductor
Connect the drain D and source S of 1, respectively, and do not apply a DC bias between the drain and source.
Further, a DC voltage 2 is applied to the gate G so as to provide a reverse bias. Further, 3 is a voltage divider for bias adjustment. If we change the gate voltage Vg and plot the reflection coefficient of the FET on an impedance chart using the gate voltage Vg as a parameter, we will see the characteristics shown in Figure 2. In other words, the gate voltage -
The reflected wave is at its minimum between 1.5 and 1.6V, and when the gate voltage is increased or decreased, the phase of the reflected wave becomes almost the same.
Exhibits a phase difference of 180°.

第3図は本発明による一実施例の構成図であり
2相の位相変調器の場合を示す。
FIG. 3 is a block diagram of an embodiment according to the present invention, and shows the case of a two-phase phase modulator.

図において、1はFET、2はゲートバイアス
用電源、3はバイアス調整用分圧器、12はパル
ス増幅器、5は被変調パルス入力端子、6はゲー
トバイアスとパルス信号の重畳器、7はマイクロ
波阻止用チヨーク、8は入出力分離用のサーキユ
レータ、9は高周波信号入力端子、10は高周波
変調信号出力端子、11は変調位相の補正用整合
回路である。
In the figure, 1 is a FET, 2 is a gate bias power supply, 3 is a voltage divider for bias adjustment, 12 is a pulse amplifier, 5 is a modulated pulse input terminal, 6 is a gate bias and pulse signal superimposer, and 7 is a microwave 8 is a circulator for input/output separation; 9 is a high frequency signal input terminal; 10 is a high frequency modulation signal output terminal; 11 is a matching circuit for correcting the modulation phase.

高周波信号入力端子9より入力した高周波信号
はサーキユレータ8、整合回路11を介して
FET1のドレインDに入力する。一方被変調パ
ルス入力端子5より入力したパルス信号はパルス
増幅器12、重畳器6を介してFET1のゲート
Gに加えられる。この場合パルス信号は重畳器6
にてバイアス変化を受けている。したがつて前述
の説明(第1図についての説明)の如くFET1
のドレインDに入力した高周波信号はゲート信号
(パルス信号)により2相に移相され、サーキユ
レータ8の出力端子10に2相に移相された変調
信号がとり出される。
The high frequency signal input from the high frequency signal input terminal 9 is passed through the circulator 8 and the matching circuit 11.
Input to drain D of FET1. On the other hand, a pulse signal inputted from the modulated pulse input terminal 5 is applied to the gate G of the FET 1 via the pulse amplifier 12 and the superimposed device 6. In this case, the pulse signal is
The bias has been changed by . Therefore, as explained above (explanation regarding Fig. 1), FET1
The high frequency signal inputted to the drain D of the circulator 8 is phase-shifted into two phases by a gate signal (pulse signal), and a modulated signal whose phase is shifted into two phases is taken out at the output terminal 10 of the circulator 8.

又FET1のドレインDとゲートGは電気的に
絶縁されているため、従来例で述べた高周波信号
と被変調信号とを分離するための回路は不必要と
なる。
Furthermore, since the drain D and gate G of the FET 1 are electrically insulated, the circuit for separating the high frequency signal and the modulated signal described in the conventional example is unnecessary.

第4図は第3図のサーキユレータ8の代わりに
ハイブリツト回路13を用いた場合の構成図であ
り、端子9,10はハイブリツド13のアイソレ
ーシヨン特性を示す端子である。
FIG. 4 is a block diagram when a hybrid circuit 13 is used in place of the circulator 8 shown in FIG.

第5図は本発明を4相位相変調器に実施した一
例である。16は高周波信号を分岐し、変調器1
4および変調器15に信号をそれぞれ同相で供給
する。変調された信号は17のハイブリツドで
90゜の位相差で合成される。すなわち、合成され
た出力はCH1、CH2の入力パルスにより0゜、
90゜180゜、270゜の位相変調される信号となる。
FIG. 5 is an example in which the present invention is implemented in a four-phase phase modulator. 16 branches the high frequency signal and modulator 1
4 and a modulator 15, respectively, in phase. The modulated signal is a hybrid of 17
They are synthesized with a phase difference of 90°. In other words, the combined output is 0°, due to the input pulses of CH1 and CH2.
The signal is phase modulated at 90°, 180°, and 270°.

以上詳細に述べた如く本発明による位相変調器
はFETを用いるため少電力で動作すると共に高
周波信号と被変調信号の分離する回路も不必要と
なり、その利点は大きい。
As described in detail above, since the phase modulator according to the present invention uses FET, it operates with less power and also eliminates the need for a circuit for separating the high frequency signal and the modulated signal, which has great advantages.

なお、FETはドレインとソースは電気的に対
称性を持つているのでドレインとソースをそれぞ
れ入れ替えても同様に本発明の目的が達成され
る。
Note that since the drain and source of the FET have electrical symmetry, the object of the present invention can be achieved in the same way even if the drain and source are interchanged.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理を説明するための構成
図、第2図は第1図の特性図、第3図は本発明の
一実施例、第4図、第5図は他の実施例を示す。 1……FET、8……入出力分離回路、9……
入力端子、10……出力端子、D……ドレイン、
S……ソース、G……ゲート。
Fig. 1 is a configuration diagram for explaining the principle of the present invention, Fig. 2 is a characteristic diagram of Fig. 1, Fig. 3 is one embodiment of the present invention, and Figs. 4 and 5 are other embodiments. shows. 1...FET, 8...Input/output separation circuit, 9...
Input terminal, 10...Output terminal, D...Drain,
S...source, G...gate.

Claims (1)

【特許請求の範囲】[Claims] 1 入出力分離回路の入出力端子以外の端子の終
端にFETのドレインとソースの一方を接続し他
方を接地し、ゲートより被変調パルス信号を印加
し該パルス信号で該分離回路入力端子より加えら
れた高周波信号を位相変調し出力端子より変調さ
れた高周波信号を取り出すことを特徴とした反射
形位相変調器。
1 Connect one of the drain and source of the FET to the terminal of the terminal other than the input/output terminal of the input/output separation circuit, ground the other, apply a modulated pulse signal from the gate, and apply the modulated pulse signal from the input terminal of the separation circuit with the pulse signal. A reflective phase modulator characterized in that it phase-modulates a high-frequency signal that is generated and extracts the modulated high-frequency signal from an output terminal.
JP18692980A 1980-12-26 1980-12-26 Reflective phase modulator Granted JPS57111158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18692980A JPS57111158A (en) 1980-12-26 1980-12-26 Reflective phase modulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18692980A JPS57111158A (en) 1980-12-26 1980-12-26 Reflective phase modulator

Publications (2)

Publication Number Publication Date
JPS57111158A JPS57111158A (en) 1982-07-10
JPH0128554B2 true JPH0128554B2 (en) 1989-06-02

Family

ID=16197178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18692980A Granted JPS57111158A (en) 1980-12-26 1980-12-26 Reflective phase modulator

Country Status (1)

Country Link
JP (1) JPS57111158A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2351423A (en) 1999-06-25 2000-12-27 Marconi Electronic Syst Ltd Modulator circuit

Also Published As

Publication number Publication date
JPS57111158A (en) 1982-07-10

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