JPH01286355A - Thin film resistance element - Google Patents

Thin film resistance element

Info

Publication number
JPH01286355A
JPH01286355A JP63116102A JP11610288A JPH01286355A JP H01286355 A JPH01286355 A JP H01286355A JP 63116102 A JP63116102 A JP 63116102A JP 11610288 A JP11610288 A JP 11610288A JP H01286355 A JPH01286355 A JP H01286355A
Authority
JP
Japan
Prior art keywords
film
thin film
pattern
resistance element
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63116102A
Other languages
Japanese (ja)
Inventor
Shoji Takayama
高山 正二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63116102A priority Critical patent/JPH01286355A/en
Publication of JPH01286355A publication Critical patent/JPH01286355A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/209Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁膜上に形成した薄膜抵抗素子の形状に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the shape of a thin film resistive element formed on an insulating film.

〔従来の技術〕[Conventional technology]

従来、薄膜抵抗素子は平坦な絶縁膜上に形成され、抵抗
用薄膜の膜厚と材料によって決まる面積抵抗から、平面
パターンの長さと幅の比をきめて所定の抵抗値を実現す
るパターンを形成していた。
Conventionally, thin-film resistive elements are formed on a flat insulating film, and a pattern that achieves a predetermined resistance value is formed by determining the length-to-width ratio of the flat pattern based on the sheet resistance determined by the thickness and material of the resistive thin film. Was.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の薄膜抵抗素子では、高抵抗を実現する場
合、抵抗パターンの長さと幅の比を大きくする必要があ
る。抵抗パターンの長さと幅の比を大きくする方法とし
ては、パターン幅を細くする事が考えられるが、電流容
量やパターン精度の点から限界がある。したがって通常
はパターン長を長くする事により所望の高抵抗値を実現
している。しかしながら、パターン長を長くすることは
それだけ広い面積を必要とするので、半導体集積回路装
置等においては集植度の点で非常に不利となる。
In the conventional thin film resistance element described above, in order to achieve high resistance, it is necessary to increase the length-to-width ratio of the resistance pattern. One possible method for increasing the length-to-width ratio of a resistor pattern is to make the pattern width thinner, but there is a limit in terms of current capacity and pattern accuracy. Therefore, a desired high resistance value is usually achieved by increasing the pattern length. However, increasing the pattern length requires a correspondingly larger area, which is very disadvantageous in terms of density in semiconductor integrated circuit devices and the like.

本発明の目的は、上記の欠点を除去して、広い面積を必
要とせず、高抵抗値をうることのできる薄膜抵抗素子を
提供することにある。
An object of the present invention is to eliminate the above-mentioned drawbacks and provide a thin film resistive element that does not require a large area and can provide a high resistance value.

〔課鐙を解決するための手段〕[Means for resolving division stirrups]

本発明の薄膜抵抗素子は、下地絶縁膜が経路上に凹凸部
を有し、該凹部の対向する側面に形成した薄膜が互いに
接触しないように、凹部径・膜厚を設定してなるもので
ある。
In the thin film resistance element of the present invention, the underlying insulating film has an uneven portion on the path, and the diameter and thickness of the recess are set so that the thin films formed on the opposing sides of the recess do not come into contact with each other. be.

、〔作用〕 薄膜抵抗素子の実効的長さが、凹凸部を設けることによ
り長くなる。しかも投影平面では、面積的に絶縁膜が平
坦な場合と同じになしうる。
, [Function] The effective length of the thin film resistance element is increased by providing the uneven portion. Moreover, on the projection plane, the area can be the same as when the insulating film is flat.

〔実施例〕〔Example〕

以下、図面を参照して、本発明の実施例につき説明する
。第1図(a)は第1実施例の平面パターン図であり、
同図(b)はA−A’線断面図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1(a) is a plan pattern diagram of the first embodiment,
Figure (b) is a sectional view taken along the line AA'.

薄膜抵抗素子は、シリコン基板3上に積層したシリコン
窒化膜4上に、線状のポリシリコン抵抗パターン1とし
て形成されている。シリコン窒化膜4は経路上に、経路
に対して直角になる四部2が設けられ、第1図(b)に
示すように、ポリシリコン膜5が凹部2の側面および底
面をおおって、この四部2内にも電流経路が形成される
。したがって、薄膜抵抗素子のシリコン基板3に対する
投影平面として、平坦な絶縁膜上に形成した薄膜抵抗素
子と同一の長さであっても、実効的な経路長が長くなる
。これによって幅を格段と狭くしないでも、高抵抗値を
うることができる。
The thin film resistance element is formed as a linear polysilicon resistance pattern 1 on a silicon nitride film 4 laminated on a silicon substrate 3. The silicon nitride film 4 is provided with four parts 2 perpendicular to the route on the path, and as shown in FIG. A current path is also formed within 2. Therefore, even if the projection plane of the thin film resistive element onto the silicon substrate 3 has the same length as that of a thin film resistive element formed on a flat insulating film, the effective path length becomes longer. This allows a high resistance value to be obtained without significantly narrowing the width.

本実施例では、例えばシリコン基板3上に厚さ3gmの
シリコン窒化膜4をCVD法により全面に被着形成後、
リアクティブイオンエツチング法によりシリコン窒化膜
4に深さ271mの溝を作り不純物としてリンを含有す
る厚さ0.5pmのポリシリコン膜5をパターニングす
ることにより実現する事ができる。この場合ポリシリコ
ン膜5の投影平面上の長さを14JLmとして第1図(
a)(b)に示す様にシリコン窒化膜4の四部2を3箇
所設けることによりポリシリコン抵抗パターン1の実効
長は23ルmとなり、平坦な絶縁膜上に形成された抵抗
パターンの約1.6倍の長さとなる。したがって、同−
面積で従来技術の1.6倍の抵抗が実現できる。ポリシ
リコン膜5の幅を2gm、面積抵抗を40Ω/口とする
と、従来技術では280Ωであった抵抗が460Ωとす
る事ができる。抵抗値は、シリコン窒化膜4の四部2の
数を増加するに従い増加させる事ができる。
In this embodiment, for example, after forming a silicon nitride film 4 with a thickness of 3 gm on the entire surface of the silicon substrate 3 by CVD method,
This can be realized by forming a groove with a depth of 271 m in the silicon nitride film 4 using a reactive ion etching method and patterning a polysilicon film 5 with a thickness of 0.5 pm containing phosphorus as an impurity. In this case, the length of the polysilicon film 5 on the projection plane is assumed to be 14 JLm as shown in FIG.
By providing the four parts 2 of the silicon nitride film 4 at three locations as shown in a) and (b), the effective length of the polysilicon resistor pattern 1 becomes 23 m, which is approximately 1 m long of the resistor pattern formed on the flat insulating film. .6 times as long. Therefore, the same
A resistance 1.6 times larger than that of conventional technology can be achieved in terms of area. Assuming that the width of the polysilicon film 5 is 2 gm and the sheet resistance is 40 Ω/hole, the resistance can be increased from 280 Ω in the prior art to 460 Ω. The resistance value can be increased as the number of four parts 2 of the silicon nitride film 4 is increased.

なお、四部において、四部の側面に形成されたポリシリ
コン膜が互いに接触すれば、実効長のこの部分の増大は
なくなる。したがって、膜厚・凹部の径を上記の接触が
ないように定めることはいうまでもない。
Note that if the polysilicon films formed on the side surfaces of the four parts come into contact with each other, the effective length will not increase in this part. Therefore, it goes without saying that the film thickness and the diameter of the recess should be determined so that the above-mentioned contact does not occur.

次に第2実施例につき説明する。第2図(a)は平面パ
ターン図であり、同1ffl(b)はB−B’線断面図
である。
Next, a second embodiment will be explained. FIG. 2(a) is a plane pattern diagram, and FIG. 2(b) is a sectional view taken along the line BB'.

本実施例ではシリコンクロム抵抗パターン6に対してシ
リコン酸化膜凸部7が直交するように形成されている。
In this embodiment, the silicon oxide film convex portion 7 is formed perpendicularly to the silicon chrome resistor pattern 6.

シリコン酸化膜凸部7にはさまれた部分および電極端部
とが凹部を形成する。このような形状の製作は、例えば
第2図(b)に示すようにシリコン基板8上に熱酸化に
よりシリコン酸化膜9を厚さ2JLm形成後、厚さ27
pmのポリシリコン10をリアクティブイオンエツチン
グ法によりパターニングして、熱酸化を実施する事によ
り厚さ0.IILmのシリコン酸化膜11を形成し、そ
の後厚さ0.3gmのシリコンクロム膜12をパターニ
ングする事により実現できる。
The portion sandwiched between the silicon oxide film convex portions 7 and the electrode end portion form a recess. To manufacture such a shape, for example, as shown in FIG. 2(b), after forming a silicon oxide film 9 with a thickness of 2JLm on a silicon substrate 8 by thermal oxidation, a silicon oxide film 9 with a thickness of 27Lm is formed.
pm polysilicon 10 is patterned using a reactive ion etching method and thermally oxidized to a thickness of 0.50 nm. This can be achieved by forming a silicon oxide film 11 of IILm and then patterning a silicon chrome film 12 with a thickness of 0.3 gm.

本実施例の場合も、第1実施例と同様にシリコンクロム
抵抗パターン6の投影平面上のパターンの長さを141
Lmとすると、第2図(b)に示すようにシリコン酸化
膜凸部7を3箇所形成することにより実効長は257h
mとなり平坦な絶縁膜上に形成された抵抗パターンの約
1.8倍の長さとなる。したがって、同一面積で従来技
術の1.8倍の抵抗が実現できる。
In the case of this embodiment as well, the length of the silicon chrome resistor pattern 6 on the projection plane is set to 141 as in the first embodiment.
Assuming Lm, the effective length is 257 h by forming the silicon oxide film convex portions 7 at three locations as shown in FIG. 2(b).
m, which is about 1.8 times the length of the resistance pattern formed on the flat insulating film. Therefore, a resistance 1.8 times that of the conventional technology can be achieved with the same area.

なお、第1および第2の実施例ではシリコン基板上での
例について述べたが、これに限定するものではなくガリ
ウム・ヒ素基板や各種絶縁基板でも実現可能であり、薄
膜抵抗・絶縁膜についても栓々の材料について本発明の
要旨を逸脱しない範囲で適用可部である。
In the first and second embodiments, examples on silicon substrates have been described, but the invention is not limited to this, and it can also be realized on gallium arsenide substrates and various insulating substrates, and thin film resistors and insulating films can also be used. The materials of the plugs are applicable within the scope of the invention.

〔発明の効果〕〔Effect of the invention〕

以上、説明したように、本発明ではF!膜抵抗素子の下
地絶縁膜に、凹凸部を設け、抵抗パターンの経路が凹部
内にも形成されるようにすることで、経路の実効長を増
大させる。これによって、基板面積として少ない面積で
高抵抗を実現することができるので、半導体集積回路等
における集積度向上に多大な効果を発揮する。
As explained above, in the present invention, F! The effective length of the path is increased by providing an uneven portion in the base insulating film of the film resistance element so that the path of the resistance pattern is formed also within the recess. As a result, high resistance can be achieved with a small substrate area, which is highly effective in improving the degree of integration in semiconductor integrated circuits and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1実施例の平面パターン図および断
面図、第2図は第2実施例の平面パターン図および断面
図である。 l・・・ポリシリコン抵抗パターン、 2・・・(シリコン窒化膜)凹部、 5・・・ポリシリコン膜、 6・・・シリコンクロム抵抗パターン、7・・・シリコ
ン酸化膜凸部、 10・・・ポリシリコン、 11・・・シリコン酸化膜。 特許出願人  日本電気株式会社 代理人 弁理士   内   原    晋第1図 第2図
FIG. 1 is a plan pattern diagram and a sectional view of a first embodiment of the present invention, and FIG. 2 is a plan pattern diagram and a sectional diagram of a second embodiment. l...Polysilicon resistance pattern, 2...(silicon nitride film) recess, 5...polysilicon film, 6...silicon chrome resistance pattern, 7...silicon oxide film protrusion, 10...・Polysilicon, 11...Silicon oxide film. Patent applicant: NEC Corporation Representative: Susumu Uchihara, patent attorney Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims]  絶縁膜上に形成した線状の薄膜抵抗素子において、下
地絶縁膜が経路上に凹凸部を有し、該凹部の対向する側
面に形成した薄膜が互いに接触しないように、凹部径・
膜厚を設定してなることを特徴とする薄膜抵抗素子。
In a linear thin film resistance element formed on an insulating film, the underlying insulating film has an uneven portion on the path, and the diameter of the recess is adjusted so that the thin films formed on opposite sides of the recess do not come into contact with each other.
A thin film resistance element characterized by having a set film thickness.
JP63116102A 1988-05-12 1988-05-12 Thin film resistance element Pending JPH01286355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63116102A JPH01286355A (en) 1988-05-12 1988-05-12 Thin film resistance element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63116102A JPH01286355A (en) 1988-05-12 1988-05-12 Thin film resistance element

Publications (1)

Publication Number Publication Date
JPH01286355A true JPH01286355A (en) 1989-11-17

Family

ID=14678748

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63116102A Pending JPH01286355A (en) 1988-05-12 1988-05-12 Thin film resistance element

Country Status (1)

Country Link
JP (1) JPH01286355A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0818011A (en) * 1994-04-25 1996-01-19 Seiko Instr Inc Semiconductor device and its production
JP2005303051A (en) * 2004-04-13 2005-10-27 Ricoh Co Ltd Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0818011A (en) * 1994-04-25 1996-01-19 Seiko Instr Inc Semiconductor device and its production
JP2005303051A (en) * 2004-04-13 2005-10-27 Ricoh Co Ltd Semiconductor device and manufacturing method thereof

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