JPH0129057B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a planar semiconductor device, and particularly to a planar semiconductor device with a small chip area and high breakdown voltage.

[Technical Background of the Invention] As is well known, the planar structure, which is the basic structure of IC, is difficult to bond in the bonding process.
Since it is protected by a SiO ₂ film, it has the excellent advantage of stabilizing the junction, but it also has the disadvantage that it is difficult to achieve a high breakdown voltage because electric field concentration occurs at the curved part of the junction and on the junction surface. There is.

Therefore, in order to correct this shortcoming, improved planar technology that incorporates a guard ring structure and improved planar technology that uses low melting point glass as part of the guard ring structure have recently been developed, but these improved planar technologies However, these known techniques have been unable to manufacture elements with higher breakdown voltages at lower cost.

[Problems with the Background Art] As is already well known, the guard ring structure is a conventional planar structure in which a ring-shaped joint that surrounds the junction of the elements is added to the surface of the junction of the elements. This device structure alleviates the electric field at the curved portion of the device junction, thereby improving the withstand voltage of the conventional planar structure. FIG. 1 is a cross-sectional view of a planar transistor constructed using this guard ring structure. As shown in the figure, a semiconductor substrate 1 includes an N ⁺ type collector region 2, an N ^- type high resistance region 3 formed by vapor phase growth, a P ⁺ type base region 4, and an N ⁺ type emitter region. 5 is formed, and two ring-shaped P ⁺ type guard ring regions 6 and 7 are formed in the N ^- type region 3 outside the base region 4 to annularly surround the base region 4, and further outside. An annular EPR region 8 (equipotential region; Egui-P ₀ -tential
Ring) is formed. The surface of the semiconductor substrate 1 is covered with a SiO ₂ thermal oxide film 9, and the surface of the semiconductor substrate 1 is covered with a SiO 2 thermal oxide film 9.
Above the SiO ₂ film 9 and each electrode 10 to 12 is a PSG film 1.
3 (phosphorus silicide glass film).

According to the improved planar technology that incorporates the guard ring structure into the planar structure, the electric field concentration at the curved portion is alleviated by the guard ring junction, so the withstand voltage is higher than that of the conventional planar element (without a guard ring). However, the semiconductor device shown in FIG. 1 has the following problems, and therefore, with such a device structure, it is difficult to economically realize a smaller device with a higher breakdown voltage. I couldn't do it.

In other words, in the semiconductor device shown in Figure 1, the concentration of electric field at the curvature at the bottom of the junction is alleviated, but since the substrate surface is covered with a SiO ₂ film, the leakage electric field from the substrate surface is effectively shielded. It was not possible to achieve a high breakdown voltage with the structure shown in FIG. 1 because it was not possible to reduce the interfacial charge density to a sufficiently small value.

On the other hand, the effect of mitigating the electric field in a guard ring structure increases as the number of guard rings increases, so if a device is designed to have a high withstand voltage, it will inevitably require a large number of guard rings with optimized spacing. However, the more guard rings there are, the larger the chip area becomes, which not only significantly increases the production cost of ICs, etc., but also causes problems such as a decrease in yield due to the complexity of the manufacturing process. .

Generally, the breakdown voltage of a device junction is determined by the specific resistance of the substrate, I
Determined by layer width, base bonding depth, etc.
In the case of an element with a guard ring structure, the number of guard rings and the interval between guard rings are also determining factors for the junction breakdown voltage. Therefore, in order to increase the junction breakdown voltage of a device, it is generally necessary to increase the resistivity of the substrate, the base junction depth, and the width of the I layer. For example, in the case of a switching transistor, Increasing the specific resistance of the substrate or increasing the width of the I layer is undesirable because it results in a decrease in reverse breakdown strength, switching characteristics, and saturation characteristics. Therefore, conventionally, when designing a high-voltage switching transistor, a guard ring structure was adopted, the number of guard rings was increased, and the guard ring spacing was optimized. If a high breakdown voltage is achieved by increasing the number of guard rings, an increase in cost is unavoidable due to an increase in chip area and a decrease in yield, as described above. The problems with the guard ring structure will be reflected in the product price and product quality.

Next, as a modification of the guard ring structure, an improved planar technology in which a ring of PbO-based low melting point glass is formed on the guard ring region is also known, and a planar transistor formed by this improved planar technology Shown in Figure 2.

In FIG. 2, parts labeled with the same reference numerals as in FIG. 1 indicate the same parts as the elements in FIG.
In the device shown in FIG. 2, a guard ring region 6 is formed to surround the bottom of the base region 4 and have the same depth as the bottom of the base region 4, and also to surround the emitter region 5 to the same depth as the bottom of the emitter region 5. A ring-shaped low melting point glass region 15 is formed at the same depth as the SiO ₂ thermal oxide film 9 . Further, a channel cut region having the same depth as the emitter region is formed on the outer periphery of the low melting point glass region 15.

According to the improved planar structure as shown in FIG.
It is difficult to accurately control the glass film thickness in the deposition process in step 5, and therefore the glass film thickness varies from element to element within the same chip, making it difficult to guarantee uniform quality and characteristics. In addition to its drawbacks, there is a large difference in the thermal expansion coefficients of Si and glass, which are the constituent elements of the semiconductor substrate, so cracks tend to occur in the glass after the glass deposition process is completed, resulting in very low yields. It has a serious drawback.

OBJECTS OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device with a further improved planar structure that does not have the drawbacks and problems of the known improved planar structures mentioned above.

SUMMARY OF THE INVENTION The present invention is the result of consideration of problems in improved planar structures and device operation. The feature of this invention is that polysilicon carbide with a dielectric constant of 7 containing oxygen, nitrogen, or halogen is used on the surface of a semiconductor substrate on which an element having a means for changing the shape of a space charge layer such as a guard ring is formed.
In addition to having the above semi-insulating first film,
A second insulating film having a dielectric constant of 7 or more is provided on the first film. By employing such a structure, the electric field within the semiconductor substrate can be effectively dispersed in the film, thereby increasing the control margin for the interfacial charge density of the semiconductor substrate. If the control margin of the interfacial charge density of the substrate can be increased, it is possible to design a planar semiconductor device with a small area while obtaining the same junction breakdown voltage without impairing characteristics such as switching speed, saturation characteristics, and reverse breakdown voltage. . It also solves the manufacturing process problems of improved planar technology using low-melting glass.

Examples of the semi-insulating film used in the present invention include polysilicon carbide having an intermediate composition between polysilicon carbide SiC and SiO ₂ , that is, containing oxygen as an impurity, and polysilicon carbide containing nitrogen or halogen. This semi-insulating film has a resistance value of about 10 ⁷ to ^{10 10} Ωcm, and often has a dielectric constant of 7 or more. This is an intermediate composition between polysilicon and silicon oxide,
That is, it corresponds to semi-insulating polycrystalline silicon having a composition of Si _x O _Y (y/x<2).

As the second film, it is preferable to use an insulating film having a dielectric constant of 7 or more, particularly an insulating film with a high ability to prevent external contamination. As such an insulating film
Al ₂ O ₃ , Si ₃ N ₄ , Nb ₂ O ₃ , HfO ₂ , Ta ₂ O ₃ , TiO ₂ ,
Examples include low melting point glass (ZnO-based or PbO-based).

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIGS. 3 to 4.

FIG. 3 is a cross-sectional view of a semiconductor device (IC-embedded transistor) having an improved planar structure according to the present invention. The same parts of the semiconductor device shown in the figure are shown.

In FIG. 3, 16 is a first film covering the entire surface of the semiconductor substrate 1. In FIG. This first film 16
is a semi-insulating film with a dielectric constant of 7 or more, and in this embodiment, for example, polysilicon carbide (poli-silicon carbide) is used.
It is composed of SiC). The second film 17 coated on the first film 16 is composed of an insulating film having a dielectric constant of 7 or more and a large ability to inhibit the diffusion of contaminant ion species. In this embodiment, the second film 17 is
It is composed of Al ₂ O ₃ . In addition, electrodes 10 to 12
A Si ₃ N ₄ film 18 is provided as a wiring protection film covering the wiring.

In a semiconductor device with such a structure, the junction surface is double coated with a semi-insulating film with a dielectric constant of 7 or more and a low interfacial charge density, which effectively shields leakage electric fields. In addition, since the electric field generated within the semiconductor substrate can be shared between the first film and the second film, the concentration of the electric field on the surface of the junction can be effectively alleviated.

Figure 4 shows the relationship between the maximum electric field strength E generated at the junction of the semiconductor device in Figure 3 and the dielectric constant _{ε s} of the two-layer films 16 and 17 covering the surface of the semiconductor substrate. It is something. The maximum electric field strength E is at the junction
This is the value when 1800V is applied, and the base depth
50μm, I layer width 110μm, substrate concentration 8×10 ¹³ cm ^-3 ,
There are two guard rings with a spacing of 32 μm, and the critical breakdown electric field strength in this substrate is approximately 2.5×10 ⁵ V/cm. It can be seen from this figure that if the dielectric constant is 7 or more, the electric field is relaxed.

The semiconductor device shown in FIG. 3 was manufactured through the following steps.

First, SiO ₂ is deposited on the surface of the N ^- type high resistance region 3 of the semiconductor substrate 1 with a specific resistance of 50 to 65 Ωcm and an I layer width of 150 μm.
After forming the film, the SiO ₂ film is selectively etched to form three annular openings, and P-type impurities are diffused into the substrate surface exposed within the openings to a depth of approximately
A base region 4 of 30 μm and two guard ring regions 6 and 7 were formed.

Next, in a similar process, N-type impurities are diffused into predetermined locations on the substrate surface to form emitter regions 5 and EPR regions 8.
and form.

After forming a predetermined region on the substrate surface in this manner, the SiO ₂ film was peeled off from the entire surface of the substrate, and then a first film 16 and a second film 17 were formed as described below.

First, silicon carbide (SiC) containing about 20 atomic percent oxygen and having a dielectric constant of 7 or more is made by performing a plasma CVD method at 600°C using a mixed gas consisting of SiH ₄ , N ₂ O, and CH ₄ as a reaction gas.
It was deposited on the substrate surface to a thickness of 1.0 μm, and this was used as the first film 16.

Next, by performing a plasma CVP method at 600° C. using a mixed gas consisting of AlCl ₃ , CO ₂ , and H ₂ as a reaction gas, a second film 17 made of alumina having a dielectric constant of 8 is deposited to a thickness of about 1000 Å. One film 16 was coated on top of the other.

Next, after selectively etching the first and second films 16 and 17, an Al film as an electrode material was deposited. Then, the Al film was selectively etched to complete the electrodes 10 to 12 and device wiring, and finally, a Si ₃ N ₄ film 18 was deposited on the entire surface as a wiring protection film to complete the device formation.

When V _CBO was measured for the semiconductor device shown in Figure 3 with three guard rings, a value of about 1800V was obtained. This was achieved under the same substrate conditions as for the mesa-type device (substrate resistivity 50-65 Ωcm, I layer width 110 μm), but this cannot be achieved with a device with a SiO ₂ planar structure as shown in Figure 1. This is an impossible value.

Incidentally, when forming an element with a SiO ₂ planar structure, in order to achieve the same breakdown voltage as above with the same three guard rings, the I layer width must be 130 μm or more and the interfacial charge density must be 5×10 ¹⁰ /cm ² However, it is not preferable to make the I layer width more than 130 μm from the viewpoint of device switching speed, reverse breakdown strength, saturation characteristics, etc., and it is not preferable to make the interfacial charge density less than the above value. This is almost impossible with current manufacturing technology. On the other hand, in the semiconductor device according to the present invention, it is possible to increase the breakdown voltage without increasing the resistivity of the substrate, the width of the I layer, or the number of guard rings, and it is possible to realize a small element with high breakdown voltage despite the small number of guard rings. be able to. Furthermore, since the first film 16 and the second film 17 only need to be deposited on the entire surface of the semiconductor substrate, it is less difficult than forming the low melting point glass region of the semiconductor device shown in FIG. Since it is simpler than the manufacturing method, the yield is improved and the manufacturing cost is reduced.

[Effects of the Invention] As is clear from the above explanation, according to the present invention, () the number of guard rings is small but the voltage resistance is high, () the chip area is small despite the high voltage resistance, and () the switching speed is low. , high voltage resistance can be achieved without deteriorating saturation characteristics, reverse withstand capacity, etc., and () manufacturing technology is easier than conventional planar structures made of low-melting-point glass, and higher yields can be obtained. A planar semiconductor device is provided.

[Brief explanation of drawings]

1 is a cross-sectional view of a conventionally known planar semiconductor device with a guard ring structure, FIG. 2 is a cross-sectional view of a known improved planar semiconductor device, FIG. 3 is a cross-sectional view of a semiconductor device of the present invention, and FIG. The figure shows the relationship between the junction electric field strength and the dielectric constant of the film in the semiconductor device of FIG. 3. 1...Semiconductor substrate, 2...Collector region, 3...
...High resistance region, 4... Base region, 5... Emitter region, 6, 7... Guard ring region, 8...
EPR region, 9...SiO ₂ film, 10-12... electrode,
13...PSG film, 14...Channel cut region, 15...Low melting point glass region, 16...First film, 17...Second film, 18...Si ₃ N ₄ film.

Claims (1)

[Claims] 1. Having a semi-insulating first film of polysilicon carbide containing oxygen, nitrogen or halogen with a dielectric constant of 7 or more on the surface of a semiconductor substrate on which an element having means for changing the shape of a space charge layer is formed; A planar semiconductor device, comprising an insulating second film having a dielectric constant of 7 or more on the first film.