JPH01291312A - Memory device - Google Patents

Abstract

PURPOSE:To identify turn-on of the power source, and also, to initialize the memory device by resetting a flip-flop circuit by setting the flip-flop circuit so that correct write cannot be executed. CONSTITUTION:When the power source of a computer is turned on, a flip-flop circuit 6a of a power source turn-on discriminating circuit 6 is set by an L level of a reset signal, an OR circuit 6b goes to an inhibition gate, and write and read-out signals of a memory cell 1a are not outputted from an input circuit 5. Accordingly, correct read-out and write of the memory cell 1a are not executed, turn-on of the power source is decided by the computer, and a clear signal is generated. By its clear signal, the flip-flop circuit 6a is reset, a gate of the OR circuit 6b is opened, and a -CS (chip select) signal is inputted to the input circuit 5. In such a way, turn-on of the power source is identified automatically, and after its power source has been turned on, the memory can be initialized.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a memory device for a computer, and more specifically, to enable identification of power-on of the computer, and initialize (clear) the contents of the memory after identification. The present invention relates to a memory device equipped with a hardware circuit that enables the following.

[Conventional example] Some computers have a memory backup function, but this memory (RAM) is backed up.
The contents of will be a random value when the power is turned on during the manufacturing process. The only way to identify whether the content is random data is to rely on an external circuit. In particular, when adjusting the manufacturing process, it is necessary to identify whether the contents of the memory are random data when the power is turned on, and it is also necessary to initialize the memory. This initialization can be done, for example, by setting all of the memory to "0" under the control of the computer.
This is done by software in ALL CLEAR mode (program) that writes the .

[Problems to be Solved by the Invention] By the way, the all-clear mode is software, and moreover, it is necessary to issue a predetermined instruction to the computer. In other words, after turning on the computer,
The above instructions must be given each time based on instructions from the person handling the product. Also, in the above case, it is simply clearing the memory, it is not possible to identify whether the contents of that memory are random data, and even though the memory has already been initialized, it cannot be initialized again. This resulted in lower work efficiency in the manufacturing process.

The present invention has been made in view of the above problems, and its purpose is to provide a memory device that can automatically identify when power is turned on and initialize the memory after power is turned on. be.

Means for Solving Problem C11l1] In order to achieve the above object, the present invention provides a memory device that is connected to an address bus and a data bus of a computer, and in which data is read and written in accordance with instructions from the computer. comprising a flip-flop circuit that is set by a reset signal generated when the computer is powered on, and a gate circuit that inhibits a chip select signal output from the computer at the circuits 1 to 1 of the flip-flop circuit, The set of the flip-flop circuit prevents correct writing to the memory device, makes it possible to identify when the power is turned on, and resets the flip-flop circuit, making it possible to initialize the memory device. It is something.

[Function] With the above configuration, the flip-flop circuit is set by a reset signal generated when the power is turned on. Then, the gate circuit is set as a prohibited gate, and chip selection of the memory device is not performed. That is,
Since the CPU cannot correctly write to the memory device, it is possible to identify when the power is turned on. After identifying this power-on, the CPU resets the flip-flop circuit and enables the memory device to be initialized. Thus, when power is turned on, the power-up is identified and the memory device is automatically initialized after this identification.

[Example] Embodiments of the present invention will be described below based on the drawings.

In FIG. 1, an address bus 3 of a computer is connected to a memory cell 1a of a memory section 1 via an address buffer section 2. As shown in FIG. Further, a data bus 4 is connected to this memory cell 1a via a bidirectional buffer section 1b.

On the other hand, when the computer is powered on, a memory write (W100) signal and a read (6) signal output from the computer are input to the input circuit 5. Also, the chip select (i
) signal is input to the power-on identification section 6. The power-on identification unit 6 includes a flip-flop circuit 6a that is set by the reset signal obtained when the power is turned on, and a negative logic OR circuit 6b that closes the gate of the lever signal by the set of flip-flop circuits 6a. is provided.

The d] signal that has passed through the OR circuit 6b is input to the input circuit 5, and is used as a read signal and a write signal for the memory cell 1a by the W1 signal and the 61 signal. moreover,
If the computer cannot write to or read from the memory cell 1a at the timing of the 61 signal, a clear signal for resetting the flip-flop circuit 6a is output.

Note that the bidirectional buffer section 2b is provided with buffer circuits 1b□ corresponding to the number of bits of the data bus 4, as in the conventional case.

Next, the operation of the memory device having the above configuration will be explained based on the time chart of FIG. 2.

First, when the computer is turned on, the power supply voltage V
cc rises, and a reset signal and a clock signal are generated (see FIGS. 2(a) and 2(b)). It is assumed that after the reset signal becomes H level, the computer accesses the memory cell 1a, that is, outputs the C100 signal, W1 signal, 6000 signal, etc.

At this time, the flip occurs at the L level of the reset signal.
Since the flop circuit 6a is set and the OR circuit (gate circuit) 6b is a prohibited gate, the input circuit 5 has 61
No signal is input from the input circuit 5 to the memory cell 1.
The write and read signals for a are not output. Then,
Correct reading and writing of the memory cell 1a is not executed, and as shown in FIG. 2(c), the computer determines that the power is turned on and generates a clear signal (L level signal) with a predetermined pulse width. be done. The clear signal resets the flip-flop circuit 6a and opens the gate of the OR circuit 6b, so that the input circuit 5 receives the d] signal. The UI multiplied signal and the WE multiplied signal cause writing into the memory cell 1a, and the ] signal and the b100 signal cause writing into the memory cell 1a.

In this manner, in the above-mentioned memory device, when the power is turned on, correct writing and reading of the memory cell 1a is disabled, and this can be canceled by a clear signal from the computer side. Therefore, if the computer cannot write or read correctly, it can identify that the power has been turned on, and after confirming that the power has been turned on, it generates a clear signal and initializes the memory cell 1a. can be executed.

[Effects of the Invention] As explained above, according to the memory device of the present invention,
A flip-flop circuit that is set by a reset signal generated when the power is turned on, and a negative logic OR circuit that prohibits the chip select signal from the computer in this set, and the flip-flop circuit is set. In some cases, the memory device is prevented from being written correctly, so that the computer can identify that the power has been turned on by not being able to write correctly. In addition, after the computer identifies whether the power has been turned on, a clear signal is generated to reset the flip-flop circuit, so the gate of the OR circuit is opened and the memory can be written and read correctly. , and the memory can be initialized.

[Brief explanation of the drawing]

FIG. 1 is a schematic circuit block diagram of a memory device showing an embodiment of the present invention, and FIG. 2 is a time chart diagram explaining the operation of the memory device. In the figure, 1 is a memory section, 1a is a memory cell, 1b is a bidirectional buffer circuit, 2 is an address buffer section, 3 is an address bus, 4 is a data bus, 5 is an input circuit, 6 is a power-on identification circuit, 6a is a flip-flop circuit, and 6b is an OR circuit (gate circuit). Patent applicant: Fujitsu General Co., Ltd. Patent attorney: Takuya Ohara

Claims (1)

[Claims] (1) A flip-flop that is connected to a computer's address bus and data bus and is set by a reset signal generated when the computer is powered on, in a memory device in which data is read and written according to instructions from the computer. circuit, and a gate circuit for inhibiting a chip select signal outputted from the computer by the set of flip-flop circuits, the set of flip-flop circuits inhibits writing to the memory, and the power is turned on. 1. A memory device characterized in that the flip-flop circuit is reset after a predetermined time to enable initialization.