JPH01291355A - Data transfer control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention [Summary] Commonly accessed by multiple host devices The present invention relates to a data transfer control circuit that controls data transfer between a higher-level device and a lower-level device using an economical hardware configuration in an adapter for a lower-level device. A data transfer control circuit equipped with a buffer memory that stores data blocks to be transferred between a higher-level device and a lower-level device, and which alternately switches addresses specifying first and second storage areas on the buffer memory. An address sending unit is provided, which creates an address that causes the lower device to write/read a predetermined amount of data blocks based on the first address of the lower device sent by the higher device, and sends the created address to the first address. The first or second storage area is sequentially and alternately selected and stored, and the address at which the next predetermined amount of data block is written/read from the first or second storage area is sequentially selected from the first or second storage area. An error occurs in the lower-level device by repeating the operation of reading and sending it to the lower-level device, and then the upper-level device transfers the data block accumulated in the buffer memory to the lower-level device, or transfers the data block accumulated by the lower-level device to the higher-level device. In this case, the address in which the error occurred, remaining in the first or second storage area, is transmitted again to recover.

[Industrial application field]

The present invention relates to an adapter for a lower-level device that is commonly accessed by a plurality of higher-level devices, and particularly to a data transfer control circuit that controls data transfer between a higher-level device and a lower-level device using an economical hardware configuration.

In recent years, as the configurations of information processing devices have become more complex, common memories have come into use that store data commonly used by a plurality of central processing units.

Such a common memory is provided with a common memory adapter provided with a data transfer control circuit for controlling data transfer between the common memory and the central processing unit, and data transfer is controlled by this common memory adapter.

By the way, this data transfer control circuit needs to be economical.

[Conventional technology]

FIG. 3 is a block diagram illustrating the conventional technology.

FIG. 3(a) is a diagram illustrating the system configuration, in which ``■'' is a central processing unit, 2 is a common memory adapter, and 3 is a common memory. The central processing unit 1 sends the address of the common memory 3 to the common memory adapter 2 via the address bus 4,
Data is sent to the common memory adapter 2 via the data bus 5.

The common memory adapter 2 uses an internal data transfer control circuit to transfer the address created based on the address sent by the central processing unit 1 and the data accumulated in the buffer memory to the common memory 3 via the lotus 6. Write in 3.

Furthermore, based on the address sent by the central processing unit 1 via the address bus 4, the data read from the common memory 3 by the address sent by the data transfer control circuit of the common memory adapter 2 is transferred to the common memory adapter via the lotus 6. 2
After being stored in the buffer memory, the data is controlled by the data transfer control circuit and transferred to the central processing unit 1 via the lotus 4.

FIG. 3(b) shows an example of a data transfer control circuit.

For example, a 3-hide address sent by the central processing unit 1 is input to the multiplexer 7 via the address bus 4 . This address is the starting address of common memory 3,
The signal is stored in register 8 via multiplexer 7.

Also 1. For example, 4-byte data is input via the data bus 5. At this time, the start address A of the sofa memory 11 is predetermined via the multiplexer 13 in the register 14.
stored in the multiplexer.

16 to the write address terminal W of the buffer memory 11
Enter. Therefore, 4 bytes of data are written into the buffer memory 11.

The adder circuit 15 adds 1° to the address of the register 14, and the address of the register 14 is updated via the multiplexer 13. This incremented address is input to the write address terminal W of the buffer memory 11 via the multiplexer 16. Therefore, the next 4 hides of data are written into the buffer memory 11.

In this way, for example, a data block of 32 hides is written into the buffer memory 11.

When a data block of 32 hides is written to the buffer memory 11, the multiplexer 12 sends the address of the register 8 to the lotus 6, and at the same time sends a command C indicating the data sending direction to the common memory 3, the amount of data to be transferred, etc. do.

After this address has been sent, the multiplexer 16 does not read the data in the buffer memory 11 but sends the address to the read address terminal R of the buffer memory 11. That is,
In the same manner as described above, the address of the register 14 to which the starting address A of the buffer memory 11 has been set is sent.

The buffer memory 11 reads 4 bytes of data using these 7 addresses, and then, each time the address sent out by the multiplexer 16 is incremented, it reads out 4 bytes of data and sends it to the multiplexer 12. The data of every 4 bytes read from is sent to the lotus 6 sequentially.

The address stored in the register 8 is sent to the register 9 and recorded 41, and the adder circuit 10 adds a value P, which is the address for writing the next data block (32 bytes) to the common memory 3, and the multiplexer 7 and is written to register 8.

When all the data in the buffer memory 11 is sent to the bus 6, the address indicating the start address A of the buffer memory 11 is input from the multiplexer 16 to the write address terminal W of the buffer memory 11, and is sent to the data bus 5 in the same manner as described above. data is written to the sofa memory 11.

When the data blocks of 32 by 1- are all sent from the buffer memory 11 to the bus 6 as described above, the multiplexer 12 adds the value P of the register 8 and sends the updated address and command C to the bus 6. Then, when the next data block of 32 hides is written to the sofa memory 11, this next data block is written to 4 blocks in the same way as above.
Send each Hyde to Hass 6.

In this way, the above operation is repeated until there are no more transfer data blocks to be sent to the data bus 5.

If an error occurs in the common memory 3, the multiplexer 7 transfers the address stored in the register 9 to the register 8, and returns it to the address before it was updated by adding the value P. Therefore, the multiplexer 12 The address of the data block where the error occurred is sent to the lotus 6. Then, recovery is performed by retransmitting the data block in the buffer memory 11.

When reading data from common memory 3, address bus 4
The address sent from the central processing unit 1 is stored in the register 8 in the same manner as described above, and the multiplexer 12 sends this address to the lotus 6. Then, the 4-byte data read at this address is written to the buffer memory 11 via the multiplexer 12 by inputting the address stored in the register 14 in the same manner as described above to the write address terminal W of the buffer memory 11. be included.

When 32 bytes of data are accumulated, the address sent by the register 14 is input to the read address terminal R of the buffer memory 11, so that every 4 bytes are sent to the data bus 5 and transferred to the central processing unit 1. be done.

Note that switching signals for the multiplexers 1.12 and 13.16, write/read timing signals for the registers 8.9.14 and the buffer memory 11, and the like are supplied from a control section of the common memory adapter 2, which is not shown.

[Problem to be solved by the invention]

In the circuit shown in FIG. 3 (bl), registers 8 and 9 are required, and if the address width is 24 pintos, each
Requires 4 flip-flops.

As the address width increases, more flip-flops are required. Further, since the multiplexer 12 is provided to separate data and addresses, a very large amount of hardware is required, and control of the registers 8 and 9 is also complicated, making it uneconomical.

In view of such problems, the present invention provides a buffer memory 11.
The purpose of this invention is to provide a data transfer control circuit that is easy to control and economical by setting up a storage area to replace registers 8 and 9 and saving the need for registers 8 and 9 and the multiplexer 12 that separates data and addresses. .

[Failure to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

The same reference numerals as in FIG. 3 indicate the same functions. The address sending means 28 sends the address of the storage area 26 to the write address terminal W of the buffer memory 11 via the multiplexer 24. An address indicating the start address of a lower-order device is input from the higher-order device to the address bus 4. Since the multiplexer 17 sends the start address of the address bus 4 to the buffer memory 11, the start address of this lower device is stored in the storage area 26.

Subsequently, a data block is input to the data bus 5 from the host device. At this time, as explained with reference to FIG. 3(b), the start address A of the buffer memory 11 is set in the register 14, and inputted to the write address terminal W of the buffer memory 11 via the multiplexers 16 and 24. Therefore, the address which is incremented every 4 bytes and set in the register 14 in the same manner as described above is input to the write address terminal W, so that a data block of 32 hides is stored in the buffer memory 11.

When a 32-hide data block is stored in the buffer memory 11, the address of the storage area 26 of the buffer memory 11 sent by the address sending means 28 via the multiplexer 23 is input to the read address terminal R. Therefore, the address of the lower device is sent from the buffer memory 11 to the bus 6, and at the same time this address is input to the adder circuit 10, where the value P explained in FIG. Sent out.

At this time, the address sending means 28 writes i! to the write address terminal W of the buffer memory 11 via the multiplexer 24. The address of the area 27 is sent, and the address to which the value P is added is stored in the storage area 27. Multiplexer 25 also sends command C to bus 6.

Here, the sofa memory 1 set in the register 14 is
The first address A of 1 is input to the read address terminal R of the buffer memory 11 via multiplexers 16 and 23, and a data block is read every 4 bytes from the buffer memory 11 and sent to the bus 6.

If an error occurs in the lower-level device, the address sending means 28 sends the address to the recording area 26 of the buffer memory 11.
In order to send out the address again, the address before the value P is added is sent to the lower device and can be recovered.

When all the data blocks stored in the sofa memory 11 have been transferred, the next data block is written to the buffer memory 11 via the multiplexer 17 in the same manner as described above. When this data block is transferred to a lower device, the address sending means 28 sends out the address of the storage area 27 of the buffer memory 11 via the multiplexer 24, so that the address of the lower device to which the value P has been added is transferred to the bus 6. sent to.

Therefore, the next data block to be transferred is written to the lower device at the address to which the value P is added.

[Effect]

By configuring as described above, the address sending means 28
alternately switches the addresses of the storage areas 26 and 27 of the buffer memory 11, and each time a data block is transferred to the address sent by the higher-order device, the address for sending to the lower-order device is added with the value -14=P;
In order to alternately store the recovery address immediately before the value P is added in the storage areas 26 and 27, the address shown in FIG.
It becomes possible to omit registers 8 and 9 shown in b), and if there is an error in the lower device, it becomes possible to recover from the error by sending a recovery address. .

Since the address to be sent to the lower device is stored in the buffer memory 11, it is possible to transfer the data block using the bus 6 after sending the address to the bus 6. There is no need to switch the lotus 6 by the multiplexer 12 shown in FIG. 3 (bl), and the amount of hardware can be reduced by simple control.

〔Example〕

FIG. 2 is a block diagram of a circuit showing one embodiment of the present invention.

The same reference numerals as in FIG. 3 indicate the same functions. The flip-flop 18 initially sets "1" to the multiplexer 21 under the control of the control unit of the common memory adapter 2 (not shown).
and is sent to NOT circuits 19 and 20, and NOT circuit 2
"0" is sent to the multiplexer 22.The multiplexer 22 is given a fixed value in advance, for example, the upper bit "100", and is sent to the write address terminal W of the buffer memory 11 as an address via the multiplexer 24. For example, "1000" is sent.

The address "1000" of the buffer memory 11 is the address of the storage area 26, and the starting address of the common memory 3 sent by the central processing unit 1 of FIG. It is stored in the storage area 26.

Then, the “1” sent out by the flip-flop 18 is NO.
After passing through the T circuit 19, it becomes aO'', and the flip-flop 18
, the flip-flop 18 sends "0" to the multiplexer 21 and the NOT circuits 19 and 20.

The multiplexer 21 is given a fixed value in advance, for example, the upper bit "100", so when the flip-flop 18 sends out "0", the multiplexer 23
Send “1000” to

A data block sent by central processing unit 1 to data bus 5 is input to buffer memory 11 via multiplexer 17 . As explained in FIG. 3(b), the start address A of the buffer memory 11 set in the register 14 is inputted to the write address terminal W of the buffer memory 11 via the multiplexers 16 and 24. As explained in FIG. 3, since the address added and incremented by the adder circuit 15 is input to the write address terminal W of the sequential sofa memory 11, the data block input from the data bus 5 is input every 4 bytes. The data are sequentially written into the buffer memory 11.

When a 32-byte data block is written to the buffer memory 11, the address “1000” sent to the multiplexer 23 is input to the read address terminal R of the high sofa memory 11 as described above, and the storage area of the buffer memory 11 is The starting address of the common memory 3 shown in FIG. 3 (al) stored in 26 is sent to the bus 6.

The starting address of this common memory 3 is the adder circuit 1.
0, the value P explained in FIG. 3 (bl) is added,
The signal is sent to the buffer memory 11 via the multiplexer 17.

At this time, as mentioned above, since the flip-flop 118 is sending out 0'', the NOT circuit 20 sends out a1'', and the address "1001" is sent from the multiplexer 22 via the multiplexer 24 to the write address of the buffer memory IJ11. Input to terminal W. The address "1001" is the address of the storage ti area 27 of the buffer memory 11, and the address to which the value P has been added by the adder circuit 10 is written.

The 32-byte data block stored in the buffer memory 11 is transmitted from the address set in the register 4 to the read address terminal R of the buffer memory 11 via the multiplexers 16 and 23, as explained in FIG. 3(b). is read out every four hides and sent out to the bus 6, and based on the address that was first read out and sent out from the storage area 26 of the hash sofa memory 11-18=, the data is stored in the common memory 3 shown in FIG. 3 (al). written.

To the left, where all 32-byte data blocks stored in the sofa memory 11 are transferred, as above, the register 14
The starting address A of the buffer memory 11 stored in the buffer memory 11 is input to the write address terminal W of the buffer memory 11 via the multiplexers 16 and 24, and the data block input from the data bus 5 via the multiplexer 17 is transferred to the buffer every 4 hides. Written into memory 11.

Then, the flip-flop 18 has a NOT circuit 19 of “1”.
”, 1” is sent again to NOT circuits 19 and 2.
0 and multiplexer 21.

Therefore, as before, via multiplexers 21 and 23,
The address "1001" is input to the read address terminal R of the buffer memory 11, and the address 4.
! The next address of the common memory 3 written in the eM area 27 ↑a, that is, the address obtained by adding the value P to the top address of the common memory 3, is read out and sent to the lotus 6.

Then, the value P is further added in the adding circuit 10 and sent to the buffer memory 11 via the multiplexer 17.

At this time, the write address terminal W of the buffer memory 11 receives the address '1000' via the multiplexers 22 and 24.
” has been input, the address to which the value P is further added is stored in the storage area 26 of the H7F memory 11.

Here, the address for reading the data block every 4 bytes from the register 14 into the buffer memory 11 is inputted to the read address terminal R of the buffer memory 11 via the multiplexers 16 and 23, and the data block every 4 bytes is is sent to storage area 2 of buffer memory 11 first.
The address to which the value P sent from 7 is added is written into the common memory 3.

If an error occurs in the common memory 3, a control unit (not shown) of the common memory adapter 2 inverts the flip-flop 18 and returns the addresses of the storage areas 26 and 27 of the buffer memory 11 to the previous state. .

Therefore, since the address of the common memory 3 before the value P is added by one is read out, recovery can be performed.

Also, data blocks are transferred from the common memory 3 to the central processing unit 1.
When transferring to the buffer memory 11, do the same as above.
The address stored in the storage area 26 of is sent to the lotus 6, and the address to which the value P is added by the adder circuit 10 is stored in the storage area 27. Then, the data blocks read from the common memory 3 are stored in the register 14 every 4 hides.
When 32 bytes have been accumulated, the address sent from the register 14 is read from the buffer memory 11 every four hides and sent to the data bus 5 via the multiplexer 17.

Then, when 32 hides of data pro-7 are transferred from the buffer memory 11, the address to which the value P is added is read out from the storage area 27 and sent to the path 6, and the address added to the storage area 27 is
The address to which the value P is further added is stored in , and the operation of storing the next data block in the buffer memory 11 is repeated.

〔Effect of the invention〕

As described above, the present invention can provide a data transfer control circuit with a reduced amount of hardware through simple control.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 3 is a block diagram illustrating a conventional technique. In the figure, 1 is a central processing unit, 2 is a common memory adapter, 3 is a common memory, 4 is an address bus, 5 is a data bus, 6 is a hash, 7, 12.13.16.17.21 to 25 are multiplexers, -22=8, 9.14 is outside the register 10.15 is the adder circuit, 11
is a sofa memory, 18 is a flip-flop, 19.2
0 is a NOT circuit, 26.27 is a storage area, and 28 is an atlus sending means.

Claims (1)

[Scope of Claims] A data transfer control circuit comprising a buffer memory (11) that temporarily stores data blocks to be transferred between a higher-level device and a lower-level device, comprising: a first storage area on the buffer memory (11); (26)
and address sending means (28) that alternately switches and sends an address specifying the second storage area (27), and a predetermined amount of data is sent to the lower device based on the start address of the lower device sent by the higher device. An address for writing/reading a data block is created, and the created address is sequentially and alternately selected and stored in the first or second storage area (26) (27) on the buffer memory (11). At the same time, the first address is used to sequentially write/read the next predetermined amount of data block from the first address.
Alternatively, the data block is read from the second storage area (26) (27) and sent to the lower device, and the upper device transfers the data block accumulated in the buffer memory (11) to the lower device, or the lower device transfers the data block stored in the buffer memory (11) to the lower device. 11) is repeated to transfer the data blocks accumulated in the first or second storage area (2) to the higher-level device, and when an error occurs in the lower-level device,
6) A data transfer control circuit characterized in that the address in which the error occurred left in (27) is transmitted again to recover.