JPH01292460A - General purpose parallel interface - Google Patents

Abstract

PURPOSE:To make it possible to connect a device having a different bit wait by providing a general purpose parallel interface with a circuit for switching the bit weight of transfer data between a CPU bus and an interface bus. CONSTITUTION:The device is constituted of a CPU bus A, a CPU 1 connected to the bus A, the general purpose parallel interface 2, and the bit weight switching circuit 5 connected to the interface 2 and an interface bus (IEEE-488 bus) J to receive a bit weight switching signal K through an AND circuit 6. On the other hand, peripheral devices 3, 4 are connected to the bus J. When a switching instruction signal K from the CPU 1 is '1' (effective) and an ATN signal H is '1' (data mode), the switching circuit 5 converts transmitted/received data into data with reverse bit weight by a switching signal L '1' (effective) outputted from the circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a general purpose parallel interface, and more particularly to a general purpose parallel interface for coupling a CPU and various peripheral devices in a computer system.

[Conventional technology]

In computer systems, the general-purpose parallel interface that connects the CPU and various peripheral devices is the IEEE standard.
It is standardized by r IEE Standard.
488-1978'' (hereinafter referred to as IEEE-488 bus). The IEEE-488 bus is a general-purpose parallel interface bus that allows systems to be easily constructed by connecting a plurality of various measuring instruments and peripheral devices in parallel and standardizing remote control and data transfer using commands. I
The EEE-488 bus consists of a total of 16 signal lines: 8 data buses, 3 transfer control buses, and 5 management buses. Data transfer between various devices connected to the bus is performed using three transfer control lines (3-wire handshake method).
. Reliable transfer is possible even between devices with different transfer speeds.

FIG. 2 is a block diagram illustrating the coupling of a computer system and peripheral devices using a conventional general-purpose parallel interface.

The general-purpose parallel interface 2 has talker and listener functions defined by IEEE-488. A talker has the function of sending data onto the IEEE-488 bus J, and a listener has the function of sending data onto the IEEE-488 bus J.
It has the function of importing data on the -488 bus J. Peripheral device 3 connected to IEEE-488 bus J
and 4 have at least one function of a talker and a listener. Although only two peripheral devices are shown in FIG. 2 for convenience, two or more peripheral devices may be present as long as they satisfy the electrical standards of IEEE-488.

Further, at least one of the general-purpose parallel interface and peripheral devices 3 and 4 has a controller function defined by IEEE-488. The controller controls the IEEE-488 bus J, and the talker and listener perform their functions in response to commands sent from the controller.

Data is sent from a talker connected to the IEEE-488 bus J to a listener. That is, when the general-purpose parallel interface 2 functions as a talker, it takes in data from one of the peripheral devices connected to the IEEE-488 bus that functions as a listener.

FIG. 3 is a time chart showing an example of data transfer using a general-purpose parallel interface. The transfer of data and commands of the general-purpose parallel interface will be described below with reference to FIG.

The IEEE-488 bus J operates in a command mode and a data mode. Command mode allows the controller to send IEEE-488
In this mode, commands are sent via bus J to specify talkers/listeners, etc., and the controller converts the attention signal H (hereinafter referred to as ATN signal) of the management bus to logic r□.

It is defined by The data mode is a mode in which the talker sends data to the listener via the IEEE-488 bus J, and the controller sends data to the listener via the management bus AT.
It is defined by setting the N signal H to logic "1". In either mode, the information sending and receiving sides send and receive information via the IEEE-488 bus by performing a three-wire handshake using three transfer control buses.

The transfer control bus has a data valid signal (hereinafter referred to as DAV signal) E and a not ready for data signal.
a signal (hereinafter referred to as NRFD signal) F and not d
ataaccepted signal (hereinafter referred to as NDAC signal) G. A DAV signal allows a talker or controller to send data or commands using IEEE-488
When sending to bus J, set it to logic "0" and
This signal indicates that the data on the 88 bus J is valid. The NRFD signal is a logic ``0'' when the listener is not ready to receive data and a logic ``1'' when it is ready.The NDAC signal is a logic ``0'' when the listener is finished receiving data. It becomes "1" and becomes logic "0" when the reception is not completed.

The device sending the information sends the information to IEEE-
Subsequent to sending on the 488 bus J, the DAV signal is set to logic r□. When the DAV signal becomes logic “0”, the receiving device receives the information from IEEE-488.
It detects that it has been sent onto bus J, and at the same time sets the NRFD signal to logic "0", it starts the operation of taking in information. A device that completes this operation sets its NDAC signal to logic "1". In this case, if there are multiple receiving devices, the NDAC signal is a wired-or combination, so the device that takes in the slowest The NDAC signal becomes logic "1" only after the data acquisition is completed.

The sending device detects that the NDAC signal becomes logic "1", determines that all receiving devices have completed receiving information on the data bus, and changes the DAV signal to logic r1. and stop sending information. Each receiving device detects that the DA■ signal has returned to logic "1" and simultaneously sets the NDAC signal to logic "O" and simultaneously sets the NRFD output to logic "1". Since the NRFD signal line is also wired-OR connected, the NRFD signal becomes logic "0" only when the slowest device makes the NRFD signal logic rQJ. As a result, even if there are a plurality of receiving devices, the handshake operation is performed according to the slowest device among them.

Data is exchanged between the CPUI and the general-purpose parallel interface 2 via the CPU bus A. The general-purpose parallel interface 2 takes in commands and data to be sent to the IEEE-488 bus J from the CPU bus in response to a write command C from the CPU 1, and receives commands and data taken in from the IEEE-488 bus J in response to a read command. Send on CPU bus A.

[Problem to be solved by the invention]

When connecting a CPU and various peripheral devices using the conventional general-purpose parallel interface described above, for example, if some of those devices have a bit weight that is different from the data handled internally by the CPU, In order to make the bit weights the same, it is necessary to change the wiring of the data bus line of the general-purpose parallel interface, or to perform bit weight conversion processing on the CPU side. With the former method, commands cannot be sent and received normally. gone,
The latter method has the disadvantage of slow processing.

An object of the present invention is to provide a general-purpose parallel interface that has a simple circuit configuration, does not reduce processing speed, and can also send and receive commands normally.

[Means to solve the problem]

According to the present invention, a bus is provided between a CPU bus that directly exchanges data with the CPU, and an interface bus that exchanges data with peripheral devices, and exchanges data between the two buses in accordance with instructions from the CPU. In the general-purpose parallel interface, a general-purpose parallel interface is provided that includes a switching circuit that switches the bit weight of data transferred between both buses in accordance with instructions from the CPU.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention.

FIG. 1 shows a computer system and peripheral devices coupled by a general purpose parallel interface in accordance with one embodiment of the present invention. Components having the same reference numbers in FIG. 1 as those in FIG. 2 have the same functions.

In this embodiment, general-purpose parallel interface 2 and I
A bit weight switching circuit 5 is provided between the EEE-488 bus J and the EEE-488 bus J. The switching circuit 5 transmits and receives data with normal bit weight when the switching signal is logic "0", and switches to data with the bit weight reversed when the switching signal is logic "1". The signal is a switching command signal from CPII, which becomes valid when the logic is "1", and is a command to switch to data with the opposite bit weight.
, the switching command signal and the ATN signal H are converted into a switching signal by an AND circuit 6. During data transmission/reception, when the switching command signal K is valid, that is, logic "1", and the ATN signal H is in data mode, that is, logic "1", the AND circuit 6 causes the switching signal to be valid, that is, logic "1". 1'' and the bit weight is switched to data with the opposite bit weight. As a result, even if there is a device among the peripheral devices connected to the IEEE-488 bus J that has a bit weight that is different from the data that the CPU handles internally, the general-purpose parallel interface 2 can transfer the data to the CPU 1 through the switching circuit 5. It can receive data with the same bit weight as the data handled by the device, and send data with the same bit weight as a device with a different bit weight.

Note that the ATN signal H is in command mode, that is, logic r
□, the switching signal is invalid, that is, logic "0"
Since the bit weight is never switched to data with the opposite bit weight, the inconvenience of the bit weight being reversed does not occur when sending and receiving commands.

〔Effect of the invention〕

As explained above, according to the present invention, the command interface is performed normally and the data bit weight is switched only when transmitting/receiving data, thereby connecting to the IEEE-488 bus with a simple circuit configuration. Even if there are devices with different data focus weights among the multiple devices, data can be transmitted and received normally with the devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the connection between a computer and peripheral devices using a general-purpose parallel interface according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the connection between a computer and peripheral devices using a conventional general-purpose parallel interface.
FIG. 3 is a time chart showing control of data transfer by the general-purpose parallel interface. 1: CPU, 2: General-purpose parallel interface, 3.4
2 peripheral devices, 5: bit weight switching circuit, 6: logic circuit. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] A CPU bus that directly exchanges data with the CPU,
A general-purpose parallel interface is provided between a peripheral device and an interface bus for exchanging data, and is configured to exchange data between the two buses in response to an instruction from the CPU. A general-purpose parallel interface characterized by comprising a switching circuit for switching the bit weight of data transferred between the interfaces.