JPH01293039A - Synchronizing system - Google Patents

Abstract

PURPOSE:To cope with a change in the period of the 1st signal without changing hardware by synchronizing the 1st and 2nd signals to each other in such a way that, when the pulse of the 2nd signal precedes that of the 1st signal, the period of the 2nd signal is made longer, and when the pulse of the 2nd signal succeeds that of the 1st signal, the period of the 2nd signal is made shorter. CONSTITUTION:A CPU 1 generates a timer interrupt signal having a period which is nearly equal to that of an external interrupting signal from clocks in a terminal and detects the pulse of the external interrupt signal from a port 3. Then the CPU 1 sets an external interrupt flag and timer interrupt flag into a memory 2 in corresponding to the pulses of the external interrupt signal and timer interrupt signal. The flags are operated by an external interrupt routine program and timer interrupt routine program and the time lag between both pulses is detected by means of a timer control flag. Then the two interrupt signals are made synchronous to each other by adjusting the generating intervals of the timer interrupt signal longer or shorter. Therefore, the necessity of changing the hardware of a timer circuit which arises when the period of the external interrupt signal is changed can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a synchronization method for synchronizing two signals having approximately the same period.

(Prior art) A host station digital exchange that connects multiple terminals via a communication channel sends a pulse (external interrupt signal) with a predetermined period to the terminal through the communication channel, and uses the external interrupt signal to interrupt the terminal. Wake up and carry out commands. FIG. 12 is a block diagram of main parts of a conventional terminal. The timer circuit 12 generates a pulse (interrupt signal) having a period approximately equal to that of the interrupt signal,
When the CPU 13 detects an interrupt from the host station based on an external interrupt signal, it executes the interrupt process. The CPU 13 resets the timer circuit 12 to generate a new timer interrupt signal, synchronizes the phases of the two interrupt signals, detects the interrupt signal selected by the interrupt priority circuit 11, and processes it.

(Problem to be solved by the invention) However, as time passes, the two interrupt signals become out of phase, causing problems such as the execution of commands from the host station at the terminal not being aligned, and when the cycle of the external interrupt signal changes, the timer The problem is that the circuit hardware must be changed.

An object of the present invention is to provide a synchronization method that solves these problems.

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a signal detection means for detecting a first signal manually inputted at a predetermined period, and a signal detecting means for detecting a first signal manually inputted at a predetermined period, generating a second signal with a variable period; detecting pulses of the first signal and the second signal;
It is determined whether the pulse of the second signal precedes or follows the pulse of the first signal, and if the pulse of the second signal precedes or follows the pulse of the first signal, the period of the second signal is lengthened, and if it follows, the period of the second signal is shortened (pulse generation to control). and control means.

(Function) According to the present invention, the first signal detected by the signal detection means
The pulses of the second signal are compared with the pulses of the second signal generated, and if the pulses of the second signal precede the pulses of the first signal, the period of the second signal is lengthened and the pulse of the second signal is If so, the second signal can be varied briefly to synchronize the second signal with the first signal.

(Example) Next, an example of the synchronization method of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram of this embodiment.

The digital converter of the host station connects a plurality of terminals via a communication path 5 and supplies each terminal 4 with an external interrupt signal at a predetermined period. The terminal 4 is provided with a CPU 1, a memory 2, and a port 3 for receiving external interrupt signals. C.P.
tJl generates a timer interrupt signal having almost the same cycle as the external interrupt signal from the terminal's internal clock, and detects the pulse of the external interrupt signal from the boat 3. Then, an external interrupt flag and a timer interrupt flag are set in the memory 2 in response to the pulses of the external interrupt signal and the timer interrupt signal, and these flags are operated by the external interrupt routine program and the timer interrupt routine program, and the pulses of both are set. The two interrupt signals are synchronized by detecting the deviation using a timer control flag and adjusting the generation interval of the timer interrupt signal to be longer or shorter.

Next, external interrupt flag (EXINT-FLAG),
The timer flag (TIMER-Ft, AG), carry flag, and timer control flag (TMCNT) will be explained below using the names ().

T[MER-FLAG is set as the negation of EXINT-FLAG in the timer interrupt routine program and cleared in the external interrupt signal routine program.

EX INT-FLAG is set as the negation of ↑IMER-FLAG in the external interrupt signal routine program, and is set to the carry flag in the timer interrupt routine.

The T gate CNTL-FLAG in FIG.
The carry flag 52, which indicates whether the timer interrupt signal precedes or follows the pulse of the external interrupt signal, and their inverted state, is the shift register 5.
EX I is the carry flag of 1 and is the carry flag 52.
NT-FLAG is set. By shifting to the left, the contents of the carry flag 52 are inserted into the bits of the shift register 51, and the contents are shifted by D and bits.

Next, the positional relationship between the timer control flag, external interrupt signal, and timer interrupt signal, and adjustment of the period of the timer interrupt signal are shown in FIGS. 2(a) to 2(d).

Timer control flag -00, in Figure 2(a),
The timer interrupt signal precedes the external interrupt signal. In this case, the timer interrupt signal interval T' is increased by 2α.

α is the smallest variable unit.

The timer control flag -11 (FIG. 2 Φ) shortens the zero interval T' in which the external interrupt signal precedes the timer interrupt signal by α.

Timer control flag -01, in Figure 2 (C),
The interval between timer interrupt signals gradually becomes longer, indicating that the order of occurrence has been reversed. In this case, the interval T'' is not adjusted, and the timer control flag changes from OO to O1 to 11.
Changes to

Timer control flag = lO1 In Figure 2(d),
The timer interrupt signal generation interval is gradually shortened, and the 0 interval T°, which indicates that the generation order has been reversed, is lengthened by α.

The timer control flag changes from 11 to 10 to 00.

Next, in the flowchart of the timer interrupt routine shown in FIG. 3, when the CPU detects an external interrupt signal, step 2
Read EXINT-FLAG at 0. Next step 21
EXINT-FLAG is set in the carry flag 52. In step 22: TEXINT-FLAG (7) is negated and set to TIMER-FLAG.0 In the next step 23, EXINT-FLAG is cleared. Read TMCNTL in step 24. Next, step 2
At step 5, TMCNTL and the carry flag are moved one pit to the left. At step 26, bits D, ~D of TMCNTL
, to mask. At step 27, TMCNTL=
Check whether it is 00 or not. If so, the process proceeds to step 28 and the timer value (period of the timer interrupt signal) is lengthened. If not, proceed to step 29? ? Check whether ICNTL is 11 or not. If it is 11, proceed to step 30 and shorten the timer value. If not, proceed to step 31;
Check whether TMCNTL is 01 or not. If so, proceed to step 32. In step 32, it is checked whether the timer value is smaller than the maximum value. If so, step 3
Proceed to step 3 and check whether the timer value is smaller than the minimum value. If so, proceed to step 35 and set the timer value to the minimum value. If not, proceed to step 36 and set the timer to a new value. When steps 34 to 36 are completed, the process returns to step 20.

, Next, in the external interrupt routine of FIG.
When I detects an external interrupt signal, T
IMER-FLAG is read, and in the next step 41, TlAER-FLAG is negated, and this is I! XIN
Set T-FLAG to 0. Next, proceed to step 41, clear TIMER-FLAG, and return to step 40.

Next, FIG. 5 shows the relationship between the changes in the flags in the flowcharts of FIGS. 3 and 4 with respect to the external interrupt signal and the timer interrupt signal.

Specific examples of changes in the timer control flag due to the timer interrupt routine (FIG. 3) and external interrupt routine (FIG. 4) will be explained with reference to FIGS. 6 and 7. external interrupt signal t
The period of timer interrupt signal t2 is assumed to be 10 m5, and the period of timer interrupt signal t2 is variable in the range of 9.5 ss to 10.5 ss in a variable unit of 0.1 ss.

In FIG. 6, the timer interrupt signal t is the external interrupt signal 1.
+5ss and the period is initially 10.2ss. The CPUI sets this relationship to timer control flag 0.
It reads at 0 and varies from period 10.2 to 10.5, leading to the process. The timer control flag of process ■ changes from OO to O1 to indicate that the timer interrupt signal is synchronized.
→11, the CPUI reads it and controls the timer interrupt signal t2 to be shorter than 10.4ss in units of O.1ss.

Next, in FIG. 7, the external interrupt signal t1 is ahead of the timer interrupt signal t2, and the difference between them is t1~t! Starts at a certain point when there are 5 meals. The generation interval of timer interrupt signal t2 is set to L by timer control flag 01.
Control is performed to make it shorter than oss.

In process ■, timer control flag is 11 → lO →
OO, and the timer interrupt signal generation interval t8 is controlled to be longer.

Next, synchronization will be explained. A state in which the host and terminal are synchronized is a state in which external interrupts and timer interrupts are always occurring in duplicate. This is shown in FIGS. 8 to 11. When a timer interrupt occurs during an external interrupt as shown in FIG. 8, the timer interrupt routine is made to wait until the external interrupt routine is completed. Therefore, in any combination of the external interrupt and the four timer interrupts shown in FIG. 8, the timer interrupt will occur at the same time as the external interrupt ends, as shown in FIG.

Next, when an external interrupt occurs during a timer interrupt as shown in FIG. 10, the external interrupt routine is made to wait until the timer interrupt routine is completed. Therefore, in any combination of interrupts shown in FIG. 8 and FIG. 10, an external interrupt occurs at the same time as the timer interrupt ends, as shown in FIG. In order to generate such an overlapping relationship, the following conditions are necessary. The total processing time for external interrupts and timer interrupts is greater than the time difference between the occurrences of external interrupts and timer interrupts.In order to satisfy this condition, the following relationship exists.

l) The range in which the timer interrupt generation interval can be varied is sufficiently small compared to the generation interval, and is preferably about ±10 times or less of the minimum variable unit.

2) The timer interrupt generation interval can be increased or decreased by plus or minus, but the variable unit of this plus or minus is sufficiently small, and the minimum variable unit is 1 of the external interrupt generation interval.
The following relationship exists between this variable unit, which is preferably less than /1000, and the timer interrupt and external interrupt.

Difference between timer interrupt and external interrupt ζ 20 x variable unit However, assuming that the variable width mentioned in 1) is the minimum increase/decrease unit of ±10 times or less, the timer interrupt generation interval is 10 of the variable unit width.
This is a case of 00 times or more.

From the above, a variable unit can be obtained by calculating the processing time required for the actual external interrupt and timer interrupt.

That is, variable unit width < 1/20X total processing time 0. For example, in the cases of FIGS. 8 to 10, the total processing time is 120 μsec. Therefore, the variable unit is <1/20×120−6 μsec.

External interrupt generation interval is 1sec, variable unit is 5μ5e
Assuming c (1/2000 of external interrupt generation interval),
Timer interrupt generation interval is 10a+sec±5 x 5
μ5ec=9.075+*sec~10.025m5e
c. The difference between the occurrence of external interrupts and timer interrupts is
The time is approximately 100 μsec or less.

This is smaller than the total of 120 μsec, which is 20 μsec for external interrupts and 100 μsec for timer interrupts, as in the examples shown in FIGS. 8 to 10, so external interrupts and timer interrupts always occur overlappingly. This means that they are in sync.

(Effects of the Invention) According to the present invention, a pulse of a first signal having a predetermined period and a pulse of a second signal whose period is variable are detected, and a pulse of the second signal is detected as a pulse of the first signal. Synchronization can be achieved by controlling the period of the second signal to be long when it is preceding the pulse and short when it is following it. Since this synchronous control is a program control method, even if the period of the first signal is changed, it can be handled without changing the hardware.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a terminal in a digital conversion system to which the synchronization method of the present invention is applied, Figure 2 is a diagram of a control flag indicating the time difference between an external interrupt signal and a timer interrupt signal, and Figure 3 is a diagram of a timer interrupt routine. Flow diagram, 4th
The figure is a flow diagram of the external interrupt routine, and Figure 5 shows the external interrupt signal, timer interrupt signal, and timer interrupt flag.
Relationship diagram between external interrupt flag and timer control flag, Figures 6 and 7 are diagrams of timer control flag inversion process, Figures 8 to 11 are explanatory diagrams of synchronization, Figure 12
The figure shows a block diagram of a conventional example. l...CPU 2...Memory 3...Boat Figure 1 Figure 2 (b) (C) (d) Figure 3 (b) ] Times 4 Figure 9 Figure 10

Claims (1)

[Claims] a signal detection means for detecting a first signal input at a predetermined period; and a signal detection means for generating a second signal whose period is variable before and after the predetermined period of the first signal, and generating a second signal whose period is variable before and after the predetermined period of the first signal. Detects the pulses of the signal, identifies whether the pulses of the second signal precede or follow the pulses of the first signal, and increases the period of the second signal if the pulses precede the pulses of the first signal; This is a synchronous method equipped with short pulse generation control means.