JPH01293664A - Manufacture of mos type field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a MOS type field-effect transistor which has so far never been realized by a method wherein an Si single-crystal film is inserted between a compound semiconductor and an Si thermal oxide film and an interface level is reduced. CONSTITUTION:P-type GaAs 2 is formed on a GaAs substrate 1; after that, an Si single-crystal thin film 3 ls formed. A thermal oxide film 5 is formed on a high-concentration Si single-crystal substrate 4. Both substrates 1, 4 are bonded at a face of the thin film 3 and at a face of the oxide film 5, and are brought into close contact by executing a heat treatment; an interface level between the thin film 3 and the oxide film 5 is reduced. The side of the substrate 4 is polished and etched; a film thickness of an Si single-crystal part is set to 2mum or lower; an Si single-crystal gate electrode 6 is formed by photolithography and etching. A source region 8 and a drain region 9 are formed by making use of the electrode 6 and a CVD-SiO2 film 7 as a mask. By this setup, it is possible to obtain a MOS type field-effect transistor which has never been realized so far.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a compound semiconductor MO5 field effect transistor.

[Summary of the invention]

The present invention uses a compound semiconductor single crystal substrate on which a Si single crystal thin film is formed on the surface, and a compound semiconductor single crystal substrate with a Si single crystal thin film formed on the surface, and
After bonding the thermally oxidized film side and the Si single crystal thin film side of the Si single crystal substrate that have been thermally oxidized to a human degree and integrating them by heat treatment, the thickness of the Si single crystal substrate on the Si single crystal substrate side becomes 2 μm or less. This Si single crystal substrate is etched by photolithography to form a gate electrode in order to use it as a gate electrode. Using the gate electrode as a mask, source and drain regions of the opposite conductivity type to the compound semiconductor substrate are formed to form a MOS. This type of field effect transistor suppresses the interface states between a compound semiconductor and a thermal oxide film.

[Conventional technology]

Conventionally, a compound semiconductor MOS field effect transistor could not be realized because an oxide film with few interface states could not be formed on the compound semiconductor. Therefore, transistors using compound primary conductors are mainly Schottky gate type (MES) field effect transistors, and transistors using heterojunctions such as HEMTs and HBTs have also been developed.

[Problem to be solved by the invention]

Since the MES type field effect transistor uses a Sirotchi barrier, it cannot use a high power supply voltage like a MOS type, and is therefore unsuitable for high integration. Further, the heterojunction type has the disadvantage that the manufacturing process is complicated. An SI single crystal film was inserted to reduce the interface states between the compound semiconductor substrate and the Si thermal oxide film.

[Effect]

In the MOS field effect transistor formed according to the present invention, the interface between the channel region and the gate insulating film is
Since they are a Si single crystal and a thermal oxide film, and a compound semiconductor single crystal and an SI single crystal, the interface states of each can be reduced.

〔Example〕 Embodiments of the present invention will be described below with reference to the drawings.

Compound semiconductors include GaAs', InP, and InAs.
, InSb, etc., but only GaAs will be discussed here, and methods for growing Si single crystal thin films include MBE method,
There are CVD methods, 2MLE methods, etc., and in this case, the CVD method will be explained.

11m (a1 to tel are cross-sectional views showing the order of manufacturing steps of an n-channel enhancement type MOS transistor. FIG. 1(5) shows that after forming a P-type GaAs 2 on a semi-insulating GaAs substrate 1, This shows a Si single crystal thin film 3 formed by the CVD method at 500 DEG C. to 600 DEG C. to a thickness of 100 atoms or less. In FIG. 1, a thermal oxide film 5 is formed on a high concentration Si single crystal substrate 4. Since this thermal oxide film becomes a gate oxide film, its thickness is generally about 1000 Å or less, but it varies depending on the desired darkness value. In Figure 1, the above-mentioned two substrates are bonded on the St single crystal thin film side and the thermal oxide film side while the surfaces are clean, and then heat treated at 600°C to make them adhere tightly and reduce the interface between the Si single crystal thin film and the thermal oxide film. , Fig. 1 fdl is S
i Polishing and etching the single crystal substrate side to reduce the thickness of the St single crystal part to 2 μm or less, and forming a Si single crystal gate electrode by photolithography and etching. Zero-order CVD.
After forming n-type GaAs source/drain regions 8 and 9 by ion implantation using the gate electrode and the CVD SiOz film as a mask, the field insulating film 10 is separated. FIG. 3 is a cross-sectional view of a completed structure in which source and drain electrodes 11 and 12 are formed by depositing contact holes and forming source and drain electrodes 11 and 12.

〔Effect of the invention〕

In the present invention, a Si single crystal film is inserted between the compound semiconductor and the St thermal oxide film to reduce the interface states, so it is possible to fabricate a MOS field effect transistor that could not be realized conventionally. This makes it possible to widen the operating range, which was small in conventional MES type transistors.
It can be applied to both channel and depression types.

[Brief explanation of the drawing]

FIGS. 1+a) to 1(e) are cross-sectional views in the order of manufacturing steps of an embodiment of the present invention. l...Semi-insulating GaAs substrate 2...P-type GaAs 3...Si single crystal film 4...High concentration Si single crystal substrate 5...Thermal oxide film 6...Gate electrode 7...・CvD-8io! Film 8...Source region 9...Drain region 10...Field insulating film 11...Source electrode 12...Drain electrode and above Applicant: Seiko Electronics Industries, Ltd.

Claims (1)

[Claims] A first substrate in which a Si single crystal thin film is provided on the surface of a compound semiconductor single crystal substrate and a second substrate in which a thermal oxide film is provided in the surface of the Si single crystal substrate are brought into close contact with the Si single crystal thin film side and the thermal oxide film side and heat treated. a step of polishing and etching the Si single crystal substrate side of the substrate to reduce the thickness of the Si single crystal substrate to 2 μm or less; and a step of etching the Si single crystal substrate by photolithography to form a gate. An MO method comprising the step of forming a source/drain region by ion implantation using the gate electrode as an electrode and the gate electrode as a mask.
A method for manufacturing an S-type field effect transistor.