JPH01295347A - Microcomputer device - Google Patents

Abstract

PURPOSE:To shorten the access time by giving only the head address of a series of data to an instruction means via a control means in case a series of data having the continuous addresses are detected. CONSTITUTION:In case a series data having the continuous addresses, a control means 3 gives only the head address of the data to an address instruction means 15. A memory means 8 delivers the data stored in said head address and the means 3 transmits the replacement control signals to the means 15 and a holding means 17. The means 17 sends the output data received from the means 8 to a data processing means 2. The output data is temporarily held by the means 2 until the next output data is delivered from the means 8. The means 15 replaces the stored address and sends this to the means 8. When the replacement control signal is transmitted from the means 3, the means 17 sends the next data to the means 2. Thus it is possible to shorten the access time of a series of data having the continuous addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer device including a microprocessor and a memory, and particularly to a microcomputer device suitable for reading programs or data having consecutive addresses.

BACKGROUND ART Conventionally, a microcomputer device shown in FIG. 11 has been known as a microcomputer device. This microcomputer device is composed of a microprocessor 1, an address latch 7, and a memory 8, and these units are interconnected by an address data bus (hereinafter referred to as AD bus) 9.

Further, the microprocessor 1 includes a processing execution section 2 and an execution control section 3. The processing execution unit 2 is the memory 8
A bus request signal 4 requesting activation of a data read/write cycle for the data is output to the execution control unit 3, and data address information of the access destination of the memory 8 is output to the execution control unit 3 via the address line 5. Further, the execution control unit 3 receives the pass refresh 1-signal 4 and outputs an acknowledge signal 6 to the processing execution unit 2.

The AD bus functions as both an address bus and a data bus in order to reduce the number of signal lines. Address information, instruction codes, and input data multiplexed on this AD bus are demultiplexed by the address latch 7. and is input to the memory 8 via the address bus 10. The microprocessor 1 also sends an address latch enable signal that specifies latch timing to the address latch 7.
It outputs a read signal (hereinafter referred to as an RD double signal) 12 to the memory 8.

Next, the operation of the conventional microcomputer device will be described with reference to the timing diagram of FIG. 12 in the case where programs having consecutive addresses are input continuously.

Normally, programs are stored in consecutive memory areas in sequence, and the microprocessor 1 reads and executes these programs via the AD bus according to the address order.

As shown in FIG. 12, one cycle of program input consists of three basic operation states B, . First, the microprocessor 1 activates the ALE signal 11 during the basic operating state B1.

Further, from basic operation state B1 to B2, microprocessor 1 outputs a read address to the AD bus. In the basic operation state B2, an address is latched in the address latch 7 at the falling edge of the ALE signal 11, and is output to the address bus 10. Next, basic operation state B
3, when the RD signal 12 (negative logic) becomes active, the memory 8 outputs read data to the AD bus in synchronization with this. The microprocessor 1 takes in data from the AD bus at a predetermined timing within the period of the basic operation state B5. Through the above series of processes, one cycle of program input is completed, and the microprocessor 1 executes the read instructions. After the instruction execution is completed, the read address is output again and the instruction code is read in the same cycle as the previous one. This is repeated until the program execution is complete.

[Problems to be Solved by the Invention] In the conventional microcomputer device, the processing execution section 2 outputs the read address to the address line 5 during the period of the basic operation state B1, and outputs the read address to the address line 5 during the period of the basic operation state B3. The period until data corresponding to that address is received is a data waiting period for waiting for data to be input. This idle time of the processing execution unit 2 reduces the processing speed of the entire device.

Further, the conventional microcomputer device reads an instruction code from the memory 18, executes it, outputs the address of the next instruction code to the AD bus, and repeats the program input cycle. Therefore, the overall processing time of a microcomputer device is determined by the read time and execution time of the instruction code, and even if a microprocessor capable of high-speed processing is used, it is difficult to improve the processing speed due to access time limitations. do not have. In particular, when reading and inputting instruction codes set at consecutive addresses such as in a program, most of the processing of the microprocessor 1 is in the instruction code waiting state, which reduces the processing speed of the entire microcomputer device. There is a problem.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a microcomputer device that can significantly shorten access time for program reading, data reading, etc.

[Means for Solving the Problems] A microcomputer device according to the present invention includes a storage means for storing processing data including instruction codes, a data processing means for processing the data upon receiving transfer of the processing data, and a storage means for storing processing data including instruction codes; control means for controlling the transfer of the data and outputting an update control signal; and an address for storing an address instructing the storage contents of the storage means, for inputting an update control signal from the control means to update the address and for storing the address. one or more instruction means for outputting the data to the storage means; and one or more instruction means for inputting an update control signal from the control means to output the output data of the storage means to the data processing means and temporarily holding this data. and a plurality of holding means, and when reading a series of data having consecutive addresses, the control means supplies only the first address of the series of data to the instruction means.

[Operations] In the present invention, when reading a series of data having consecutive addresses from the storage means, the control means supplies only the address of the first data to be read to the instruction means. The storage means receives an address from the instruction means and outputs the data stored at this address. The control means outputs an update control signal to the instruction means and the holding means.

Then, the holding means outputs the output data output from the storage means to the data processing means, and temporarily holds this data until the next output data from the storage means is output. The instruction means updates the stored address and outputs it to the storage means. Next, when the control means outputs an update control signal, the holding means outputs the next data to the data processing means.

Since the control means sequentially outputs update control signals, the holding means outputs the output data of the storage means, and the instruction means updates the stored address, the address of the data is sent to the instruction means every time one piece of data is read. In this way, the data to be processed by the data processing means is read in advance from the storage means, so access to programs and data can be made faster.

Further, when reading data other than a series of data with consecutive addresses, for example, after the control means gives the address of the first data to be read to another instruction means, this other instruction means and other An update control signal is output to the holding means.

Then, each time the update control signal is output, the other holding means outputs the data in the storage means, and the other instruction means updates the address to the address of the next data.

Next, when a series of data with consecutive addresses is to be read again, after reading the data held in the holding means, the control means sequentially sends an update control signal to the instruction means and the holding means. By outputting, it is possible to read a series of data with consecutive addresses following the previous one.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a microcomputer device according to a first embodiment of the present invention. The microprocessor 1 performs data input/output processing, arithmetic processing, and control of the entire microcomputer device. The memory chip 13 has a memory 8, and this memory 8 stores programs to be executed by the microprocessor 1 and data necessary for its execution.

The microprocessor 1 includes a processing execution section 2 that executes instructions, and an execution control section 3 that controls the overall operation of the microprocessor 1.

A bus request signal 4 and an address line 5 are output from the processing execution section 2 to the execution control section 3. This bus request signal 4 is a signal requesting activation of a data read cycle between the memory 8 in the memory chip 13 and the memory 8 in accordance with the execution of an instruction, and the address line 5 transmits data address information of the access destination of the memory 8. . When the execution control unit 3 receives a request to start a data read cycle, it outputs the processing execution unit 2 hair removal signal 6.

The microprocessor 1 is connected to a memory chip 13 via an AD bus. Address information and data are multiplexed on this AD bus. Data is read between the microprocessor 1 and the memory 8 in the memory chip 13 via this AD bus.

The bus interface unit 14 connects the memory chip 13 based on various signals output from the microprocessor 1, which will be described later.
The data is read from a predetermined address in the memory 8 by controlling the operation of the memory 8. The address counter 15 latches the address information input from the AD bus, and the address decoder 1
Output to 6.

Then, the address counter 15 increments its contents in synchronization with the rise of a data latch control signal (hereinafter referred to as a DLC signal) 20, which will be described later. The address latch 7 is also controlled by the bus interface unit 14 to latch address information input from the AD bus.

The output of the address counter 15 or the output of the address latch 7 is input to the address decoder 16 based on a control signal to be described later, and a cell of the memory 8 is selected based on the contents (address information). Memory 8 is address decoder 16
outputs the data of the selected cell to the microprocessor 1. The output latch 17 temporarily holds the output data output from the memory 8 at the rising edge of the DLC signal 20. The output buffer 18 is controlled by the bus interface section 14 and outputs the output data from the memory 8. A memory address bus (hereinafter referred to as MAD bus) 19 interconnects the bus interface section 14, address counter 15, address latch 7, output latch 17, and output buffer 18.

Next, control signals input to and output from the microprocessor 1 and the memory chip 13 will be explained.

A reset signal 22 is input to the microprocessor 1 as an input control signal for initializing hardware within the microprocessor 1 .

The microprocessor 1 outputs an ALE signal 11, an RD signal 12, a DLC signal 20, and a counter/latch selection control signal (hereinafter referred to as C/Latch) as output control signals to the memory chip 13.
21 (referred to as the L signal) is output.

ALE signal 11 provides timing for address latch 7 or address counter 15 to latch address information on MAD bus 19. The RD signal 12 provides timing for the microprocessor 1 to read data from the memory 8 within the memory chip 13. C/L signal 21 is MAD bus 1
Instructing which of the address counter 15 and the address latch 7 should latch the address information of 9, and
It instructs which of the output latch 17 and the output buffer 18 is selected as the output light of the data from the memory 8.

The DLC signal 20 is an update control signal that causes the output latch 17 to latch the output data of the memory 8 in synchronization with its rising edge, and causes the address counter 15 to increment its count contents. Note that the RD signal 12
is a low active signal. In addition, the C/L signal 21
When is at a high level, the contents of the address latch 7 are output to the address decoder 16, and when is at a low level, the contents of the address counter 15 are output.

Next, the operation of the microcomputer device configured as described above will be explained with reference also to FIGS. 2, 3, and 4. Note that in these figures, Pi (i=1.
2, 3. ) indicates a program address and data, and Di indicates a data storage address and data. Further, data Pi (Di) is data stored at address Pi (Di>) of the memory 8.

FIG. 2 is a timing diagram showing a read cycle of a program immediately after a branch, FIG. 3 is a timing diagram showing a read cycle of a program having consecutive addresses, and FIG. 4 is a timing diagram showing a read cycle of a data read.

The read cycle of the microprocessor 1 consists of four basic operating states T1, T2, . T3.
It consists of TI and free state. Execution control unit 3
outputs various control signals to the memory chip 13 based on these states to control read cycles with the memory 8 associated with execution of instructions.

As shown in FIG. 2, the read cycle immediately after a program branch is comprised of basic operating states T, . . . T2°TI. First, in order to write the address (address PL) of the execution program to the address counter 15, the execution control unit 3 starts the A at the start timing t1 of the state T1.
The LE signal 11 is raised and the C/L signal 21 is set to low level to designate the address counter 15 as the address write destination. As a result, the bus interface section 14 sets the address P1 of the MAD bus 19 to the address counter 15 at an intermediate timing t2 in the state T1.
input. This address P1 is then input to the address decoder 16.

Next, the execution control unit 3 determines the end timing t of state T1.
3, the ALE signal 11 falls.

As a result, the bus interface unit 14 closes the input gate of the address counter 15 and causes the address counter 15 to latch the address information (address PL) on the MAD bus 19. The memory 8 selects the cell at the address P1 by the address decoder 16 and outputs the data P1.

The execution control unit 3 lowers the DLC signal 20 at start timing t3 of state T2, and raises the DLC signal 20 at timing t4 in the middle of state T2. As a result, the bus interface section 14 causes the address counter 15 to increment its contents, inputs the address P2 of the next instruction code to the address decoder 16, and transfers the contents (data PL) outputted from the memory 8 to the output latch 17. to latch. The data P1 latched in the output latch 17 is output to the MAD bus 19 when the RD signal 12 becomes low level.
Next, in state TI, data P1 on the MAD bus 19 is output to the AD bus, and at timing t6 in the middle of state TI, the execution control unit 3 takes in the instruction code (data PL) on the AD bus and sends it to the processing execution unit 2.
At the same time, the RD signal 12 is raised to complete the read cycle immediately after branching.

Next, a read cycle for reading a program having consecutive addresses following address P1 will be described with reference to FIG. As shown in FIG. 3, a read cycle of a program located at consecutive addresses is performed in a sequence of basic operating states T3 and basic operating states T3.
It is composed of I. First, at timing t8 in the middle of state T3, the RD signal 12 is lowered. Then, the data P2 held in the output latch 17 becomes M
The data is output to the AD bus 19 and further taken into the processing execution unit 2 via the AD bus.

At timing t9 of the next state T3, the execution control unit 3 lowers the DLC signal 20, and furthermore, at timing tt
At o, the DLC signal 20 is raised. This results in
The content (data P3) that has been output from the memory 8 is latched into the output latch 17. Since the RD signal 12 is at a low level, this data P3 is output to the MAD bus 19, and further taken into the processing execution unit 2 via the AD bus.

Further, in synchronization with the rising edge of the WEDAT signal 20 at timing tto, the address counter 15 increments its contents (address P3), and
The incremented content (address P4) is output to the address decoder 16.

The memory 8 stores the address P selected by the address decoder 16.
The data of cell No. 4 (data P4) is output. Thereafter, this operation is continuously performed in parallel, and programs having consecutive addresses are read out. This read cycle is completed by raising the RD signal 12 at an intermediate timing of state TI.

Next, a case where data at an address different from the address held by the address counter 15 is read will be described with reference to the timing diagram of FIG. 4. In this case, the data read cycle is in the basic operating state T1. T2. T.I.
Consisted of.

The execution control unit 3 is in state T! At the start timing t1, the ALE signal 11 is raised and the C/L signal 2 is raised.
1 to high level, and then address latch M A D t<S19 of the data to be read at timing t2.
Output to. Address D1 of this MAD bus 19 is C/
Since the L signal 21 is at a high level, it is latched by the address latch 7 and input to the address decoder 16 at timing t2. As a result, the memory 8 outputs the data at address D1 (data D).

Next, when the execution control unit 3 lowers the RD signal 12 at timing t4, since the C/L signal 21 is at a high level, the data D-1 in the memory 8 is transferred to the output buffer 1.
8 and input to the processing execution unit 2 via one MAD bus and an AD bus. This read cycle is C
The state TI ends by setting the /L signal 21 to a low level at the end timing t7 of state TI.

During this data read cycle, the contents of the address counter 15 and output latch 17 are held, and immediately after the data read cycle ends, instruction codes with consecutive addresses are output to the processing execution unit 2, Read cycles of programs with consecutive addresses can be restarted.

As is clear from a comparison between FIG. 12 and FIGS. 2 and 3, in this embodiment, the time required for reading data when the microprocessor 1 inputs a program from the memory 8 is extremely short. There is.

FIG. 5 is a block diagram showing a microcomputer device according to a second embodiment of the present invention. In Figure 5, the first
Components that are the same as those in the drawings are designated by the same reference numerals and descriptions thereof will be omitted. This second embodiment uses an address counter A24 and an address counter B25, respectively, in place of the address counter 15 and address latch 7 in the first embodiment, and uses an output latch in place of the output latch 17 and output buffer 18, respectively. A26 and output latch B27 are used.

In other words, one of the address counter A24 and address counter B25 of the memory chip 23 is selected by the C/L signal 21 and outputs address information to the address decoder 16, and output latch A26 and output latch B27
are selected by the C/L signal 21, and data is input from the memory 8 to either one. When reading a program, the address counter A24 and output latch A26 are selected by setting the C/L signal 21 to a low level, and when reading data, the C/L signal 21 is set to a high level. This selects address counter B25 and output latch B27. Note that address P of memory 8
The data stored in 1 to P5 are data P1 to P5.
5, and the data stored in addresses D1 to D6 are data D1 to D6.

Next, the operation of the microcomputer device configured as described above will be explained with reference to timing diagrams shown in FIGS. 6, 7, and 8. The read cycle of this embodiment consists of four basic operating states T, , T2 . T3. Constructed by TI. FIG. 6 is a timing diagram showing a read cycle of a program immediately after a branch and a read cycle of a program having consecutive addresses. As is clear from FIG. 6, the read cycle in this case is the same as in the first embodiment. However, in this case, address counter A24 and output latch A26 are selected by setting C/L signal 21 to low level.

A data read cycle is divided into a read cycle for one data and a read cycle for data having consecutive addresses (hereinafter referred to as a continuous data read cycle). The read cycle for one data is as shown in Figure 7.
Basic operating states T,, T2. Constructed by TI.

First, the execution control unit 3 determines the start timing 1 of state T.
1, the ALE signal 11 and the C/L signal 21 are raised. Next, the execution control unit 3 outputs the address of the data D1 (address Di) to the AD bus.

The address counter B25 selected when the C/L signal 21 becomes high level takes in the address D1 from one MAD bus at timing t2 of state T1, and then takes in the address D1 from one MAD bus at timing t3.
When 1 falls, this address D1 is latched.

The execution control unit 3 lowers the DLC signal 20 at the start timing t3 of the state T2, and raises the DLC signal 20 at the timing t4, thereby transmitting the output data from the memory 8 to the output latch B27, as in the case of reading the program. The address counter B25 is latched and the contents of the address counter B25 are incremented. At the same time,
The RD signal 12 is lowered to output this data D1 to the MAD bus 19.

Next, in state T2, the execution control unit 3 executes the MAD
The contents of one bus are output to the processing execution unit 2 via the AD bus, and the RD signal 12 is output at timing t6 of state TI.
is raised, and at timing t7, the C/L signal 21 is lowered to complete the read cycle of one data.

Next, as shown in FIG. 8, the continuous data read cycle consists of a succession of basic operating states T3 and basic operating states TI. First, the execution control unit 3 starts at timing 1. Then, at timing t8, the RD signal 12 is brought down to select the data (data D2) held in the output latch B27 by raising the C/L signal 21 and selecting the address counter B25 and the output latch B27.
) is output to the processing execution unit 2 via the MAD bus 19 and the AD bus.

The execution control unit 3 raises and lowers the DLC signal 20 at timing t9 of the next state T3, and raises it at timing tto, thereby causing the output latch B27 to latch the output data D3 of the memory 8 and transfer this data D3 to MA.
In addition to outputting to the D bus 19, the address counter B2
5 (address D3) is incremented. The incremented contents of the address counter B25 (address D4) are input to the address decoder 16.

Address decoder 16 selects the cell at address D4 of memory 8, and memory 8 outputs data D4 at address D4. Data D3 on the MAD bus 19 is taken into the processing execution unit 2 via the AD bus.

Thereafter, by continuing this operation, data having consecutive addresses is read out. This continuous data read cycle causes the RD signal 12 to rise in state TI, and the C/C/
The process ends by lowering the L signal 21. As described above, from a comparison of FIG. 12 with FIGS. 6 and 8, it can be seen that in this embodiment, reading of a program and reading of data having consecutive addresses are performed at extremely high speed.

FIG. 9 is a block diagram showing a microcomputer device according to a third embodiment of the present invention. Note that in FIG. 9, the same parts as in FIGS. 1 and 5 are designated by the same reference numerals, and explanations thereof will be omitted. The microcomputer device according to the third embodiment has a bus interface section that directly connects the memory 8 in the memory chip 23 to the microcomputer device shown in FIG. A path 31 for outputting data to 14 is newly added as a component.

In this embodiment, the operation of each unit and control signal in the read cycle of a program with continuous addresses is the same as in FIG. 6, and the operation in the continuous data read cycle is the same as in FIG. The explanation of the operation will be omitted.

Next, when a request to execute a single data read with discontinuous addresses occurs due to program execution during a read cycle of program code with continuous addresses (hereinafter referred to as a continuous program read cycle),
The closed cycle will be explained with reference to FIG. 10.

The operation during execution of a continuous program read cycle is the same as that shown in FIG. 3 of the first embodiment, but the execution control unit 3 performs a single data read with non-consecutive addresses during execution of this read cycle as instructions are executed. When a cycle start request is accepted, following the T3 timing (at the middle t2 of the TI timing), the RD signal 12 is raised, and at the same time, the address counter A24 selected by the C/L signal 21 is activated in synchronization with the rising edge of the DLC signal 20. is incremented, and the output latch A26 latches the output content from the memory 8.Thereafter, the DLC signal 20 is not changed while the C/L signal 21 is at a high level.

At the leading edge t3 of the next T1 timing, the execution control unit 3 raises the ALE signal 11 and sets the C/L signal 21 to high level in order to write the address of the single data read into the address counter B25.

As a result, the bus interface section 14 inputs the contents of the MAD bus 19 to the address decoder 16 via the address counter B25 at the middle t4 of the T1 timing. Then, the execution control unit 3 executes AL at the trailing edge t5 of the T1 timing.
Turn down E signal 11. As a result, the bus interface section 14 closes the input gate of the address counter B25, and outputs the contents output from the memory 8 to the latch B3.
The data is output directly to the bus interface section 14 via the bus 31 without going through the bus 1.

At the middle t6 of the next T2 timing, the execution control section 3 sets the RD signal 12 to low level to transmit the contents of the bus interface section 14 to the processing execution section 2 via the A D /< bus 9. The RD signal 12 is raised at the same time as the data on the AD bus is taken in at the middle t8, and the C/L signal 21 is lowered at the trailing edge t9 of the same timing. The execution control unit 3 then maintains the DLC signal 20 at a high level during a single data read cycle period with non-continuous addresses. As a result, the contents of the address counter A24 and the output latch A26 are held, and by lowering the RD signal 12 at the middle tlO of the next T3 timing, the interrupted continuous program read cycle is restarted.

Furthermore, even if the execution control unit 3 receives a request to start a single program read cycle with non-continuous addresses during the execution of a continuous data read cycle, the instruction code stored in the memory 8 will be transferred to the output latch. The signal is output directly to the bus interface section 14 via the bus 31 without passing through A26. As a result, the read instruction code is immediately transmitted to the processing execution unit 2, and a single program read cycle is executed. After execution, the interrupted continuous data read cycle is immediately resumed.

As described above, according to this embodiment, even if there is a request to start a read cycle of a single program or single data having discontinuous addresses during continuous program read cycles and continuous data read cycles, the bus 31 is not activated. By reading out the instruction code and data through the memory card, the access time can be shortened.

Effects of the Invention As described above, according to the present invention, the control means sequentially outputs update control signals to the holding means and the instruction means, and the holding means outputs the output data of the storage means to the data processing means. Holding that data, the instruction means updates the stored address and outputs it to the storage means, so when reading data with consecutive addresses, the control means gives an address to the instruction means every time one piece of data is read. Since there is no need
Access time can be extremely shortened without adding a high-speed reference function to the storage means.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a microcomputer device according to a first embodiment of the present invention, FIG. 2 is a timing diagram showing a data read cycle of a program immediately after a branch in the first embodiment, and FIG. FIG. 4 is a timing diagram showing a data read cycle of a program having consecutive addresses in the first embodiment, FIG. 4 is a timing diagram showing a data read cycle in the first embodiment, and FIG. 5 is a timing diagram showing a data read cycle in the first embodiment. FIG. 6 is a block diagram showing a microcomputer device according to an example. FIG. 6 is a timing diagram showing a read cycle of a program immediately after a branch and a read cycle of a program having consecutive addresses in the second embodiment. FIG. FIG. 8 is a timing diagram showing a read cycle of single data in the embodiment. FIG. 8 is a timing diagram showing a read cycle of data having consecutive addresses in the second embodiment. FIG. 9 is a timing diagram showing a read cycle of data having consecutive addresses in the second embodiment. A block diagram showing a microcomputer device according to an example,
Fig. 10 is a timing diagram when there is a request to read non-continuous data during a continuous program read cycle in the third embodiment, Fig. 11 is a block diagram showing a conventional microcomputer device, and Fig. 12 shows its operation. FIG. 3 is a timing chart diagram for explanation. 1; microprocessor, 2; processing execution unit, 3; execution control unit, 4; bus request signal, 5; address line, 6;
Acknowledge signal, 7; Address latch, 8; Memory,
9; A[) bus, 10. Address bus, 11; AL
E signal, 12; RD double signal 13.23; memory chip,
14; Bus interface unit, 15; Address counter, 16; Address decoder, 17; Output latch, 18
;Output buffer, 19;MAD bus, 20. WED
AT signal, 21. DRC signal, 22; Reset signal, 2
4; Address counter A, 25; Address counter B,
26; Output latch A, 27; Output latch B, 31: Pass

Claims (1)

[Claims] (1) A storage means for storing processing data including instruction codes, a data processing means for receiving the transfer of processing data and processing the data, and a control means for controlling the transfer of the processing data and outputting an update control signal. , one or more instruction means for storing an address for instructing the storage contents of the storage means, inputting an update control signal from the control means to update the address, and outputting the stored address to the storage means; , one or more holding means for inputting an update control signal from the control means, outputting the output data of the storage means to the data processing means, and temporarily holding this data; 2. A microcomputer device, characterized in that when reading out a series of data, said control means supplies only the first address of the series of data to said instruction means.