JPH01295444A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01295444A JPH01295444A JP63026653A JP2665388A JPH01295444A JP H01295444 A JPH01295444 A JP H01295444A JP 63026653 A JP63026653 A JP 63026653A JP 2665388 A JP2665388 A JP 2665388A JP H01295444 A JPH01295444 A JP H01295444A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- insulating film
- forming
- wiring
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概要〕
チップ構造の半導体装置の外部電極構造の改良に関し、
従来構造において、性能試験に際して金属バンプの税落
や変形を生じ、該半導体装置の歩留り低下や、外部回路
との接続の信頼性低下を生じていた点を解決するバンプ
を用いる電極構造の形成方法を提供することを目的とし
、
半導体基板上の層間絶縁膜上に形成する上層のアルミニ
ウム配線を、外部リードと接続するバンプが形成される
バンプ接続部とプローバの触針が当接するパッド部とを
もつ拡がりに形成する工程、前記触針をパッド部に当接
せしめ所定の試験を行った後にバンプ接続部とパッド部
を覆う被覆絶縁膜を形成する工程、および該被覆絶縁膜
に開孔を形成し、開孔形成部にバリアメタルとバンプと
から成る電極を形成する工程を含むことを特徴とする半
導体装置の製造方法を含み構成する。[Detailed Description of the Invention] [Summary] Regarding the improvement of the external electrode structure of a semiconductor device with a chip structure, in the conventional structure, the metal bumps were deformed or deformed during a performance test, resulting in a decrease in the yield of the semiconductor device and damage to the external circuit. The purpose of this project is to provide a method for forming an electrode structure using bumps that solves the problem of poor connection reliability with external leads. A process of forming a bump connection part in which a bump is formed to be connected to the prober, and a pad part to which the stylus of the prober comes into contact; and a step of forming an insulating coating film covering the pad portion, forming an opening in the insulating coating film, and forming an electrode made of a barrier metal and a bump in the opening area. Contains and constitutes a method for manufacturing the device.
本発明は、チップ構造の半導体装置の外部電極構造の改
良に関する。The present invention relates to an improvement in the external electrode structure of a chip-structured semiconductor device.
半導体装置の集積密度を上げて、各種情報処理装置の小
型大容量化を図るためにチップ構造の半導体装置が用い
られる。2. Description of the Related Art Chip-structured semiconductor devices are used to increase the integration density of semiconductor devices and to increase the size and capacity of various information processing devices.
チップ構造の半導体装置においては、外部回路に取り付
けられる以前にその性能試験がプローバを用いる触針法
でなされるが、この際該半導体装置の外部電極部即ちバ
ンプ部が損傷され易く、このため該半導体装置を情報処
理装置等の配線基板に金属バンプを介して取り付けた際
の接続の信頼性が低下するという問題があり、バンプ部
に損傷を与えずにブローバによる性能試験が行なえる外
部電極構造が要望されている。Performance tests for chip-structured semiconductor devices are performed using a stylus method using a prober before they are attached to an external circuit, but in this case, the external electrode portions, that is, the bump portions of the semiconductor device are likely to be damaged. There is a problem that the reliability of the connection decreases when a semiconductor device is attached to a wiring board of an information processing device etc. via a metal bump, so an external electrode structure that allows performance testing with a blower without damaging the bump part is needed. is requested.
第3図は、上記チップ構造の半導体装置における従来の
バンプ部の構造を示す要部模式側断面図である。FIG. 3 is a schematic side sectional view of a main part showing the structure of a conventional bump portion in the semiconductor device having the above-mentioned chip structure.
同図において、11は層間絶縁膜、12は上層のアルミ
ニウム(AJ)配線、13は被覆絶縁膜、14は上層配
線を表出する被覆絶縁膜の開孔、15はバリアメタルパ
ターン、16は金属バンプを示す。In the figure, 11 is an interlayer insulating film, 12 is an upper layer aluminum (AJ) wiring, 13 is a covering insulating film, 14 is an opening in the covering insulating film that exposes the upper layer wiring, 15 is a barrier metal pattern, and 16 is a metal Showing bumps.
従来上記バンプを形成する際には、被覆絶縁膜13上に
上層AI配線12の一部を表出する開孔14を形成した
後、該開孔14内を含む被覆絶縁膜3上にバリアメタル
層15をスパッタ法、蒸着などにより被着し、該バリア
メタル層上にバリア形成領域を表出する開孔を有するレ
ジスト膜を形成し、該レジスト膜をマスクにして電気メ
ツキ法により該レジスト膜の開孔内に例えば金(Au)
よりなる金属バンプ16を成長させ、上記レジス)MW
を除去した後、上記金属(Au)バンプ16をマスクに
してエツチング手段によりバリアメタル層の表出領域を
選択的に除去する方法が用いられていた。そこで従来の
バンプ部は同図に示すように金属(Au)バンプ5の下
部のみにバリアメタルパターン5が配設される構造であ
った。なお、バンプ16に対しては最終的に外部リード
17が熱圧着によって接続され、外部回路との接続がと
られるものである。Conventionally, when forming the above-mentioned bump, after forming an opening 14 exposing a part of the upper layer AI wiring 12 on the covering insulating film 13, a barrier metal is formed on the covering insulating film 3 including the inside of the opening 14. Layer 15 is deposited by sputtering, vapor deposition, etc., a resist film having openings exposing the barrier formation region is formed on the barrier metal layer, and the resist film is electroplated using the resist film as a mask. For example, gold (Au) is placed inside the opening of
The metal bump 16 consisting of the above resist) MW is grown.
After removing the barrier metal layer, an exposed area of the barrier metal layer is selectively removed by etching using the metal (Au) bump 16 as a mask. Therefore, the conventional bump section has a structure in which a barrier metal pattern 5 is provided only at the lower part of the metal (Au) bump 5, as shown in the figure. Incidentally, an external lead 17 is finally connected to the bump 16 by thermocompression bonding to establish a connection with an external circuit.
従来チップ構造の半導体装置の性能を外部回路への取り
付けに先立ってプローバを用いて試験する際には、金属
バンプ16上に触針全室てて試験せざるを得ない。この
とき、プローバは自動的に第3図に示されるデバイスが
形成されたウェハに向は自動的に動かされて触針がこの
例の場合にはバンプに当接するのであるが、バンプと触
針との間に確実な導通をとるため、バンプの寸法などに
よって定めたある力で触針がバンプに当接し、その際金
属バンプ16が脱落して該半導体装置が不良になったり
、また金属バンプ16が変形して一様に良好な外部回路
との接続が得られず外部回路との接続の信頼度が低下す
るという問題を生じていた。When testing the performance of a conventional chip-structured semiconductor device using a prober prior to attachment to an external circuit, the test must be performed with the entire stylus placed over the metal bump 16. At this time, the prober is automatically moved toward the wafer on which the device shown in FIG. 3 is formed, and the stylus contacts the bump in this example. In order to ensure reliable conduction between the metal bumps 16 and the bumps, the stylus contacts the bumps with a certain force determined by the dimensions of the bumps. 16 is deformed and a uniformly good connection with the external circuit cannot be obtained, resulting in a problem that the reliability of the connection with the external circuit is reduced.
また上記金属バンプの脱落、変形をなくすために、被v
fi、絶縁膜13にAl配線12を表出する開孔14を
形成した時点で、表出するAl配線上にプローバの触針
を立てて試験を行う方法も行われるが、この方法による
と第4図(a)の断面図と(b)の平面図に示されるよ
うに開孔内に表出するAl配線12の表面に深い穴(ま
たはキズ)18が形成され、第4図(C)の断面図と(
d>の平面図に示されるように該へl配線12の表出面
上に被着されるバリアメタル層15に特別薄い部分や欠
陥部を生じバリア効果が損なわれて、Al配線12と金
属(Au)バンプ16が反応し、該金属(Au)バンプ
が脱落し易くなるという問題がある。このことは、前記
したようにバリアメタルをスパッタリング法または蒸着
で被着するときに、バリアメタルが段差部や急峻な傾き
のある部分には平坦部上のように具合良く被着しないこ
とによるものである。In addition, in order to prevent the metal bumps from falling off and deforming,
When the opening 14 exposing the Al wiring 12 is formed in the insulating film 13, a test is also carried out by setting the stylus of a prober on the exposed Al wiring. As shown in the cross-sectional view of FIG. 4(a) and the plan view of FIG. 4(b), a deep hole (or scratch) 18 is formed on the surface of the Al wiring 12 exposed within the opening, and as shown in FIG. 4(C). A cross-sectional view of (
As shown in the plan view of Al wiring 12, the barrier metal layer 15 deposited on the exposed surface of the Al wiring 12 has particularly thin parts or defective parts, impairing the barrier effect, and causing the Al wiring 12 and the metal ( There is a problem in that the metal (Au) bumps 16 react and the metal (Au) bumps tend to fall off. This is because, as mentioned above, when barrier metal is applied by sputtering or vapor deposition, the barrier metal does not adhere as well to stepped areas or areas with steep slopes as it does to flat areas. It is.
更に、バリアメタル層を被覆絶縁膜の開孔上のみに形成
し、該開孔上のバリアメタル層上にプローバの触針を立
てて試験を行う方法も試みられたが、この方法だと触針
によってバリアメタル層が破壊されてバリア機能を失い
、上記同様A7!配線と金属(Au)バンプの反応によ
りバンプ脱落の障害を生ずる。Furthermore, a method was also attempted in which the barrier metal layer was formed only over the opening in the coating insulating film and the test was conducted by setting the stylus of a prober on the barrier metal layer above the opening. The barrier metal layer is destroyed by the needle and loses its barrier function, and as above, A7! The reaction between the wiring and the metal (Au) bumps causes problems such as bumps falling off.
そこで本発明は、上記のように従来構造において、性能
試験に際して金属バンプの脱落や変形を生じ、該半導体
装置の歩留り低下や、外部回路との接続の信頼性低下を
生じていた点を解決するバンプを用いる電極構造の形成
方法を提供することを目的とする。Therefore, the present invention solves the problem that, as described above, in the conventional structure, metal bumps may fall off or deform during performance tests, resulting in a decrease in the yield of the semiconductor device and a decrease in reliability of connection with external circuits. An object of the present invention is to provide a method for forming an electrode structure using bumps.
上記問題点は、半導体基板上の層間絶縁膜上に形成する
上層のアルミニウム配線を、外部リードと接続するバン
プが形成されるバンプ接続部とブローバの触針が当接す
るパッド部とをもつ拡がりに形成する工程、前記触針を
パッド部に当接せしめ所定の試験を行った後にバンプ接
続部とパッド部を覆う被覆絶縁膜を形成する工程、およ
び該被覆絶縁膜に開孔を形成し、開孔形成部にバリアメ
タルとバンプとから成る電極を形成する工程を含むこと
を特徴とする半導体装置の製造方法によって解決される
。The problem described above is that the upper layer aluminum wiring formed on the interlayer insulating film on the semiconductor substrate is spread out to have a bump connection area where bumps are formed to connect to external leads and a pad area where the blower stylus comes into contact. forming a covering insulating film that covers the bump connection part and the pad part after bringing the stylus into contact with the pad part and performing a predetermined test; and forming an opening in the covering insulating film. The problem is solved by a method of manufacturing a semiconductor device, which includes a step of forming an electrode made of a barrier metal and a bump in a hole forming portion.
すなわち本発明では、アルミニウム配線をバンプ接続部
と触針が接触するパッド部とを含む如くに形成し、触針
試験によってキズの付いたパッド部分を被覆絶縁膜で覆
い、しかる後にバンプ接続部形成のための開孔を被覆絶
縁膜に施し、この開孔した部分にバンプを形成するもの
である。That is, in the present invention, an aluminum wiring is formed to include a bump connection portion and a pad portion that is in contact with a stylus, and the pad portion that is scratched by the stylus test is covered with a covering insulating film, and then the bump connection portion is formed. A hole is formed in the covering insulating film, and a bump is formed in the hole.
以下、本発明を図示の一実施例により具体的に説明する
。Hereinafter, the present invention will be specifically explained with reference to an illustrated embodiment.
第1図(a)と(blは本発明実施例の断面図と平面図
である。FIGS. 1(a) and 1(bl) are a sectional view and a plan view of an embodiment of the present invention.
従来例においては、図示しない半導体基板に素子が形成
され、該半導体基板上に形成された燐・シリケート・ガ
ラス(PSG)などから層間絶縁膜11上にアルミニウ
ム配線12がバンプ接続部(開孔14が作られる部分)
を形成するに足る拡がりをもって形成されたが、本発明
においては、層間絶縁膜11までを従来例同様に形成し
た後に、アルミニウム配線21を、バンプ接続部22に
加え、プローブのためにプローバの触針と接触するバン
ド部23をももつように、従来例のAJ配線12を長く
延在せしめた構造に形成する。In the conventional example, an element is formed on a semiconductor substrate (not shown), and an aluminum wiring 12 is formed on an interlayer insulating film 11 from phosphorous silicate glass (PSG) formed on the semiconductor substrate at a bump connection portion (opening 14). (the part where is made)
However, in the present invention, after forming up to the interlayer insulating film 11 in the same manner as in the conventional example, the aluminum wiring 21 is added to the bump connection part 22, and the aluminum wiring 21 is added to the bump connection part 22, and the aluminum wiring 21 is The AJ wiring 12 of the conventional example is formed into a long extended structure so as to have a band portion 23 that comes into contact with the needle.
そして、触針によるプローブは、触針をパッド部23に
当接させて行う。その結果、パッド部23にはキズ24
が付けられる。このキズ24が付けられることは、前述
したように現在の技術では避けられない。The probe using the stylus is performed by bringing the stylus into contact with the pad portion 23. As a result, there are scratches 24 on the pad portion 23.
is added. As mentioned above, the formation of this scratch 24 is unavoidable with the current technology.
次いで、被覆絶縁膜13を被着する。例えば、PSGを
気相成長(CVD )で1μmの厚さに堆積する。Next, a covering insulating film 13 is deposited. For example, PSG is deposited to a thickness of 1 μm by chemical vapor deposition (CVD).
CVD法においては、スパッタリング、蒸着の場合と異
なり、キズの段差部、傾斜部を完全に覆う膜の成長があ
るので、キズ24はPSGの被覆絶縁膜で完全に覆われ
る。In the CVD method, unlike in the case of sputtering or vapor deposition, a film is grown that completely covers the stepped portions and sloped portions of the scratches, so the scratches 24 are completely covered with the PSG coating insulating film.
次いで、通常のリソグラフィー技術により、被覆絶縁膜
にバンプ接続部22を表出する例えば50〜100μ請
角程度の開孔14を形成した後に、全面にスパッタリン
グ法でそれぞれ3000人程度0厚さのTi層とpt層
とを続けて堆積せしめて、開孔14を含む被覆絶縁膜1
3の全面上にTiとPLとの2層構造よりなるバリアメ
タル層15を形成する。続いて、従来例と同様にバリア
メタル層15とバンプ16を形成する。Next, a hole 14 of, for example, about 50 to 100 μm angle is formed in the covering insulating film to expose the bump connection portion 22 by a normal lithography technique, and then a Ti film with a thickness of about 3000 mm is formed on the entire surface by a sputtering method. The covering insulating film 1 including the openings 14 is formed by successively depositing the PT layer and the PT layer.
A barrier metal layer 15 having a two-layer structure of Ti and PL is formed on the entire surface of the substrate 3. Subsequently, a barrier metal layer 15 and bumps 16 are formed in the same manner as in the conventional example.
上記した方法によると、AIl配線21のパッド部でプ
ローブを行い、その際形成されたキズを覆って被覆絶縁
膜を堆積し、この被覆絶縁膜のバンプ接続部を開孔して
バリアメタル、バンプを形成するのであるから、バンプ
、バリアメタル、Affi配線にはなんらのキズも作ら
れることなく、信頼性の高い電極構造をもった半導体装
置が提供されるものである。According to the above-mentioned method, a probe is performed at the pad part of the AIl wiring 21, a covering insulating film is deposited covering the scratches formed at that time, and a hole is opened at the bump connection part of the covering insulating film to form a barrier metal and a bump. Therefore, a semiconductor device having a highly reliable electrode structure is provided without any scratches being made on bumps, barrier metals, or Affi wiring.
本発明の変形例は第2図の平面図に示される。A variation of the invention is shown in plan view in FIG.
一般に、パッド部は触針との関係である寸法以上のもの
であることが要求されるが、バンプ接続部22の寸法は
50〜100μ−角の範囲にある。そこで、例えばバン
プ部22が50μl角の寸法のときにはパッド部23が
大きく形成されることもある。このように、バンプ接続
部22とバンプ部23とを、それぞれに要求される所定
の寸法に形成することも可能であり、本発明の通用範囲
は第1図に示した例に限定されるものではない。Generally, the pad portion is required to have a size that is at least a certain size in relation to the stylus, but the size of the bump connection portion 22 is in the range of 50 to 100 μ-square. Therefore, for example, when the bump portion 22 has a size of 50 μl square, the pad portion 23 may be formed large. In this way, it is also possible to form the bump connecting portion 22 and the bump portion 23 to the predetermined dimensions required for each, and the scope of the present invention is limited to the example shown in FIG. isn't it.
以上のように本発明によれば、バンプにキ°ズを着ける
ことがないので外部リードの接続は良好になされ、外部
リードの接続はプローブによって良品と認定されたチッ
プに対してのみなされるので、外部リード接続の不良、
不良チップに対するリード接続は行われず、コスト低減
に有効で、プローブによる試験データをフィードバック
して、ステッパなどを利用し良品チップにのみバンプが
形成され、無駄な作業が完全に回避される効果がある。As described above, according to the present invention, the bumps are not scratched, so the external leads can be connected well, and the external leads can only be connected to chips that have been certified as good by the probe. , defective external lead connection,
Leads are not connected to defective chips, which is effective in reducing costs. Test data from the probe is fed back and bumps are formed only on good chips using a stepper, which completely avoids unnecessary work. .
第1図は本発明実施例の図で、その(81は断面図、(
b)は平面図、
第2図は本発明変型側平面図、
第3図は従来例断面図、
第4図は従来例の問題点を示す図で、その(alと(C
)は断面図、(11)と(diは平面図である。
図中、
11は層間絶縁膜、
12はA1配線、
13は被覆絶縁膜、
14は開孔、
15はバリアメタル、
16はバンプ、
17は外部リード、
1日はキズ、
21はAl配線、
22はバンプ接続部、
23はパッド部
を示す。
特許出願人 富士通株式会社
代理人弁理士 久木元 彰
□−−−−
□1■ニニー二ヨと
□■」
第1図
114聞脆珠順
13 補f1とt挿議
14 関ル
] 15 バリアメタル
16 バンプ。
21 A/DC線
22 ノ\′ン7゛nと1吾F
23 バ〜ド゛(p
−η
1変來ffi ノrsB 、@、 t 示j J従来1
Fllめ間数、乞を示↑囚
第4図
手続補正書(方式)
%式%
1、事件の表示
昭和63年特許願第26653号
2、発明の名称 半導体装置の製造方法3、補正をす
る者
事件との関係 特許出願人
住 所 神奈川県用崎市中原区上小田中1015番地(
522)名 称 富士通株式会社
4、代理人 ■160 電話(03) 350
−0270(発送日平成1年7月4日)
6、補正の対象
図面、第4図の図番号(a 、 bの分)7・補正の内
容 別紙のとおり
覆え禾イf’lの問題、!、を示を口
第4図FIG. 1 is a diagram of an embodiment of the present invention, in which (81 is a sectional view, (
b) is a plan view, Fig. 2 is a plan view of the modified side of the present invention, Fig. 3 is a sectional view of the conventional example, and Fig. 4 is a diagram showing the problems of the conventional example.
) is a cross-sectional view, (11) and (di are plan views. In the figure, 11 is an interlayer insulating film, 12 is A1 wiring, 13 is a covering insulating film, 14 is an opening, 15 is a barrier metal, and 16 is a bump) , 17 is an external lead, 1 is a scratch, 21 is an Al wiring, 22 is a bump connection part, and 23 is a pad part. Patent applicant Akira Kukimoto, Fujitsu Limited representative patent attorney □---- □1■ "Nininiyo and □■" Fig. 1 114 mound order 13 Supplementary f1 and t interpolation 14 Kanru] 15 Barrier metal 16 Bump. 21 A/DC line 22 No\'n7゛n and 1goF 23 Bird (p −η 1 changeffi NorsB , @, t Indication j J Conventional 1
1. Indication of the case 1988 Patent Application No. 26653 2. Title of the invention Method for manufacturing semiconductor devices 3. Make amendments Relationship with the Patent Case Patent Applicant Address 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture (
522) Name Fujitsu Limited 4, Agent ■160 Telephone (03) 350
-0270 (Delivery date: July 4, 1999) 6. Drawings to be amended, drawing numbers of Figure 4 (for a and b) 7. Contents of the amendment As shown in the attached sheet, the issue of cover-up, ! Figure 4 shows the opening.
Claims (1)
のアルミニウム配線(21)を、外部リード(17)と
接続するバンプ(16)が形成されるバンプ接続部(2
2)とプローバの触針が当接するパッド部(23)とを
もつ拡がりに形成する工程、前記触針をパッド部(23
)に当接せしめ所定の試験を行った後にバンプ接続部(
22)とパッド部(23)を覆う被覆絶縁膜(13)を
形成する工程、および 該被覆絶縁膜(13)に開孔(14)を形成し、開孔形
成部にバリアメタル(15)とバンプ(16)とから成
る電極を形成する工程を含むことを特徴とする半導体装
置の製造方法。[Claims] A bump connection portion (2) in which a bump (16) is formed to connect an upper layer aluminum wiring (21) formed on an interlayer insulating film (11) on a semiconductor substrate to an external lead (17).
2) and a pad portion (23) that the stylus of the prober comes into contact with.
) and perform the prescribed test, then the bump connection part (
22) and a step of forming a covering insulating film (13) covering the pad portion (23), forming an opening (14) in the covering insulating film (13), and forming a barrier metal (15) in the opening forming part. A method of manufacturing a semiconductor device, the method comprising the step of forming an electrode consisting of a bump (16).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63026653A JPH01295444A (en) | 1988-02-09 | 1988-02-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63026653A JPH01295444A (en) | 1988-02-09 | 1988-02-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01295444A true JPH01295444A (en) | 1989-11-29 |
Family
ID=12199394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63026653A Pending JPH01295444A (en) | 1988-02-09 | 1988-02-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01295444A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5554940A (en) * | 1994-07-05 | 1996-09-10 | Motorola, Inc. | Bumped semiconductor device and method for probing the same |
| US5891745A (en) * | 1994-10-28 | 1999-04-06 | Honeywell Inc. | Test and tear-away bond pad design |
| WO2004001839A1 (en) * | 2002-06-21 | 2003-12-31 | Fujitsu Limited | Semiconductor device and its producing method |
| JP2010050224A (en) * | 2008-08-20 | 2010-03-04 | Oki Semiconductor Co Ltd | Semiconductor device ,and method of manufacturing the same |
| WO2012035688A1 (en) * | 2010-09-16 | 2012-03-22 | パナソニック株式会社 | Semiconductor device, semiconductor device unit, and semiconductor device production method |
| JP2017045900A (en) * | 2015-08-27 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
-
1988
- 1988-02-09 JP JP63026653A patent/JPH01295444A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5554940A (en) * | 1994-07-05 | 1996-09-10 | Motorola, Inc. | Bumped semiconductor device and method for probing the same |
| US5891745A (en) * | 1994-10-28 | 1999-04-06 | Honeywell Inc. | Test and tear-away bond pad design |
| WO2004001839A1 (en) * | 2002-06-21 | 2003-12-31 | Fujitsu Limited | Semiconductor device and its producing method |
| US7095045B2 (en) | 2002-06-21 | 2006-08-22 | Fujitsu Limited | Semiconductor device and manufacturing method thereof |
| JP2010050224A (en) * | 2008-08-20 | 2010-03-04 | Oki Semiconductor Co Ltd | Semiconductor device ,and method of manufacturing the same |
| WO2012035688A1 (en) * | 2010-09-16 | 2012-03-22 | パナソニック株式会社 | Semiconductor device, semiconductor device unit, and semiconductor device production method |
| JP2017045900A (en) * | 2015-08-27 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
| CN106486446A (en) * | 2015-08-27 | 2017-03-08 | 瑞萨电子株式会社 | The manufacture method of semiconductor device and semiconductor device |
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