JPH01295541A - Waveform shaping and identifying circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a demodulation circuit in a digital communication device.

(Prior Art) Conventionally, in this type of circuit, the optimum phase of a recovered clock for a received signal is set by adjusting the delay time of an n-stage regular filter made up of CRs as shown in FIG. It was obtained. The operation of the conventional waveform shaping identification circuit shown in FIG. 3 will now be explained. First, in FIG. 3, a received signal as shown in FIG. 4(a) is input from terminal 1, and the waveform is shaped by the waveform shaping circuit 2 into high level and low level as shown in FIG. 4(b). .

Next, as shown in FIG. 4(C), a received recovered clock synchronized with the received signals (a) and (b) is extracted and reproduced by clock recovery time vs3. This is set as n in the phase adjustment circuit 4 to set the delay time of the filter as variable resistor RVI...RV.
n to match the reproduced clock to the optimum phase. The amplitude attenuated by the phase adjustment circuit 4 is then amplified to a desired amplitude by the amplifier circuit 5. This output has the waveform shown in FIG. 4(d). When the optimally phased recovered clock (d) and received signal (b) in Figure 4 are input to the sampling circuit 6, the synchronized signals (d) and (e) in Figure 4 are output to the output terminals 7.8. Ru. This adjustment of the optimum phase is performed, for example, from the transmitting side separately from the information or based on the transmission of synchronization signal pulses included in the information and based on the measurement results of the bit error rate.

(Problems to be Solved by the Invention) Incidentally, as the reception level of the receiver becomes weaker, the S/N of the reception signal 48 that can be input to terminal 1 in FIG. 3 deteriorates. Accordingly, the reproduced clocks extracted and reproduced by the clock reproduction circuit 3 also have different pulse widths as shown in FIG. 5 (Co). In other words, jitter occurs. Different pulse widths equivalently mean different frequencies. In Figure 5,
Pulse width To and Tll T2 are respectively frequency fo,
fo−△f.

Assuming that it corresponds to fO+△f, and further assuming that the delay time versus frequency characteristic of the n-setting filter in the phase adjustment circuit 4 of FIG. 3 is as shown in FIG. 6, the output of the amplifier circuit 5 of FIG. Then, the result becomes as shown in Fig. 5 (d"). In other words, the jedder is amplified by the constant shape filter. As a result, the bit error rate (B, E, R) becomes as shown in Fig. 7. As the reception level of the receiver decreases, it deteriorates significantly from the theoretical value.

As described above, in conventional waveform shaping identification circuits, the optimal phase of the recovered clock is obtained by adjusting the delay time of the constant-shaped filter, so as a large delay amount is required, the number of stages of the constant-shaped filter increases. Furthermore, as the receiving level of the receiver decreases, the jitter of the recovered clock is amplified by the fixed filter, and the bit error rate (B, E, R) deteriorates significantly. Ta.

(Means for Solving the Problems) In order to eliminate these drawbacks, the present invention employs a method in which the phase adjustment circuit is processed digitally, that is, the reproduced clock signal is set higher than that of the conventional one, and the A shift register circuit that delays one bit and outputs in parallel,
One of the parallel outputs is digitally selected by a selector to obtain a synchronizing signal, which is then applied to the sampling circuit.Examples will be described below in detail with reference to the drawings.

(Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention, and for the sake of simplicity, the case where the frequency dividing circuit 4 is n=8 will be explained.

In Figure 1, the signal received from input terminal 1 is shown in Figure 7 (a).
When input, the waveform shaping circuit 2 converts the signal shown in FIG. 2(b)
After being shaped into High level and Low level as shown in FIG. Here, a clock of 8Xfcl, which is eight times the required clock frequency fcl, is reproduced as shown in FIG. 2(C). This 8Xfcl is inputted to the clock input terminal (9) of the shift register 6 in the phase adjustment circuit 5, and on the other hand, 8Xfcl is inputted to the frequency dividing circuit 4, and the waveform shown in FIG. 2(d) after frequency division by 8 is outputted. Next, this is inputted to the input terminal (10) of the shift register 6, and fcl is shifted one bit at a time by 8 bits using 8Xfcl, and then inputted to the output terminal (1) of the shift register 6.

(2), (3), (4), (5), (6), (7).

Waveforms (e), (f), (g) from (8) in Figure 2.

Output (h), (i), (j), (k), and (1), respectively. Roughly speaking, this is the input terminal (1) of selector 7,
(2), (3), (4), (5), (6).

Input terminals (7) and (8), input terminals (9) and (1
0) and (11), the waveform is shown in Fig. 2(e).

(f), (g), (h), (i), (j), (k).

(1) to the output terminal (12) of selector 7.
Output to. In this example, three control lines are used, so that <23=8 transitions are obtained as shown in Table 1. For example, [(9), (10), (11)] = (0,1 ,0)
Then, waveforms (g) and (m) in FIG. 2 are output to the output terminal (12) of the selector 7 (see Table 1).

Furthermore, this reproduced clock fcl (FIG. 2(m)) is input to the sampling circuit 8 to synchronize with the received signal FIG. 2(b), and the waveform FIG. 2(n) is outputted to the output terminal 12.

(Effects of the Invention) As described above, the waveform shaping identification circuit of the present invention can easily adjust the phase of the reproduced clock fcl because it can digitally set the phase to the optimum position. If you increase the frequency division number n and make nXfcl a high frequency,
Rough and fine phase settings are also easy. In addition, since the shift register 6 in Fig. 1 only shifts fcl one bit at a time using nXfcl, there is no element to amplify the jitter that occurs as the receiving level of the receiver decreases, as in the conventional system, and the opposite is true. Furthermore, since the reproduced clock fcL'li is obtained by dividing nXfcl by n, the generated jitter is also reduced to 1/n. Therefore, if the waveform shaping identification circuit of the present invention is used, even if the reception level of the receiver decreases as shown in FIG. 7, B, E, and R will not deteriorate significantly from their theoretical values as in the conventional system.

Furthermore, since it is entirely composed of digital circuits, it is easy to implement it into an LSI.

Because of the many advantages described above, the present invention has an extremely large effect on the demodulation circuit of a digital communication device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the embodiment of the present invention, FIG. 2 is a timing chart showing the waveforms of each part of FIG. 1, FIG. 3 is a block diagram of the conventional system, and FIG. 4 is a diagram of each part of FIG. Timing chart showing the waveforms. Figure 5 shows the recovered clock when the reception level of the receiver drops and the timing chart when it outputs the phase adjustment circuit in Figure 3. Figure 6 shows the timing chart when the signal is output from the phase adjustment circuit in Figure 3.
FIG. 7 is a graph showing the relationship between the reception level of the receiver and the bit error rate (B, E, R). 2... Waveform shaping circuit, 3... Clock regeneration circuit, 4
... Frequency dividing circuit, 5... Phase adjustment circuit, 6... Shift register, 7... Selector, 8... Sampling circuit. Patent applicant: Japan Radio Co., Ltd.fO-Affofo+,! lf Frequency receiver reception level procedure? Hoshosho (method) 1. Indication of the case Relationship to Patent Application No. 2292 of 1988 Patent applicant address 1-1 Shimorenjaku 5-chome, Mitaka-shi, Tokyo June 12, 1999 (all date of sending) (July 4, 1999) 5. "Figure 1" of the drawing to be amended, and the "Detailed Description of the Invention" column of the specification. 6. Contents of amendment (1) Figure 1 of the drawings will be corrected as shown in the attached sheet. (2) Insert the following table in the line next to "Three control lines" written on page 6, line 10 of the specification. "Table 1

Claims (1)

[Claims] The voltage of the received signal is compared by a waveform shaping circuit and the H level and L level are determined.
A waveform shaping identification circuit configured to demodulate the received signal by adding it to one end of the sampling circuit after shaping the level, and also adding the recovered clock signal extracted by the clock recovery circuit to the other end of the sampling circuit via the phase adjustment circuit. generating a clock signal of n times the frequency from the clock regeneration circuit and applying it to one end of the shift register;
In addition, one bit of the n-times clock signal is sequentially delayed by adding it to the other end of the shift register via a 1/n frequency divider circuit, and one of the obtained n parallel clock signals is digitally transmitted within the selector. A waveform shaping identification circuit, characterized in that a synchronizing signal is selected to be added to the sampling, and its phase is optimally set with respect to a received signal.