JPH01295548A - FSK demodulator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FSK demodulator, and particularly to an FSK demodulator that demodulates an FSK-modulated signal and converts it into binary data.

[Prior Art] Conventionally, when transmitting and receiving digital data via an analog transmission path, an FSK (frequency shift keying) modulation method has been used. The FSK method is, for example, CCI
It is used in data communication devices such as facsimile machines that comply with TT Recommendation V2 Recommendation-2123. FSK
The method associates different frequency components with 1's and 0's of a binary signal.

When receiving and demodulating an FSK modulated signal, a demodulator using a PLL circuit as shown in FIG. 7, for example, is used. In FIG. 7, reference numeral 100 is a PLL circuit, which is composed of a phase comparator 101, an LPF (0-pass filter) 1o2, and a VCO (voltage controlled oscillator) 1o3 that changes the frequency generated by following the output of the LPF 102. There is. In such a configuration, the phase comparator 101
compares the frequency and phase of the input signal with the oscillation frequency and phase of VCO 103, and generates an average DC voltage proportional to the error.

This voltage is applied to the input of VC0103 via LPF102. Normally, the output of the PLL circuit is VCO1.
03 is used, but in the case of FSK demodulation, LPF1
An LPF 104 is roughly added to the subsequent stage of 02, and a voltage signal indicating the phase comparison result is used as a demodulation signal (binary data of high level or low level). LPF102.10
4 are for removing harmonic components generated during phase comparison.

FIG. 8 shows the operation of the demodulator of FIG. 7. In FIG. 8, the horizontal axis represents time, and the vertical axis represents voltage level. In FIG. 8, reference numeral 81 is the output signal of the LPF 104, and a broken line waveform 82 is the data signal to be finally demodulated.

Further, the scale on the horizontal axis in FIG. 8 indicates the time width corresponding to the baud rate. The output 81 of the LPF 104 is designated by the symbol SP
As shown in , sampling is performed for each baud rate length, and a high level or low level binary signal can be demodulated depending on whether the voltage level at that time is positive or negative.

[Problems to be Solved by the Invention] In the conventional configuration as described above, when large instantaneous noise occurs, the signal may cross zero even though there is no data change point, which may cause data errors. In cases where noise occurs immediately before sampling, there is a possibility that the sampling data itself may be distorted.

An object of the present invention is to solve the above problems and provide an FSK demodulator that is resistant to interference caused by noise.

[Means for Solving the Problems] In order to solve the above problems, in the present invention, FS
FSK demodulates K-modulated signals and converts them into binary data
The demodulator consists of a PLL circuit that inputs the modulation signal, and 1, D, and F connected to the output of this PLL circuit,
I. A configuration was adopted in which the demodulated output was extracted from D and F.

[Function] According to the above configuration, I. Since D and F are used, P
The harmonic components after passing through the LL can be sufficiently removed, and FSK demodulation that is resistant to external disturbances can be performed.

[Embodiments] The present invention will be described in detail below based on embodiments shown in the drawings.

FIG. 1 shows the configuration of an FSK demodulator employing the present invention. The FSK demodulator shown in FIG. 1 is constructed using a DSP (digital signal processor).

In FIG. 1, reference numeral 205 is a control section of the DSP;
Each section shown at the bottom of the figure is controlled using an algorithm, which will be described later, stored in 206.

The main parts of the FSK demodulator include a multiplier 201, an LPF 202, a VCO 203, and an IDF (integrating low-pass filter) 204, which constitute a phase comparator.

As shown in the figure, each section is constructed using delay elements D1 to D4 having a delay time of T seconds (sampling time), an adder, a multiplier, and the like. These functional blocks are
It is composed of P hardware and/or software.

Here, the LPF 202 is an adder and a multiplier (coefficient is 2)
This is the simplest first-order loop filter using a delay element D2 (delay time is T).

In addition, the VCO 203 includes a multiplier (coefficient 03), an adder, an adder (coefficient C'4), a delay element D4, and a trigonometric function circuit (C
os).

The IDF 204 includes a delay loop composed of an adder and a delay element D3, and a switch SW connected to the subsequent stage.
1 and SW2. Switch SWI, SW
2 is controlled by software, and as noted in the appendix, N
The integral value is sequentially output via the switch SWI every 7 hours (corresponding to the baud rate period described below), and immediately after that, the integral value is reset by the switch SW2.

In the above configuration, when the input signal Sinθ(n) is first input to the phase comparator 201, its output f(n) is multiplied by Cosφ(n-1) inputted via the delay element D1. )=Sinθ(n)・CO3−(n−1)
...(1)... (2) When the high frequency component of the first term of the above equation is suppressed from this f (n) using the LPF 202, h(n) is obtained. This signal is denoted as . Also, from θ(n)-φ(n-1), θ(n)
-φ(n-1)'-,O...(5) Here, the coefficient C4 is the fundamental angular frequency set in the adder of vCo, for example, CCITT Recommendation V2 Recommendation A21
For channel 1, C4,2πX10130XT
... (6). Here, in the above formula, 2-0.9065, LPF at C3-0,03
The output h (n) of 202 is shown in FIG. 2, and the configuration of this figure is the same as that of FIG. 8 described above.

As is clear from FIG. 2, quite large harmonic components are superimposed on the output data of the LPF 202. IDF2
04 is for suppressing this harmonic component.

By controlling the IDF 204 in the manner described below, a demodulated output waveform 84 close to the original data 82 as shown in FIG. 3 can be obtained.

Here, the IDF 204 forms an integral value of N pieces of data during a period of N7, which corresponds to the baud rate, but the point in time to start the integration is not certain, and even if the integration is performed every fixed period of time NT, the correct demodulation is not possible. If the output cannot be obtained, or if the PLL output has considerable harmonics as shown in FIG. 2, it will not be possible to detect the zero-crossing point and find the data conversion time. Therefore, a control algorithm for the integral operation of the IDF 204 by the control unit 205 to obtain such demodulated data will be described below.

The flow of the control algorithm is shown in FIG.

The flow of this algorithm is as follows.

1) First, the integral value r (i
) is initialized (step S1 in Figure 4), and then the eight data are set as integral tr(i) (steps S2 and S3 in Figure 4).
. At this time, the IDF 204 controls the switches SW1 and SW2 in FIG. 1 according to the software settings to integrate N pieces of data every sampling time T (because step 54r(i-1) in FIG. 4 is no longer O, Step S
(Proceed to step 5).

2) Under the condition that r(L-1)≠0 (step 34), the signs of r (i) and r(i-1) are compared (step S5). If the signs are the same, row+1 (step S6)
, if the signs are different, set ro=-1 (step S7).

Here, rO is a flag used for the following control.

3) The reduction ratio Dr of r (i) is determined by the following formula (step Sa).

Dr=r(i)/r(i-1)X
r O (7) In this equation, since the flag ro is multiplied, the value of Dr is expressed as an absolute value.

4) If the reduction ratio Dr is 0.8 or more (step S9), it is assumed that the integration is almost synchronized with the data transmission,
If it is less than that, correct it. Various correction formulas can be considered for calculating the value N for changing the integration timing, but in this embodiment, the following formula, which is the simplest, is used (step 510).

N ” N −□ f' o ” (o, a-Dr)2
X O,8 The value N' obtained in the above manner is
It is compared with N at 1, and if N'<N, the process goes to step 312, and if N<N', the process goes to step S13. In step Sll, N' data integral values are output, and in step S13, the first to (N'-N)th data are discarded, and the remaining N data are integrated. Thereafter, the above correction is repeated every time the value of r(i) decreases.

The above algorithm advances the timing of integration when the integral values decrease with the same sign, and retards the timing when they decrease with opposite signs, as shown in Figures 5 (A) and (B). be. In FIG. 5(A), N-Δ=N', and in FIG. 5(B), N+Δ=N'.

When the integration start timing is delayed by using a different sign, the data corresponding to the difference Δ between N' and N shown by the sign in FIG. 5(B) are discarded, and thereafter, N data integration is repeated after casting. Note that in FIG. 5, symbol I is the ideal integration timing calculated backward from the waveform zero-crossing point.

The above integration start timing control can be summarized as follows. That is, as is clear from the determinations in steps S5 and S9 in FIG. 4, the sign of the integral value is reversed (from + to -,
or vice versa), in which case the reduction ratio is 0.
．． If the changes are smaller than 8 and have the same sign, the integration timing is advanced as described above, and if the changes are of opposite signs, the integration timing is delayed.

FIG. 6 shows the correction results using this algorithm when the timing deviation is maximum (that is, NT/2 deviation).

As is clear from the figure, using this algorithm,
Although the timing is delayed by approximately NT/2 (half the baud rate), it is clear from the comparison with the original data 82 indicated by the broken line that the demodulated data 85 can be obtained accurately. It can be seen that almost all corrections can be made with just one data conversion.

In step S9 of FIG. 5, synchronization is considered when the reduction ratio Dr is 0.8 or more, but this means that when the maximum integral value when the timing is correct is 1, the minimum integral value is approximately This value was used because it is 0.8, and it is expected that it can take various values depending on the situation. Also, step SI
The correction equation (8) in O also uses a simple linear equation, and various equations can be considered depending on the situation, such as a quadratic equation. If a linear equation is used as described above, calculation time can be reduced.

Although the above-described algorithm was performed using software on a DSP, the same configuration can be used in a hardware configuration using an IC, although it is somewhat more complicated.

[Effects of the Invention] As is clear from the above, according to the present invention, in an FSK demodulator that demodulates an FSK-modulated signal and converts it into binary data, a PLL circuit that inputs a modulated signal, and a
1, D, and F connected to the output of the L circuit; D
, Since the configuration is adopted to extract the demodulated output from F,
I. Since D and F are used, harmonic components after passing through the PLL can be sufficiently removed, FSK demodulation that is resistant to disturbances can be performed, and the reliability of the demodulator can be greatly improved, which is an excellent effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of an FSK demodulator employing the present invention, Fig. 2 is a waveform diagram showing the output of the PLL section of the circuit in Fig. 1, and Fig. 3 is a waveform diagram showing the output of the PLL section of the circuit in Fig. 1. A waveform diagram showing the demodulated output, Fig. 4 is a flowchart showing the IDF algorithm of Fig. 1, Figs. 5 (A) and (B) are explanatory diagrams showing the principle of the algorithm of Fig. 4, Fig. 6 is a waveform diagram showing the output obtained when the integration timing has the maximum deviation, Fig. 7 is a block diagram showing the configuration of a conventional FSK demodulator, and Fig. 8 is a waveform diagram showing the configuration of a conventional FSK demodulator. FIG. 3 is a waveform diagram showing demodulation operation.

Claims (1)

[Claims] 1) In an FSK demodulator that demodulates an FSK-modulated signal and converts it into binary data, there is a PLL circuit to which the modulated signal is input, and an I.L. D. F(
I.Integrate and Dump Filter). D. An FSK demodulator characterized in that a demodulated output is extracted from an FSK demodulator. 2) The above I. D. The integration start timing of F is determined by I. D.
The FSK demodulator according to claim 1, wherein the FSK demodulator is determined according to a change between the latest integral value of F and the previous integral value.