JPH01296486A - Multi-port ram - Google Patents

Abstract

PURPOSE:To attain high speed reading even when writing and reading timing is overlapped by detecting the coincidence of writing and reading addresses and directly transmitting writing data through a transmitting means to a reading system. CONSTITUTION:In a multi-port RAM to independently execute the writing and reading of data, when X addresses from reading and writing X address buffers 13 and 21 and addresses from respective reading and writing Y address buffers 24 and 28 are coincident, a coincidence detecting output AC is outputted from an address coincidence detecting circuit 8. A short-circuiting circuit 9 of the transmitting means is controlled by this output AC and the writing data from a writing data driver 3 are directly transmitted to a reading system sense amplifier 5. Accordingly, even when the writing and reading timing of the data to the same memory cell of a memory cell array is overlapped, the high speed reading can be executed without waiting for the end of writing.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multi-port RAM (Random Access Memory) in which data can be read and written independently or in parallel, and also to a multi-port RAM (Random Access Memory) in which data can be read and written at high speed. Regarding read technology, the present invention relates to a technology that is effective when applied to a multi-port RAM having static type memory cells, for example.

[Prior art]

A static multi-port RAM can be used to increase the processing speed of microcomputers and even small and medium-sized computers.

This static multi-port RAM has a plurality of memory cells formed by connecting a write transfer gate and a read transfer gate to data input/output terminals of a static latch circuit, and the write transfer gate of a memory cell selected by a write address. A write system for giving write data to the write bit line connected to the memory cell, and a read system for reading externally the data given to the read bit line from the read transfer gate of the memory cell selected by the read address. The data write and read operations can be performed asynchronously and independently.

An example of a document describing static multi-port RAM is rV published in November 1987.
LSI SYSTEMS DESIGNJ P2O
- rEm beddad RAM described in P65
in Gate Arrays: Config
urability and stability
There is a J.

[Problem to be solved by the invention]

The present inventor has studied how to speed up the data read operation in a static multi-port RAM.

In a static multi-port RAM that can perform data write and read operations asynchronously and independently, write and read operations may be performed on the same memory cell at approximately the same timing. Considering this, under write priority, as is often the case, the access time for static multi-baud 1-RAM is
It is determined by the time until the information written in the memory cell to be accessed is read out again. In other words, when a write operation and a read operation are not performed on the same memory cell at the same timing, the access time is also constrained by the slow access time, and the overall access time according to the timing rules imposed on multi-baud 1-RAM is limited. Time becomes slower.

In order to eliminate this overall access time delay, it is possible to monitor the read address and write address, issue an alarm when they approach each other, and prohibit simultaneous access to the same memory cell. However, such a method has the drawback that a restriction condition is added to the access to the multi-port RAM, and access control to satisfy this restriction condition becomes complicated, and the multi-baud 1-RAM becomes difficult to use.

In this way, with conventional multi-port RAM, if you try to use it for high-speed access, you have to set a restriction condition that prohibits simultaneous write and read access to the same memory cell, and conversely, it is necessary to set a restriction condition that prohibits simultaneous write and read access to the same memory cell. The inventors have discovered that if ignored, there is a problem in that the data read operation speed must be reduced.

Furthermore, the inventor of the present invention precharges the bit lines and common data lines to one of the relatively high power supply voltage levels from the viewpoint of reducing power consumption in static multi-port RAM and preventing erroneous writing during data read operations. With this in mind, we have developed a memory cell structure in which a minute potential change corresponding to the memory cell data can be directly applied to the bit line precharged to the above power supply voltage, and a structure for the bit line near the power supply voltage. We also investigated other means that contribute to speeding up data read operations in static multi-port RAMs, such as the structure of a sense amplifier that can detect potential differences at high speed and amplify and output them.

An object of the present invention is to provide a multi-port RAM that can read data at high speed even when writing and reading operations to the same memory cell are performed at completely the same or partially overlapping timing.

Another object of the present invention is to speed up the data read operation in a multi-port RAM having a configuration in which the pin 1 line and the common data line are precharged to one relatively high power supply voltage level. The aim is to provide a memory cell structure and a sense amplifier structure that are possible.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, it is equipped with a write system and a read system that can perform data write and read operations asynchronously and independently, and in response to detecting a match between a write address and a read address, writes data given to the write system from the outside. It is provided directly to the readout system via the transmission means.

The above-mentioned transmission means is a switch element that transmits data given from the outside to the write system via a write common data line to a read common data line included in the read system, or a switch element that transmits data applied from the outside to the read common data line included in the read system, or a sense amplifier included in the read system from the write system. It can also be used as a switch element that transmits write data between the output cover and the output sofa. At this time, if the precharge levels of the write bit line and read bit line, as well as the write common data line and read common data line, correspond to one relatively high power supply voltage level applied to the static memory cell. In this case, it is preferable that the switching element constituting the transmission means be formed of a p-channel type MOSFET.

When the write data is directly provided to the read system via the transmission means, it is desirable to control all the read selectors to be non-conductive for selectively controlling the read bit line to the read common data line to be conductive.

In addition, data write and read operations can be performed asynchronously and independently for static memory cells coupled to the write bit line and the read bit line, with one relatively high power supply voltage level as the precharge level. Multi-port RA with write system and read system
In M, a write transfer gate for coupling the write bit line and the static memory cell is n.
A channel type MOSFET is used, and a p-channel type MOSFET is used as the readout 1 herans spread gate for coupling the readout bit line and the static memory cell.
The memory cell structure is as follows.

At this time, the sense amplifier included in the readout system is
It is preferable that the configuration includes a differential amplifier and a level shift circuit that level-shifts the precharge level of the read common data line to near the operating point of the differential amplifier and supplies the precharge level to the input terminal of the differential amplifier. Furthermore, a read select switch for selectively controlling the read bit line to be conductive to the read common data line is a p-channel type MO.
It is preferable to use an n-channel type MOSFET as a write select switch for selectively controlling the write focus line to be conductive to the write common data line.

[For production]

According to the above means, when a write operation and a read operation are performed on the same memory cell at the same timing, the transmission means directly supplies the write data to the input of the sense amplifier or data output buffer of the read system. The data given to the read system is read out at high speed while substantially satisfying the write priority condition, and writing to the memory cells is performed in parallel.

At this time, the sense amplifier to which write data is applied via the transmission means amplifies and outputs the data according to the original data read operation timing, so the transmission means specially sets the timing for transmitting the write data to the read system. No control is required.

When write data is applied from the write system to the read system with both the write common data line and the read common data line precharged to one relatively high power supply voltage level, the P-channel MO
As a result of the transmission means made up of SFETs having a large mutual conductance, this large mutual conductance works to improve the transmission performance of write data.

When the transmission means gives write data to the read system,
Since the read selector controls all the read bit lines to be non-conductive with respect to the read common data line, this non-conductive state avoids conflict between the memory cell data selected at this time and the write data given to the read system. It acts like this.

When memory cell data is applied to the read bit line in a state where both the write bit line and the read bit line are precharged to one of the relatively high power supply voltage levels, the read transfer transistor configured with a p-channel MOSFET As a result of the gate having a large mutual conductance, this large mutual conductance works to improve the transmission performance of memory cell data that changes near the power supply voltage. Furthermore, in a write operation, the write transfer gate, which is composed of an n-channel MOSFET connected to the write bit line that is discharged from the precharge level, has a large mutual conductance, and as a result, this large mutual conductance is discharged from the power supply voltage. It works to improve the performance of transmitting the level change of the write bit line and the level reached by the discharge to the static latch circuit. Similarly, the read select switch composed of a p-channel type MOSFET and the write select switch composed of an n-channel type MOSFET have a large mutual conductance during operation.
This large transconductance works to improve signal transmission performance.

The level shift circuit included in the sense amplifier converts minute level changes near the power supply voltage applied to the read common data line into level changes near the operating point where the amplification operation of the differential amplifier becomes highly sensitive. Therefore, the differential amplifier that receives this level-shifted voltage speeds up its amplification operation without waiting for the read bit line or read common data line itself, which has a large load capacitance, to reach the vicinity of the differential amplifier's operating point. Determine.

[Embodiment 1] FIG. 1 shows a block diagram of a static 2-port RAM which is an embodiment of the present invention.

The two-point RAM shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known MO8 integrated circuit manufacturing technique, although this is not particularly limited.

First, to explain the outline of the two ports 1 to RA, M of this embodiment, the memory cells forming the memory cell array 1 have a write transfer gate and a read transfer gate 1- connected to the data input/output terminals of the static latch circuit. Data is written to the memory cell through a write system coupled to a write transfer gate via a write bit line, and a read system coupled to a read transfer gate via a read bit line. The operation and read operation can be performed asynchronously and independently.

According to this embodiment, the write system selectively writes the write bit line to the write common data line CDw.

Write Y selector 2 that controls conduction to CDw, and write common data lines CDw and CDw to write data D
Write data 1- driven to complementary level according to in
It is composed of Lime 3 and others. The read system selectively reads the read bit lines and connects them to the common data line CDr.
, a read Y selector 4 that controls conduction to CDr, a read common data line CDr, a sense amplifier 5 that detects and amplifies the potential difference applied to CDr, an output latch circuit 6 that holds the output of the sense amplifier 5, and It is composed of an output sofa circuit 7 and the like.

The operation timing or operation cycle for the read system and the write system is not particularly limited, but is basically defined by the read clock CER for the read operation and the write I to clock CEW for the write operation,
The read clock CER and the write clock CEW have a meaning as chip enable signals in a tarlock-synchronized RAM. The read clock CER and read 1 lock CEW are asynchronous clocks, and their mutual phase relationship is determined by their supply conditions and internal and external delay conditions. As a result, it is generally assumed that read cycles and write cycles completely or partially overlap, and therefore write and read operations are performed on the same memory cell at completely the same or partially overlapped timing. Sometimes.

Regarding this point, in the multi-baud 1-RAM of this embodiment, the address coincidence detection circuit 8 detects the write address ΔW.
, ~Awn and the read addresses Ar1 to Arn, the write data given to the write system from the outside is directly transferred to the read common data line CDr of the read system via the short circuit 9 serving as a transmission means.
It is designed to be given to CDr. Write information applied to the read common data lines CDr, CDr via this short circuit 9 is supplied to the sense amplifier 5.

The information given to the read system in this way is read out at high speed while substantially satisfying the write priority condition, and writing to the memory cell to be accessed is performed in parallel.

Therefore, even if a write operation and a read operation are performed on the same memory cell at completely the same or partially overlapping timing, the data read operation speed will not decrease. It becomes possible to use a 2-point RAM with high-speed access without setting a restrictive condition that prohibits access.

The details of the 2-port RAM will be explained below.

Details of the memory cell array 1 are shown in FIG.

Although not particularly limited, the memory cell 10 may be a complementary MO8
Its basic configuration is a static latch circuit (hereinafter simply referred to as CMO8). The static latch circuit is P
A pair of CMOs composed of a channel type MOSFETQl and an N-channel type MOSFETQ2
It is constructed by cross-coupling one input terminal of the S inverter circuit and the output terminal of the other CMOS inverter circuit.

At each coupling node of MOSFETQI and Q2,
2 sets of N-channel type MOS FET Q3
.

Q4. , Q5. Q6 is combined. MOSFETQ3 and Q4 are used as write transfer gates, MOSFET
ETQ5 and Q6 are read transfer gates. Although one memory cell is representatively shown in FIG. 2, a plurality of memory cells]O are actually arranged in a matrix in the X and Y directions.

MO3FETQ3 forming write transfer gate in memory cells 1-OB2 arranged in matrix
．． The gate electrode of MOSFET Q4 is coupled to the write word line WLwα (α=, ~2I) in each X direction, and is connected to the MOSFET Q5.Q4 that constitutes the read transfer gate. Q6
The gate electrode is connected to the read word line WL for each X direction.
It is coupled to rα.

Then, MOSFETQ constituting the write transfer gate in the memory cells 10 arranged in a matrix
3. One of the train or source electrodes of Q4 is Y
Write bit lines BLwβ, BLwβ (β=1
~2 + n -11) and also constitutes a read transfer gate. One of the train or source electrodes of Q6 is coupled to read bit lines BLrβ and BLrβ in each Y direction.

The selection control of the read word lines WLr1 to WLr2I is performed by the read X address buffer 13 shown in FIG.
, a read X address decoder 14° and a read word driver 15.

The read X address buffer 13 converts the read address signals Ar, ~Ari into complementary address signals a r, , a
rl-ari, a r] and supplied to the read X address decoder 14. FIG. 4 shows an example of the configuration of the address buffer J3 corresponding to ]-bits, in which the address bit Arα is inverted by CMOS inverter circuits 16 to 18 in three stages in series to form an inverted bit arα, and The CMOS inverter circuits 6 and 17 form a normal bit arα.

The read X address decoder 14 receives complementary address signals ar, which are supplied from the read X address buffer 13.
, ar1 ari, ari are decoded to form selection signals WSr1 to WSr for selecting one of the read word lines WLr□ to WLr2+.

FIG. 5 shows an example of the configuration of the read X address decoder 14. The read X address decoder 14 shown in FIG. 5 is provided with a Nant gate 19 for every four pitches of the read word line, although this is not particularly limited, and each Nant gate 19 has an internal complementary address signal ar3. ar3~a
Predetermined bits of ri, ar; are supplied, and the output of one Nant gate 19 is set to a low level in accordance with the combination of levels of the supplied bits. The output of one Nant gate 19 is used to select a block of four word lines as one unit. To select one of the four word lines included in a unit block, select the lower two word lines.
The result of decoding by AND logic of bits ar□, ar, and ar218r2 is used. For example, an N-channel MOSFET QIO-Q13 receives four types of signals obtained as a result of decoding on its gate electrode individually.
is commonly connected to the output terminal of one Nant gate 19, MOSFETQIO is connected to the read word line W
Similarly, MOSFETQ11 is used as the output gate for the word line selection signal WSr corresponding to the word line WLr2 for reading, and MOSFETQ11 is used as the output gate for the word line selection signal WSr2 corresponding to the word line WLr2 for reading. The output gates of the word line selection signal WSr corresponding to the word line W I-r 3 and the MO3FET Q13 are the read word line W L r .

Low 1 (output gate 1 to line selection signal WSr4) corresponding to
It is said that

-"2 read word driver" -5 sets a predetermined one read word line to a selection level such as a high level based on the word line selection signals WSr, ~WSr2+ supplied from the read X address decoder 14. Drive to.

FIG. 6 shows an example of the configuration of the read word driver 15. Although not particularly limited, the word driver 15 includes a drive inverter circuit 20 that inverts and drives the word line selection signal WSrα via an n-channel gate MO3FETQ, which receives the read clock CER at its gate electrode.

Further, at the input of this drive inverter circuit 20, there is a p-channel type MOSFET Q16 for forcing the word line to a non-select level during the precharge period indicated by the low level of the read clock CER, and a p-channel MOSFET Q16 for forcing the word line to a non-select level, which is indicated by the word line selection signal WSrα. P-channel type MO3FETQ to maintain the state until the drive timing
17 are combined.

Selection control of the write word lines WLw□ to WLw, + is performed by the write X address buffer 21, write X address decoder 22, and write word driver 23 shown in FIG.

The write X address buffer 21 converts the write address signal Aw to the complementary address signal
It converts and outputs y a W1 to a W l + a W□, and can be configured similarly to that shown in FIG. 4.

The write X address decoder 22 receives the complementary address signal aw supplied from the write X address buffer 21.
1. Write word line selection signals WSw1 to WS for decoding aw, -awi, awi and selecting a predetermined one from write word lines WLw1 to WLW, I
Form w2I. As selection logic for this purpose, logic similar to the configuration shown in FIG. 5 can be adopted.

The write word driver 23 receives a word line selection signal WS supplied from the write X address decoder 22.
A predetermined one write word line is driven to a selection level such as a high level based on w, ~WSw2+, and can be configured in the same manner as in FIG. 6.

In FIGS. 1 and 2, 11 is a precharge circuit.

The precharge circuit 11 precharges the read bit lines BLrβ, BLrβ and the write bit lines BLwβ, BLwβ to one relatively high power supply voltage Vdd before a read or write operation. In this precharge circuit 11, the train electrode of a pair of P-channel precharge MOSFETQ8 whose source electrode receives the power supply voltage Vdd is connected to the read bit line B.
The train-24= electrodes of a pair of P-channel precharge MOSFETs Q9 are coupled to one ends of the write bit lines BLwβ and BLrβ and receive the power supply voltage Vdd at their source electrodes. be done. Precharge MOSFETQ8
is switch-controlled by the read clock CER, and is turned on in response to the precharge period instructed by the low level of the read clock CER, thereby pre-priming the read bit lines BLrβ and BLrβ to the power supply voltage Vdd. Charge. On the other hand, the precharge MOSFET Q9 is switch-controlled by the write clock CEW, and is controlled to be on in response to the precharge period instructed by the low 1 novel of the write clock CEW, so that the write bit line BL
Precharge wβ and BLwβ to power supply voltage Vdd.

When the write bit lines BLwβ, BLwβ and the read bit lines BLrβ, BLrβ are precharged to the power supply voltage Vdd, the write common data lines CDw, CDw and the read common data lines CDr, C will be described in detail later.
Dr is also precharged to the power supply voltage Vdd. In the read operation of memory cell data in this state, the read bit line and the read common data line CDr, CDr, which are made conductive with the selected memory cell, are connected to one of the selected MOSFETs which is turned on according to the information held in the memory cell.
Due to the discharge action by ETQ2, a slight level change starts from the power supply voltage Vdd. In a write operation, one of the write bit line and write common data line CDw, CDw, which are brought into conduction with the selected memory cell, is powered up to a level sufficient to invert the information held in that memory cell by the action of the write data driver 3. Voltage Vd
cl is discharged toward the ground potential Vss.

”2 Write bit line BLw1. BLw, -BLw,
tn-++, B L W2 (Tl-11 is commonly connected to the write common data lines CDw, CDw via n-channel type selection MOSFETs Q20 and Q20 forming the write Y selector 2, as shown in FIG. Read bit lines BLr□, BLr, ~BLr2 (n-hole, BLr, (nn is p-channel type selection MOSFET Q21.Q21 that constitutes the read Y selector 4)
It is commonly connected to read common data lines CDr and CDr via.

Here, the write bit lines BLwβ, BLwβ and the read bit lines BLrβ, BLrβ are both precharged to a relatively high level power supply voltage Vdd. Separately written common data line CDw.

CDw and read common data lines CDr and CDr are also precharged to the power supply voltage Vdd. In this state, when memory cell data is applied from the read bit lines BLrβ, BLrβ to the read common data lines CDr, CDr, the p-channel type selection MOS is controlled to be in the on state.
FETQ21°Q21 has a large mutual conductance, and as a result, this large mutual conductance works to improve the transmission performance of memory cell data that changes near the power supply voltage Vcld. Furthermore, during a write operation, one of the write common data lines CDw, CDw is finally discharged from the precharge level of the power supply voltage Vdd to the circuit ground potential Vss, and such discharge level is transmitted to the memory cell. is required to improve the reliability of write operations. At this time, the n-channel type selection MOS F E is controlled to be in the on state.
TQ 20.

As a result of increasing the mutual conductance of Q20,
This large mutual conductance causes the write common data line CDw to be discharged from the power supply voltage Vdd,
It works to improve the performance of transmitting the level change of CDw to the write bit line.

Selection MOSFET Q20 included in write selector 2
．． Write pin 1-line BLWβ, BLw via Q20
The selection control of β is performed by the write Y address buffer 24 and the write Y address decoder 25.

The write Y address buffer 24 converts the write address signal A w j −A w n into a complementary address signal a W J + a W J + a W n + a
Convert to W n and output. The write Y address decoder 25 receives complementary address signals a w j , a w j supplied from the write Y address buffer 24 .
”-a w n , awn is decoded and the write bit line BLw++B L wl-B L w2(n −
II, BLw2tn - write bit line selection signal BLSW for controlling a predetermined pair of selection MOSFETs Q20゜Q20 to be in the on state;
l−B L S w2+n −u is formed. For example, as shown in FIG. 2, the output of the Nant gate 26 is inverted by an inverter circuit 27 and the selection MOSFET Q20. Q2
The configuration for supplying the gate I to electrode of 0 to each writing pin 1 to
Logic provided for each line pair can be employed. In such address decoding logic, no matter what the combination of levels of write address signals Aw j -A w n is, any one write bit line selection signal is set to high level and a pair of selection MOSFETs Q20゜Q2
0 takes the on state.

Selection MOSFET Q21 included in read selector 4
, read bit lines BLrβ, BLrβ via Q21
The selection control is performed by the read Y address buffer 28 and the read Y address decoder 29.

The read Y address buffer 28 converts the read address signal A r j -A r n into a complementary address signal ar.
, ], ar, ] to a rn, a rn and output. The read Y address decoder 29 is the read Y address decoder 29.
Complementary address signals arj, ar, j~arn, arn supplied from the address buffer 28 are leveraged to read bit lines BLr□, BLr, ~BLr2tn
-n, B L t, (selection M corresponding to a predetermined pair from n-++, read focus line selection signal BLSr1~ for controlling 08FETQ21.Q21 to ON state
Form BLSr2+n-th.

For example, as shown in FIG. 2, the output of the Nant gate 30 is selected by the MOSFET Q21. It is possible to adopt a logic in which a configuration for supplying the gate electrode of Q2] is provided for each readout pin 1 to each line pair.

In this embodiment, each NAND game 1-30 included in the read Y address decoder 29 is supplied with the detection signal AC of the address coincidence detection circuit 8. This detection signal A
C is set to a low level when there is a match, and set to a high level when there is a mismatch. Therefore, when the write addresses Aw1 to Awn and the read addresses Ar, to A r n match, the output of the Nant gate 30 is forced to a high level, thereby all selection MOSFETs Q21 . Q21 is turned off, read common data lines CDr, CDr are connected to all read bit lines B L r2 . B L rl-B L r2f
When the write address and the read address match, the write data applied to the write common data lines CDw and CDw is connected to the read common through the short circuit 9. When transmitted to the data lines CDr, CDr, all the read bit lines are connected to the read common data line CDr.
, CDr, this non-conducting control state acts to avoid conflict between the read data of the memory cell selected at this time and the write data applied to the read system.

Note that in a state where the write addresses Aw□ to Awn and the read addresses Ar□ to Arn do not match, -3]- No matter what the combination of levels of the read address signals A r and j to Arn is, any one read bit is read. When the line selection signal is set to high level, a pair of selection MOSFs
ETQ21. By turning on Q21, the read bit lines BLr□, BLrx~BLr, fn-
++, B L I"2 (η-++ is the power supply voltage Vdd
In response to this, the read common data lines CDr and CDr are also precharged to the power supply voltage Vdd.

In FIG. 2, the write common data line CDw.

A short circuit 9 that selectively conducts CDw and read common data lines CDr, CDr is a pair of p-channel type transmission MOSFETs Q22. It is composed of Q22. Kono transmission MOS FET Q22, Q22 is
The switch is controlled by receiving the second detection signal AC at the gate electrode.

Transfer MOSFET Q22゜Q22 controlled to be on-state
The write data is read through the common data line CD
r, CDr, write common data lines CDw, CDw and read common data line CDr
, CDr are both write voltages. At this time, the p-channel type transmission MOSF that is controlled to be in the on state
ETQ22. As a result of the mutual conductance of Q22 being increased, this large mutual conductance changes from the vicinity of the power supply voltage Vdd to the write common data line CD.
It works to improve the transfer performance of complementary level changes of w and CDw.

FIG. 7 shows an example of the write data driver 3.

This write data driver 3 has two drive output stages.
The write data Din is supplied to one Nant gate 31 through two series CMOS inverters 33 and 34, and the other Nant gate 32 is supplied with the inverted level of the write data Din. is supplied via the CMOS inverter 33. Output control by the Nant gates 31 and 32 is performed by the write clock CEW and the write enable signal WE for instructing a write operation at a high level.

The control logic for this includes a two-manufactured Nantes gate 3F which is supplied with a write enable signal WE and a write clock CEW through two series CMOS inverters 35 and 36, and the output of this Nantes gate 37. is inverted by a CMOS inverter 38 and supplied to the other input terminal of the pair of NAND gates 31 and 32, respectively.

The write data driver 3 drives the write common data lines CDw and CDw to complementary levels in accordance with the write data Din when the write enable signal WE and the write 1 lock CEW are both set to high level. In other cases, write common data line CDw
, CDw are both equal to the precharge level at a power supply voltage V
Force to dd.

FIG. 8 shows an example of the address-number construction circuit 8. This address-number construction circuit 8 has complementary write addresses aw,, aw, ~awn, awn and complementary read addresses ar1. Matching of ar1 to arn and arn is determined by an exclusive OR 40 for each corresponding bit, and a NOR gate 41 determines whether each bit matches. When the write address and the read address all match, the outputs of the NOR games 1 to 41 are set to high level.

At this time, unless a write operation and a read operation are performed on the same memory cell at approximately the same timing, the transmission MOSFETQ22. In order to avoid the possibility of Q22 turning on, the output of the Norgelt 41 is input to the Nand gate 42 together with the write clock CEW, and the detection signal AC is formed through the NAND logic.

FIG. 3 shows an example of the sense amplifier 5 shown in FIG.

This sense amplifier 5 is connected to the read common data line CDr.
, the power supply voltage V which is the precharge level in CDr
It includes a differential amplifier 50 that detects and amplifies complementary level changes occurring near dd.

The above-mentioned minute level change near the power supply voltage Vdd occurring in the CDr is converted into a level change near the operating point where the amplification operation of the differential amplifier 50 is also highly sensitive, and this is applied to the input terminal of the differential amplifier 50. A level shift circuit 51 is provided.

Although not particularly limited, the differential amplifier 50 is an N-channel power switch MO8I? whose common connection end of the source electrode serves as a current source. Ground potential Vss via ETQ30
A pair of N-channel type inputs M forming a differential pair connected to
OSFETQ31. Q32, input MOSFET Q
31. A P-channel type MC SFET Q33.
It is formed by connecting the drain electrode of Q34. Karen 1~Channel type MOSFET Q33 that constitutes the mirror load
, Q34's source electrodes are connected to the power supply voltage Vdd, and the common connection end of their gate electrodes is connected to the input MOSFET Q31.
is coupled to the drain electrode of.

A pair of input terminals of the differential amplifier 50 are input MOSFETQ
31. This is used as the gate electrode of Q32. The output terminal of the differential amplifier 50 serves as the combined drain electrode of MOSFETs Q32 and Q34, and is coupled to the input terminal of the output inverter 52. The output voltage of the differential amplifier 50 is output from the output inverter 52.
The output of this output inverter 52 is determined by reaching a detectable level.

The power switch MOSFET Q30 is switch-controlled by a read clock CEH supplied to its gate electrode. The power switch MOSFET Q30 is turned on by the high level of the read clock CER to activate the differential amplifier 50. The output terminal of the differential amplifier 50 is charged to the power supply voltage VddL/bell by the P-channel MOSFET Q35 in response to the inactivation of the differential amplifier 50.

When the differential amplifier 50 is activated and a complementary signal is applied to the input terminal, MOSFETQ31. The drain-source current flowing through each of Q32 is different, and as a result, M
The current between 1 and the rain source of OSFETQ31 is MOS
By changing the voltage between the source and 1z rain of FETQ33,
The source-drain voltage of MOSFETQ34 is determined by this change and the change in the drain-source current of MO3FTE TQ32. For example, MOSFET
When the gate input voltage of Q31 is higher than the gate input voltage of MOSFET Q32, the drain voltage of MOS FET Q32, which is the amplified output of the differential amplifier 50, is higher than the MOSFET Q32.
It is made higher than the drain voltage of SFETQ31. Conversely, the gate input voltage of MO3FETQ32 is
When it is higher than the gate input voltage of Q31, the drain voltage of MOSFET Q32, which is the amplified output of the differential amplifier 50, is lowered compared to the drain voltage of MOSFET Q31.

In this way, the differential amplifier 50 consists of a pair of human-powered MOSFETQ
31. Due to the difference in gate input voltage of Q32, these MO
SFETQ31. The current change occurring in Q32 is
Since the change in voltage between the source and drain of TQ34 is taken out to its output terminal, the amplification degree or amplification sensitivity of the differential amplifier 50 is maximized by the differential amplifier 5.
The respective MOSFETs Q31. Q32. Q3
3. It is considered to be the saturation region of Q34. That is, in the amplification operation of the differential amplifier 50, the differential input level at which the sensitivity is the highest is approximately the intermediate level of the power supply voltage Vdd (voltage Vd d/
The complementary levels are centered around the two neighboring ranges).

The level shift circuit 51 transfers minute level changes in the vicinity of the power supply voltage Vdd as a precharge level occurring in the read common data lines CDr and CDr to the differential amplifier 51.
The amplification operation of 0 is also converted into a level change near the above operating point where sensitivity becomes high.

That is, this level shift circuit 51 includes, as a basic configuration, a pair of source follower circuits that change the output source potential to follow the input voltage, although this is not particularly limited. Specifically, the level shift circuit 51 includes an N-channel type drive as a current amplification transistor. The drain electrode of MOSFETQ40°Q41 is coupled to the power supply voltage Vdd, and one drive MO3FETQ4
0 is coupled to the read common data line CDr, and the gate electrode of the other drive MO3FETQ41 is coupled to the read common data line CDr. The drive MOSFET Q40. An N-channel MOSFET Q42 is connected to the source electrode of Q41. Q4.3 and their MOSFETs Q42. The gate electrode common connection end of Q43 is coupled to the drain electrode of MOSFET Q42 to form a current mirror circuit. MOSFETQ42. which constitutes this current mirror circuit. Q43
The common connection end of the source electrode of is connected to the ground potential Vss via an N-channel power switch MOSFET Q44. A pair of input terminals of this level shift 1-circuit 51 are connected to drive MOSFETQ4. It is considered as a gate electrode of O,Q41,
The drive MO which is one output terminal of the level shift circuit 51
The source electrode of SFETQ40 is connected to the gate electrode of input MOSFETQ31, which is one input terminal of differential amplifier 50, and the source electrode of drive M,08 FETQ41, which is the other output terminal of level shift circuit 51, is connected to differential amplifier 50. The input MOSFETQ is the other input terminal of
32 gate electrodes. Above power switch M
OSFETQ44 is switch-controlled by read clock GER supplied to its gate electrode, and is activated in synchronization with differential amplifier 50.

In this level shift circuit 51, the shift amount of the output voltage with respect to the input voltage is determined by the amount of shift of the output voltage with respect to the input voltage.
41) threshold voltage, constants determined by gate oxide film capacitance, carrier movement in the channel, etc., and M
It is determined by the drain-source current of OSFET Q40 (Q41), and in relation to the operating point of the differential amplifier 50, for example, in the case of a 5V power supply, it is set to about 2V to 2.5V. As a result, a minute complementary level change near the power supply voltage Vdd occurring on the read common data lines CDr, CDr can be reduced to an operating point near the middle of the power supply voltage Vdd, where the amplification operation of the differential amplifier 50 also becomes highly sensitive. This is converted into a level change in the vicinity, and this is converted into a level change in the differential amplifier 50.
is supplied to the input terminal of

In this way, the level shift circuit 51 handles minute level changes near the power supply voltage Vdd applied to the read common data lines CDr and CDr in the vicinity of the operating point (approximately The differential amplifier 50 that receives this level-shifted voltage is capable of converting it into a level change at a level that is half the level of the power supply voltage Vdd, so the differential amplifier 50 that receives this level-shifted voltage is connected to the read bit lines BLrβ, BLrβ, which have a large load capacity, the read common data line CDr, and the CDr itself. is the differential amplifier 5
To quickly determine an amplification operation without waiting for the vicinity of a zero operating point to be reached.

In particular, since the relationship between the input and output of the level shift circuit 51 is a source follower type, if the output load capacitance is small, the output response will be extremely fast.In this embodiment, the output load of the level shift circuit 51 is dynamic amplifier 50
Since it is only an input gate container, the level shift circuit 5
The time required for the level shifting operation by the controller is so short that it can be substantially ignored.

The output latch circuit 6 shown in FIG. 1 and FIG. This is so that it can be output externally even during periods of time.

For example, as shown in FIG. 3, the output latch circuit 6 is constituted by a latch circuit S4 that statically latches the output data of the output inverter 52 that is selectively supplied via the CMO3+-transfer gates 1 to 53. be done. The CMO3I-transfer gate 53 consists of a p-channel type MOSFET Q46 and an n-channel type MO3F.
It is constituted by the ETQ47 and is switch-controlled by the REIT clock CER and its inverted signal by the CMOS inverter circuit 55. The latch circuit 54 includes two stages of CMOS inverters 56 and 57 in series, and the subsequent stage CM
The output of the OS inverter 57 is sent to the previous stage CMOS inverter 5.
The output of the subsequent CMOS inverter 57 is fed to the output buffer circuit 7 such as the CMOS inverter 58.

Next, an example of a write operation and a read operation when the write address and read address do not match in the 2-point RAM of this embodiment will be described with reference to FIG. 9.

In Figure 9, the read clock CER and the write clock CE
W is out of phase, 5YCr beam is one cycle, S
YCw indicates a write cycle, and the low level period of the clock in each cycle is a precharge period.

Time t in FIG. When the write clock CEW is set to high level, the write address signal Aw at that time, ~
By operating the write X address buffer 21, the write , wα are driven to the selection level. Similarly, the write Y address buffer 24, the write Y address decoder 25, and the write Y selector 2 are operated according to the write address signal A w j −A w n, so that the write address signal A w j
- A predetermined pair of write bit lines BLwβ+ BLwβ corresponding to A w n are write common data lines CDw
, CDw conduction is controlled. At this time, the write data driver 3, which is enabled to operate by the high level of the write enable signal WE and the write clock CEW, connects the write common data line CD according to the write data Din.
w and CDw to complementary levels. By applying this drive signal to the pair of bit lines BLwβ and BLwβ, predetermined data is written into the memory cell selected in response to the write address signals Aw□ to Awn.

When the read clock CER is set to high level at time t1 in FIG. 9, the read address signals Ar1 to
The read X address bannofer] 3, the read input address decoder 14, and the read word driver 15 are operated according to the read address signal Ar.

~ One predetermined read word line WLr corresponding to Ari
α is driven to the selection level. Similarly, a read Y address buffer 28, a read Y address decoder 29,
By operating the read Y selector 4, a predetermined pair of read focus lines BLrβ, BLrβ corresponding to the read address signal Arj-Arn is controlled to be conductive to the read common data 1icDr, CDr. In this way, the read address signal Ar□~A
When the data of the memory cell selected in response to rn is transmitted to the read common data lines CDr, CDr, the sense amplifier 5 transfers the data to the read common data lines CDr, CDr.
Detect and amplify changes in the level of r. The amplified output from the sense amplifier 5 is taken into the output latch circuit 6, and is given to the outside as read data Dout from the output buffer 7.

In the read operation, the sense amplifier 5 immediately detects minute level changes in the vicinity of the power supply voltage Vdd of the read bit line and the read monitor data lines CDr and CDr by the action of the level shift circuit 51 and determines the output operation. The word line selection period is made relatively short, and correspondingly, the amplitudes of the read bit line and the read common data line, which are changed during data read operations, are also kept to a value closer to the power supply voltage Vdd.

The access time from when the read clock CER is asserted at time t until the read data D out is determined is tea□ in FIG.

Note that in the operation shown in the time chart of FIG. 9, the write address and read address do not match during the high level period of the write clock CEW, and the write address and read address do not match during the high level period of the write clock CEW.
Since the high level period of ER does not overlap with the high level period of write clock CEW, the detection signal AC is always at high level, and the transmission MOSFE included in the short circuit 9
TQ22 and Q22 maintain an off state.

Next, an example of an operation in which write and read operations are performed on the same memory cell at the same timing in the two-point RAM of this embodiment will be described with reference to FIG.

In FIG. 10, the phases of the read clock CER and write clock CEW are completely the same, and the read cycle 5YC
Let us take as an example a case where r and write cycle SYCw completely overlap.

Even when the high-level periods of write clock CEW and read clock CEH overlap, the basic operations for writing and reading are performed independently from each other as described above, but especially during the high-level period of write clock CEW, Write addresses Aw1 to Awn and read address A
When the address-number construction circuit 8 which monitors the coincidence of r1 to A r n determines whether the addresses match,
The detection signal AC is set to low level, and this low level detection signal AC is applied to the transmission MOSFETQ included in the short circuit 9.
22. Turn on Q22. This causes the on-state transmission MOSFET Q22. Q22 directly transmits a drive signal for the write data driver 3 according to the write data Djn from the write common data lines CDw, CDw to the read common data lines CDr, CDr.

The write data transmitted in this manner is applied to the sense amplifier 5, and is applied to the outside according to the original data read timing. The data given externally in this way substantially satisfies the write priority condition, and since the data read operation to the outside is performed in parallel with the write operation, it is not possible to read the data as before. In order to satisfy the write priority condition, there is no need to wait for confirmation of the read operation until the data once written is read again. Although this read operation does not utilize the read information of the memory cell, the access time tca2 at this time is the access time te described in FIG.
It will be slightly shorter than a1.

The readout pinot I line BLrβ shown in FIG.

A change in BLrβ indicates a state in which the information held in the selected memory cell is inverted by the write data Din at that time. That is, at first, the levels of the read bit lines BLrβ and BLrβ are changed according to the information held in the memory cell, but later, when the memory cell data is inverted by the write data Dcon, the read bit lines BLrβ are changed accordingly. , BLrβ level changes are reversed. As in the past, this read bit line BLr
β.

Read the level change of BLrβ and read the common data line CDr
, CDr, the determination of the read data Dout is delayed as shown by the broken line, and the access time tea3 becomes extremely long. It should be noted that the level changes of the read 7-bit lines BLrβ and BLrβ are illustrated in an exaggerated manner compared to the actual state.

Therefore, even if the two-bottom RAM of this embodiment is used for high-speed access with the access time tea1 explained in FIG. 9, a constraint condition is set that prohibits simultaneous write and read access to the same memory cell. Thereby, the port RAM of the second embodiment can be accessed at high speed under any access conditions.

[Embodiment 2] Data write and read operations are performed asynchronously and independently for static memory cells coupled to a write bit line and a read bit line using one relatively high power supply voltage level as a precharge level. A 2-port RA with a write system and a read system that can perform
In this case, a memory cell having the structure shown in FIG. 11 or FIG. 12 can be employed.

The memory cell 60 shown in FIG. 11 is different from the above-described memory cell 10 in that p-channel type MOSFETs Q50 and Q51 are used as read transfer gates.

Memory cell 6J- in FIG. 12 differs from memory cell 60 in FIG. 11 in that high resistance loads R, R are used.

When configuring a two-point RAM using the memory cells 60 and 61, the structure of the first embodiment can be applied as is, except that the selection level of the read word line WLrα is changed to low level.

In this embodiment, the write bit line BLwβ.

BLwβ and read bit line BLrβ, BT=rβ are both precharged to relatively high level power supply voltage Vdd. When memory cell data is applied to the read bit lines BLrβ and BLrβ in this state, the P-channel type MO3FETQ50. As a result of the mutual conductance of Q51 being increased, this large mutual conductance works to improve the transmission performance of memory cell data that changes near the power supply voltage Vdd. In a write operation, an n-channel type M for a write transfer gate configuration is made conductive to write bit lines BLwβ, BT, and wβ that are discharged from a precharge level.
OSFETQ3. As a result of Q4 having a large mutual conductance, this large mutual conductance serves to improve the performance of transmitting a level change of the write bit line discharged from the power supply voltage Vdd to the static latch circuit.

In this type of precharging the write bit line and the read bit line to one of the relatively high power supply voltages Vdd, the write 1 transfer gate is configured with an n-channel type MOSFET, and the read transfer gate is configured with a p-channel type MOSFET. By using MOSFETs, it becomes possible to directly apply a minute potential change corresponding to the memory cell data to the read bit line precharged to the power supply voltage Vdd, thereby improving the data read speed. At this time, write performance is not sacrificed.

In particular, when a memory cell is configured with a CMOS static latch circuit as shown in FIG. 11, the write and read transfer gates are also CMO8 circuits, so the diffusion layer of the static latch configuration transistor is stretched and utilized to transfer the transfer gate. It becomes possible to form the configuration transistors, and the layout of the memory cell configuration transistors becomes easier.

The memory cell structure shown in FIGS. 11 and 12 is the sense amplifier 5 described in Embodiment 1, and the read Y selector 4 constituted by a p-channel MOSFET.
By combining this with the write Y selector 2 constituted by an n-channel type MO8FET, it becomes possible to further speed up the data read operation of the 2-port RAM.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

In Embodiment 1, the transmission means is a p-channel type transmission MOSFET Q22. Although explained as Q22, the write data may be given to the output launch circuit 6 as shown in FIG. That is, the write common data lines CDw, CDw are coupled to the input of the CMOS inverter 56 and the output of the CMOS inverter 57 constituting the latch circuit 54 via the p-channel type transmission MO3FETs Q22', Q22'.

Further, in the first embodiment, the read Y address decoder 29 is used which controls all the selection MOSFETs Q21 constituting the read Y selector 4 to be in the off state in response to the ON operation of the transmission MOSFET Q22°Q22.
If the drive capacity of the write data driver is extremely large compared to the drive capacity of the memory cell, select MOSFETQ.
In some cases, such consideration may not be given to 21.

The present invention is not limited to a 2-point RAM, but can be applied to a 3-point RAM by using a memory cell as shown in FIG. 14, and even to a multi-port RAM having more ports. The memory cell shown in FIG. 14 includes p-channel type MOSFETs Q54 . Q55 constitutes a first read port, and a p-channel MOSFET Q56. Q57 constitutes the second read port I-, and the n-channel MOSF is coupled to the write word line WLwα.
ETQ58. Q59 constitutes a write port.

By applying the memory cell shown in FIG. 14 to Example 1, a 3-point R
When configuring an AM, a circuit configuration as shown in FIG. 15 can be adopted as the address matching detection circuit. 1st
The address-number configuration circuit shown in FIG. -61 is determined. Similarly, the read address and write address regarding the second read port are determined by exclusive OR 62 for each corresponding pin point, and the match of each bit is determined by NOR game 1-63. Then, a logical sum 64 is performed on the determination results of both NOR gates, and a write clock CEW and a NAND logic 65 are performed on the result to form a detection signal AC.

Note that in the second embodiment, the transmission means is not an essential component.

Although the invention made by the present inventor is applied to a two-point RAM, which is the background field of application, the present invention is not limited thereto, and can be applied to other multi-port RAMs and even gates. It can also be widely applied to arrays. The present invention can be applied at least to conditions where write operations and read operations can be performed independently.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

(1) When a write operation and a read operation are performed on the same memory cell at approximately the same timing, the transmission means directly supplies the write data to the input of the sense amplifier or data output buffer of the read system. The data given to the memory can be read externally at high speed while substantially satisfying the write priority condition. Therefore, a multi-vote RAM can be used for high-speed access without setting a restrictive condition that prohibits simultaneous write and read access to the same memory cell.

(2) In a configuration in which the transmission means transmits data given to the write system from the outside from the write common data line to the read common data line, the sense amplifier to which the write data is supplied via this transmission means is used for the original data readout. Since the amplification operation is performed according to the operation timing, the transmitting means does not need to specially control the timing of transmitting the write data to the reading system, and the configuration of the transmitting means can be extremely simplified.

(3) When write data is given from the write system to the read system via the transmission means in a state where the write common data line and the read common data line are precharged to one of the relatively high power supply voltage levels,
As a result of the large mutual conductance of the transfer means made up of P-channel MOSFETs, this large mutual conductance works to improve the transfer performance of write data, thereby allowing data to be written to the same memory cell at approximately the same timing. When a read operation is performed, it is possible to further speed up the read operation.

(4) When the transmission means supplies write data to the read system, the read selector controls all the read bit lines to be non-conductive with respect to the read common data line, so that this non-conductive state is selected at this time. It works to avoid conflicts between memory cell data and write data given to the read system, thereby further speeding up read operations when write and read operations are performed on the same memory cell at roughly the same timing. be able to.

(5) In a multi-port RAM that can independently perform write and read operations by pulling the write bit line and the read bit line to one of the relatively high power supply voltage levels, The transfer gate is an n-channel MOSFET, and the readout transfer gate is a p-channel MOSFET.
By adopting a memory cell structure of T, when memory cell data is given to the read bit line precharged to the power supply voltage,
The read transfer gate composed of ET has a large mutual conductance, and as a result, this large mutual conductance works to improve the transfer performance of memory cell data that changes near the power supply voltage, and is precharged to the power supply voltage. It becomes possible to directly apply a minute potential change corresponding to memory cell data to the read bit line, making it possible to improve the data read speed. At this time, n-channel type M
Write performance is not sacrificed due to the operation of the write-only I-transfer gate consisting of an OSFET.

(6) In a multi-port RAM in which the write bit line, the read bit line, and the write common data line and read common data line are precharged to one relatively high level power supply voltage, the read bit line is connected to the read common data line. The read select switch for selectively controlling conduction to the data line is a p-channel MOS.
If the write select switch for selectively controlling conduction of the write bit line to the write common data line is an n-channel type MOSFET, it will be in the on state when memory cell data is applied from the read pinto line to the common data line. p-channel type M controlled by
The read select switch made of an OSFET has a large mutual conductance, and this large mutual conductance acts to improve the transmission performance of memory cell data that changes near the power supply voltage. In addition, an n-channel MOSF that is controlled to be in an on state during a write operation
The mutual conductance of the write selector made of ET is increased, and as a result, this large mutual conductance improves the performance of transmitting the discharge level of the write common data line discharged from the power supply voltage to the write focus line. Therefore, compared to the case where each select switch is formed of a CMOS transfer gate, the number of these constituent elements can be halved without impairing the data transfer characteristics.

(7) The level shift circuit included in the sense amplifier handles minute level changes near the power supply voltage applied to the read common data line, and changes the level near the operating point where the amplification operation of the differential amplifier becomes highly sensitive. Therefore, the differential amplifier that receives this level-shifted voltage can perform its amplification operation without waiting for the read bit line or read common data line itself, which has a large load capacitance, to reach near the operating point of the differential amplifier. can be determined at high speed, thereby achieving high-speed data read operations.

Furthermore, the word line selection operation can be completed without the signal line with a large load capacitance connected to the memory cell reaching the operating point of the differential amplifier.
The amplitude of the read bit line in the data read operation can be kept to a change close to the power supply voltage, making it possible to speed up the precharging operation of the read bit line and the read common data line, as well as precharging the signal line. Power consumption required for charging operation can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the entire 2-point RAM as an embodiment of the present invention. FIG. 2 is the main part of the 2-point RAM shown in FIG. 1, from the memory cell to the write system and read system. 3 is a circuit diagram from the 2-point RAM sense amplifier to the output sofa circuit in FIG. 1, FIG. 4 is a circuit diagram showing an example of the address buffer, and FIG. 5 is a circuit diagram of the address decoder A circuit diagram showing an example, FIG. 6 is a circuit diagram showing an example of a word driver, FIG. 7 is a circuit diagram showing an example of a write data driver, and FIG. 8 is a circuit diagram showing an example of an address-multiple output circuit. , FIG. 9 is a timing chart for explaining an example of a write operation and a read operation when the write address and read 71~res do not match, and FIG. Timing Chart 1 for explaining an example of the operation performed in each case Figures 11 and 12 show MOS transistors forming a write transfer gate and a read transfer gate 1 with different conductivity types. FIG. 2 is a circuit diagram showing an example of a memory cell structure. Figure 14 is a circuit diagram showing another example of the transmission means.
The figure is a circuit diagram showing an example of a memory cell structure that can be adopted in a 3-port RAM, and Figure 15 is an example of an address-to-number output circuit in a 3-port RAM that uses the memory cell shown in Figure 14. FIG. memory cell array, 2...Write Y selector diagram, evening, 3...Write data driver, 4...Read Y selector, Q21 - Selection MOSFET, 5...Sense amplifier, 6...Output latch, 7 Output buffer circuit , 8...address-number circuit, 9 short circuit, Q22
・・Transmission MOSFET, CER・Leat clock, CE
W write clock, AC detection signal, Ar1 to Ar
n・Read address, Aw□~Awn...Write address, WLr1~WLr2+...Read work line, WLw1~WLw2+...Write word line, B L rl, B L r□-B T-1 -2in
-1] + BL r2+n -++- readout focus line, BLw. BLw, ~BLw,,tn-n,BLW2[η-mouth...
・Write bit line, CDw, CDw...Write common data line, CDr, CDr...Read common data line, 1o...Memory cell, 11...Precharge circuit, 13 Read X address buffer, 14...Read X address decoder, 15...Read word driver, 21.Write X address buffer, 22...
Write X address decoder, 23 - Write word driver, 24... Write Y address buffer, 2
5. Write Y address decoder, 28... Read Y
Address buffer, 29/read Y address decoder, 50 differential amplifier, 51 level shift circuit. Fig. 13 Fig. 14 Lr2cX Lrt91 Fig. 15 1, 6°

Claims (1)

[Scope of Claims] 1. A write system for providing write data to a write bit line of a memory cell selected by a write address, and a write system for externally supplying data to a read bit line from a memory cell selected by a read address. In a multi-port RAM that is equipped with a read system for reading data and is capable of writing and reading data independently, the address match detecting means detects a match between a write address and a read address, and the address match detecting means detects a match between a write address and a read address. A multi-port RAM characterized in that it is provided with a transmission means for directly transmitting write data given to a write system from the outside to a read system in response to coincidence detection. 2. Claim 1, wherein the transmission means is a switch element that transmits data externally applied to the write system via a write common data line to a read common data line included in the read system. Multi-port RAM as described in section. 3. The memory cell includes a static latch circuit,
The write bit lines and read bit lines that are individually coupled to the data input/output terminals of this memory cell, and the write common data lines and read common data lines that can be selectively made conductive with these, have relatively low levels. The switch element is precharged to one of the higher power supply voltage levels, and serves as a transmission means for selectively controlling the write common data line and the read common data line to be conductive, and is constituted by a p-channel MOSFET. A multi-port RAM according to claim 2, characterized in that the multi-port RAM comprises: 4. In response to the coincidence detection between the write address and the read address by the address coincidence detection means, the read selector for selectively making the read bit line conductive and the read common data line conductive can be controlled to make all the read selectors non-conductive. The multi-port RA according to claim 2, characterized in that it is equipped with an address decoder.
M. 5. The above-mentioned transmission means is a switch element that transmits write data to an output latch circuit provided between the output of a sense amplifier included in the read system and the input of a data output buffer circuit. The multi-port RAM described in the first range. 6. A write system that can independently perform data write and read operations for static memory cells coupled to a write bit line and a read bit line, using one relatively high power supply voltage level as a precharge level. A multi-port RAM comprising a readout system and a readout system,
The write transfer gate for coupling the write bit line and the static memory cell is an n-channel MOSFET, and the read transfer gate for coupling the read bit line and the static memory cell is a p-channel MOSFET. A multi-port RAM characterized by: 7. The read system includes a sense amplifier coupled to the read common data line, and the sense amplifier shifts the precharge level of the differential amplifier and the read common data line to near the operating point of the differential amplifier. 7. The multi-port RAM according to claim 6, further comprising a level shift circuit for supplying signals to input terminals of said differential amplifier. 8. A read select switch for controlling the read bit line to be selectively conductive to the read common data line is configured by a p-channel MOSFET, and a read select switch for selectively controlling the conductive state for the write bit line to the write common data line. 8. The multi-port RAM according to claim 6, wherein the write select switch is constituted by an n-channel type MOSFET.