JPH01296488A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device that can perform a high-speed and reliable read operation.

[Prior Art] FIG. 3 is a circuit diagram showing a part of a conventional static random access memory (hereinafter abbreviated as SRAM).

Referring to FIG. 3, this SRAM is connected to a memory array including memory cells 4, a row decoder 8 for selecting word lines WLI to WLn, an I/O line, and an I/O line. A sense amplifier circuit 3 that amplifies the signal read from the cell 4 and outputs it to the RWD line (data bus line), a latch circuit 7 that latches the signal output from the sense amplifier circuit 3, and an output that outputs the signal. and a huffer circuit 6.

The sense amplifier circuit 3 includes a differential amplifier 30 that differentially amplifies an I/O line and a voltage signal between the I/O lines;
0 output and the RWD line, and a hash buffer circuit 34 for driving the RWD line. The output buffer circuit 6 includes a NAND gate G1 and a NOR gate G2 connected to one input to the RWD line and the other input connected to receive the output enable signals OE and OE, and the power supply and the ground. and a series connection of a P-channel transistor 61 and an N-channel transistor 62 connected to each other. The read data signal DQ is output from the connection point between transistors 61 and 62.

FIG. 4 is a timing diagram illustrating the operation of the SRAM shown in FIG. 3.

Next, the operation will be explained with reference to FIGS. 3 and 4.

When an externally applied address signal changes, an address transition detector (hereinafter abbreviated as ATD) circuit detects this and generates an ATD pulse. The internal synchronization signal generation circuit generates various internal synchronization signals (signals BLEQSWLEN, l0EQX) in response to this ATD pulse.
SAEN and 5AEQ).

First, when the externally applied address signal An changes, the bit line equalize signal BLEQ and the I/O line equalize signal l0EQ are output. Bit line and I
The /O lines are equalized in response to these signals.

Furthermore, word line enable signal WLEN and sense amplifier enable signal 5AEN are output, and row decoder 8 and differential amplifier 30 are activated.

The row decoder 8 and column decoder (not shown) then bring one word line (eg WLl,) and one column select line (eg C0LI) high. As a result, one memory cell 4 is selected, and the data signal stored there causes an I/O line to be connected to the I/O line.
A potential difference occurs between the O lines.

At this time, the If power of the differential amplifier 30 and the RWD are already
The lines are equalized. Also, transistors 3 and 32 are turned on in response to a high-level sense amplifier equalize signal 5AEQ, and transistor 33 is turned on in response to a high-level sense amplifier enable signal 5AEN.

After a sufficient potential difference is generated between the I/O line and the I/O line for the differential amplifier 30 to sense, the signal 5AEQ changes to a low level to equalize the output of the differential amplifier 30 and to equalize the RWD line. Equalization ends. The differential amplifier 30 amplifies the potential difference between the I/O line and the 〒/O line, and
supply data signals to the line. The data signal applied to the RWD line is outputted via the output buffer circuit 6 and latched by the latch circuit 7.

Generally, the equalization level of the output of the differential amplifier 30 and the RWD line -5 is set to an intermediate level within the voltage level range of the data signal. this is,
This is to perform a high-speed read operation by shortening the width of change in voltage level after a data signal is applied. Therefore, it is necessary to finish equalization after a voltage difference appears between the I/O lines due to signals from the memory cells.

[Problem to be solved by the invention] However, as shown by the dotted line in FIG.
If the appearance of the potential difference from the memory cell between the I/O lines and the I/O lines is delayed and equalization is completed first, the following inconvenience will occur. That is,
A mismatch occurs between the output of the differential amplifier 30 and the logic threshold of the hash buffer circuit 34, and a false data signal as shown by the arrow in the figure is output. Here, if the level of the true data signal and the level of the color data signal are different, there is a problem that it takes time to invert the level, and the successive output speed decreases rapidly.

The cause of the delay in the appearance of the potential difference between the Ilo and I/O lines is that the voltage change on the word line is delayed due to variations in the characteristics of the transistors that make up the internal synchronization signal generation circuit for generating the internal synchronization signal. An example of this is the variation in characteristics of the various circuits included in the circuit.

Furthermore, in order to avoid the above-mentioned inconvenience, if the trailing edge of the sense amplifier equalize signal 5AEQ is delayed to lengthen the equalization period, false data signals will not be generated, but access will be delayed by the delayed time and the equalization will be delayed. The problem is optimizing the timing.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that can read data signals accurately and at high speed.

[Means for Solving the Problems] A semiconductor memory device according to the present invention has an I/O device connected to a memory array and transmitting data signals stored in memory cells.
/O line means, amplification means for amplifying the data signal input to the memory cell transmitted via the I/O line means, and a bus line for outputting the output signal of the amplification means to the outside. an equalizer for equalizing the data bus means in response to the timing at which the data signal stored in the memory cell is applied to the I/O line means and the internal synchronization signal from the internal synchronization signal generation means; It includes equalization control means for outputting a control signal, and equalization means for equalizing the data bus means to a predetermined voltage in response to the equalization control signal.

[Operation] In the semiconductor memory device according to the present invention, the equalizing means controls the data bus means in response to the equalization control signal output in response to the timing given to the data signal/O line means stored in the memory cell. equalize to a predetermined voltage.

Since the equalization of the data bus means is performed in response to the timing of the data signal applied from the memory cell to the I/O line means, generation of false data signals is prevented and only correct data signals are provided to the data bus means. Therefore, high-speed read operation is possible.

[Embodiment of the Invention] FIG. 1 is a circuit diagram showing a sense amplifier circuit showing an embodiment of the invention.

Referring to FIG. 1, this sense amplifier circuit 3 has an I/O line and an I/O line, compared to the conventional one shown in FIG.
A differential signal detection circuit 1 connected to the O line is newly provided, and a P-channel transistor 32 is connected between the input and output of the pass buffer circuit 34, and its gate receives the output signal EQ of the differential signal detection circuit. connected like this.

The differential signal detection circuit] is connected to the I/O line and the differential amplifier/O having the same circuit configuration as the differential amplifier 30, and the differential amplifier/O between the two outputs of the differential amplifier/O. and an N-channel transistor 11 for equalizing these outputs in response to a sense amplifier equalize signal 5AEQ. P-channel transistors 12 and 13 are connected to receive the sense amplifier equalize signal 5AEQ, and an N-channel transistor 14 is connected between the output of the differential signal detection circuit 1 and ground, and the gate thereof is connected to receive the sense amplifier equalize signal 5AEQ. including.

FIG. 2 is a circuit diagram for explaining the operation of the sense amplifier circuit of FIG. 1.

Next, the operation will be explained with reference to FIGS. 1 and 2.

Sense amplifier enable signal 5AEN and sense amplifier equalize signal 5AEQ are output from the internal synchronization signal generation circuit in response to the ATD pulse obtained by detecting a change in the address signal as described above. Differential amplifier]0 and 30 are activated in response to signal 5AEN.

Also, transistors 11 and 31 are connected to high level signal 5.
Since it is turned on in response to AEQ, the outputs of differential amplifiers /O and 30 are equalized to an intermediate level.

= /O- Since the output signals SA2 and SA2 of the differential amplifier /O are at the same level, transistors 12 and 13 are turned off, and transistor 14 is turned on in response to the high level signal 5AEQ. Therefore, the gate of transistor 32 is brought to ground level and turned on. This results in
The input and output of the pass buffer circuit 34 are equalized. Further, since the transistor 33 is also turned on in response to the high level signal 5AEN, the RWD line is also equalized to an intermediate level.

The circuit is configured such that when the RWD line is equalized, transistors 61 and 62 forming the final stage of output buffer circuit 6 are both turned off. That is,
Logic threshold value vT of NAND gate G1, (Gl) or R
It is set higher than the equalization level of the WD line, and the logical threshold VTH (G2) of the NOR gate G2 is set lower than the equalization level of the RWD line. Therefore, the output terminal of the output buffer circuit 6 is brought into a high impedance state at this time, and the level of the previously read data signal is held by the self-capacitance of the output terminal.

Differential amplifiers /O and 30 produce no voltage difference between their two outputs when the voltage levels on the I/O and I/O lines are the same. Therefore, the outputs of the differential amplifiers 0 and 30 are held at the same voltage level as the equalization level until a voltage difference occurs between the I/O lines due to the data signal from the memory cell. As a result, transistor 1
2 and ]3 remain off, so even if the signal 5AEQ changes to a low level and turns off the transistor 14, the signal E remains off.
Q is the ground level.

When the signal 5AEQ changes to low level, the transistor 11
and 31 are turned off, and differential amplifiers /O and 30 are connected to the I/O line and I/O by the data signal from the memory cell.
The potential difference appearing between the O lines is amplified and signals SAI, SAT, SA2 and 100 watts of contradictory voltage levels are output, respectively. Also, the transistor 14 has a signal 5AEQ
off in response to. One of the transistors 12 or 13 is turned on in response to signals SA2 and SA2 having different voltage levels output from the differential amplifier ]0, and the signal EQ changes to high level.

The transistor 32 is turned off in response to the high level signal EQ, thereby completing equalization of the pass buffer circuit 34 for driving the RWD line. At this time, the differential amplifier 30 outputs an output signal τA corresponding to the data signal read from the memory cell. Since we have already output
The hash buffer circuit 34 never outputs a false data signal. Therefore, since the RWD line is brought directly from the equalization level (intermediate level) to the correct voltage level indicated by the data signal, an accurate read operation can be performed without delay.

Therefore, even if there is a delay in the appearance of the data signal from the memory cell on the I/O line and the I/O line, the differential signal detection circuit detects the signal (potential difference) that appears between the I/O line and the I/O line. Since the transistor 32 is controlled in response to the timing of ), generation of false data signals can be prevented.

Note that the sense amplifier circuit 3 shown in FIG. 1 is only one embodiment of the present invention, and other circuits may be used to respond to the I/O line and the timing of the data signal appearing on the I/O line. A similar effect can be obtained by controlling the timing of equalizing the RWD line.

Further, although a P-channel transistor is used as the transistor 32, an N-channel transistor can also be used if the differential signal detection circuit 1 is configured to invert the phase of the signal EQ.

[Effects of the Invention] As described above, according to the present invention, the equalizing means adjusts the data bus means to a predetermined voltage in response to the timing applied to the data signal stored in the memory cell or the I/O line means. Since equalization is performed, a semiconductor memory device that can read data signals accurately and at high speed can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a sense amplifier circuit showing an embodiment of the present invention. FIG. 2 is a timing diagram for explaining the operation of the sense amplifier circuit shown in FIG. 1. FIG. 3 is a circuit diagram showing part of a conventional SRAM. FIG. 4 is a timing diagram illustrating the operation of the SRAM shown in FIG. 3. In the figure, 1 is a differential signal detection circuit, 3 is a sense amplifier circuit, 4 is a memory cell, 6 is an output buffer circuit, 7 is a latch circuit, 8 is a row decoder, /O and 30 are differential amplifiers, and 34 is a pass It is a buffer circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] Internal synchronization signal generation means for outputting an internal synchronization signal necessary for a read operation; a memory array including memory cells for storing data signals; I/O line means for conveying a data signal transmitted through the I/O line means; amplification means connected to the I/O line means for amplifying a data signal stored in a memory cell conveyed via the I/O line means; data bus means connected to the output of the amplification means and forming a bus line for outputting the output signal of the amplification means to the outside; and data signals stored in the memory cells are applied to the I/O line means. equalization control means for outputting an equalization control signal for equalizing the data bus means in response to timing and an internal synchronization signal from the internal synchronization signal generation means; and equalization control means responsive to the equalization control signal from the equalization control means. and equalizing means for equalizing the data bus means to a predetermined voltage.