JPH01297732A - Interrupt control method - Google Patents

Abstract

PURPOSE:To permit an interruption processing program stored in a prescribed bank to execute immediately without using none of common memory areas other than a memory bank when interruption is generated while executing a processing program in an arbitrary bank by storing a bank switching control program in the prescribed area of the memory bank. CONSTITUTION:The interruption processing program 13 for specified interruption is stored in the addresses (X-W) of the memory bank 3. When the specific interruption is generated while executing the processing program of the memory bank 1, an interruption control program starting from an address X in the same bank is executed first, and a jump destination bank number BANK No.3 and a jump destination address Y are saved at an AL register and a BX register, respectively. A bank switching manager, when its own bank number No.1 being saved at the AL register after being saved, for example, at an AH register as a return bank number, jumps to a second program by deciding the jump destination bank No. saved at the AL register.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an interrupt control method when an interrupt occurs in a system equipped with a program memory consisting of a plurality of memory banks.

(b) Conventional technology As disclosed in Japanese Patent Application Laid-open No. 57-30050, in a system in which processing programs are stored in multiple memory banks, interrupts are conventionally stored in a common memory area outside the memory banks. A processing program or an interrupt bank control program for specifying a memory bank in which an interrupt processing program is stored is stored, and control when an interrupt occurs is performed based on the program.

(c) Problems to be Solved by the Invention If a common memory area for storing programs related to interrupt processing cannot be provided outside the memory bank due to system circumstances, the interrupt control method disclosed in the above publication may be used. Therefore, the same interrupt processing program had to be stored in each memory bank. Therefore, there is a problem that the area for storing the processing program becomes narrow.

(d) Means for Solving the Problems The first method of the present invention includes a plurality of memory banks for storing processing programs, and stores a bank switching control program in a specific same address area of the plurality of memory banks. and predetermined memory/data of the plurality of memory banks.
Interrupt control that stores an interrupt processing program in a storage device, and stores destination bank information indicating the predetermined memory bank and/or the address of the interrupt processing program in a memory bank other than the predetermined memory bank. When a program is stored and a processing program in a memory bank other than the predetermined memory bank is being executed, if an interrupt occurs, the program moves to the bank switching control program after executing the interrupt control program, and the process program in the memory bank other than the predetermined one is executed. Information indicating the bank is saved as return bank information, switching to the predetermined memory bank is performed, and after switching, the interrupt processing program is called and executed based on the contents of the storage means, and after execution, the return bank information is saved. Switch to memory bank,
The above problem is solved by an interrupt control method that returns to the processing program after switching.

Further, a second method of the present invention includes a plurality of memory banks for storing processing programs, stores a bank switching control program in the same specific address area of the plurality of memory banks, and stores the bank switching control program in the same specific address area of the plurality of memory banks. When an interrupt processing program is stored in a predetermined memory bank and a processing program in a memory bank other than the predetermined one is executed,
When an interrupt occurs, the program moves to the bank switching control program, which saves information indicating its own memory bank as return bank information, switches to the predetermined memory bank, and after switching, executes the bank switching control program. The above problem is solved by an interrupt control method that calls and executes a processing program, switches the return bank information to a memory bank after execution, and returns to the processing program after switching.

(*) Effect In the present invention, an interrupt occurs while an interrupt processing program stored in a predetermined bank is being executed while a processing program in an arbitrary bank is being executed, without using any common memory area other than the memory bank. It will be available when you do so. In the first method, the bank switching control program can be used in common for a plurality of different interrupts or interrupt processing programs of different banks, and in the second method, the processing steps can be shortened.

(F) Embodiment FIG. 3 is a block diagram showing a hardware configuration for realizing an embodiment of the present invention, in which (1) is an Intel 8086 CPU, (2) is an address bus, and (3) is a hardware configuration for realizing an embodiment of the present invention. 〉 is a data bus, and (4〉 is a ROM serving as a memory bank 1 for storing the first processing program.

(5) is a memory bank 2 that stores the second processing program.
(6) is a ROM as a memory bank 3 that stores the third processing program, and (7) is a main memory that stores various data, tables loaded from external devices, user programs, etc. R
AM, (8) is a bank register in which bank specification data specifying a bank is set when cpU(t) executes a bank switching instruction described later; , a decoder for selecting one of the memory banks (10>) inputs multiple external interrupt signals, outputs a vector address corresponding to the type of interrupt, and also issues an interrupt signal INT to the CPU (1). In the interrupt controller that is generated, an interrupt vector table is prepared in the RAM (7) in which program addresses to be executed are stored for each vector address,
When an interrupt occurs, the CPU is sent to the address indicated by the table.
The process of (1) moves on.

As described above, the hardware configuration of the present invention is common, and when configuring two or more memory banks using the same ROM chip, the configuration disclosed in Japanese Patent Application No. 61-252195 is used. may also be used, and these configurations are not related to the gist of the present application.

FIG. 1 is an explanatory diagram for explaining an embodiment of the first method of the present invention, and shows program contents of memory banks (4) to (6).

Here, one specified interrupt among a plurality of interrupts will be explained, and it is assumed that at the time of this interrupt, address X is specified by the interrupt vector table on RAM (7>).

In this embodiment, as shown in FIG.
) (5) The same address area (11) of (6), i.e.
A bank switching control program (hereinafter referred to as bank switching manager) is stored at address 0-3-1, and different processing programs are stored in each processing program area (12) after this area (11). .

The bank switching manager is roughly divided into four programs, 1st to 4th, and each program has addresses O to P-1, P-
It is stored in Q-1, QR-1, and R-8-1. The second program is for execution to actually switch banks to the destination bank, and includes a combination of NOP commands and JMPQ commands, and two programs for switching from one's own 7-kun 7-i to any other bank. Each memory bank 1,
In 2.3, the NOP instruction is completely stored at the same address as the switching instruction to the own bank. Also, the fourth program is for returning to actually switch banks to the return bank, and has almost the same configuration as the second program.
A RET command is stored instead of an MPQ command.

The first program sets each bank to a predetermined register, for example AH, with its own bank number as the return bank number.
It consists of an instruction to save to a register, and an instruction to judge the destination bank number saved in a predetermined ALX register and jump to the corresponding address of the second program. Furthermore,
The fourth program is common to all banks, and includes an instruction to call a subroutine starting from the destination address saved in the BX register, and an instruction to judge the return bank number saved in the AH register and jump to the corresponding address in the fourth program. Consists of.

Hereinafter, the interrupt processing q-program (13) regarding the above-mentioned specific interrupt will be executed at address X~ of memory bank 3.
An example in which the interrupt processing program (13) is stored up to W and is used when an interrupt occurs during execution of the processing program in memory bank 1 or 2 will be described with reference to FIG. Specifically, an interrupt processing subroutine representing the actual interrupt processing contents is stored at addresses Y-W of the memory bank 3, and a CALL instruction and an IRET instruction for calling the subroutine are stored at addresses X and X+1.

In this case, addresses X to Z of memory banks 1 and 2 contain the MOV instruction, which saves the destination bank number BANK No. 3 in which the interrupt processing program has been stored, in the ALX register. An interrupt control program (14) is stored which includes a MOV instruction for saving the completed destination address Y in the BX register, a CALL instruction without calling the bank switching manager, and an IRET instruction.

Therefore, while executing the processing program for memory bank 1,
When the above-mentioned specific interrupt occurs, first, the interrupt control program starting from the atray X in the same bank is executed, and the ALX register and B

Each destination bank number B A N K No,
3 and the destination address Y are saved, and after saving, the process moves to the bank switching manager within the same bank. In the bank switching manager, after saving its own bank number 1 as the return bank number, for example, in the AH register, the destination bank number saved in the ALX register is determined and jumps to the corresponding address of the second program. do. Here, the destination bank is N.

Since BANK No. is 3, it jumps to bank 3 execution and bank switching to memory bank 3 can be executed. In memory bank 3, JMPQ is executed after the NOP instruction.
Since the instruction is stored, after switching to memory bank 3, the interrupt processing subroutine starting at address Y stored in the BX register will be called and executed. After execution, return bank N is saved in the AH register by the RET instruction.

In this case, the return bank number is BAN.
KNo. 1, so jump to bank 1 return,
Bank switching to memory bank 1 is executed. and,
After bank switching, the RET command of memory bank 1 returns to the interrupt control program of memory bank 1, and via this program, returns to the processing program before the interrupt.

Note that when the above-mentioned specific interrupt occurs during the execution of the processing program of memory bank 2, it is processed in exactly the same way. Also, when the above-mentioned specific interrupt occurs during the execution of the processing program of memory bank 3, the interrupt at address The interrupt processing subroutine is executed by the CALL instruction, and after execution the address
1 IRET command returns to the original processing program.

By the way, in the embodiment shown in FIG. 1, the bank switching manager ~- is configured to be able to switch from any bank to any bank, so the same applies to other types of interrupts and interrupt processing programs for other memory banks. , stores an interrupt control program that saves the destination bank number and/or destination address of the interrupt processing program to be executed in the ALX register and/or BX register, respectively, at a specific address specified by the interrupt. If you let it, the area (
Interrupt control can be realized by commonly using the bank switching manager 10).

Next, the second method of the present invention will be explained with reference to FIG. The major difference between this method and the first method is that the bank switching manager is provided exclusively for the specific interrupt mentioned above. Specifically, the bank switching destination bank No. 1 and destination address are BANKN in advance within the manager.

3 and Y. Therefore, although the same bank switching manager cannot be used in common for other interrupts, the number of steps is extremely reduced, and the time required for interrupt control can be shortened.

That is, in this method, if an interrupt occurs while the processing program in memory bank 1 is being executed, the JMPO at address
The command immediately moves to the bank switching manager, and after saving return bank No. 1, switching to bank 3 is performed uniquely. After switching, the CALLY instruction directly specifies address Y to call the interrupt processing subroutine, and after this routine is executed, switching to the return bank is performed. After switching to the return bank, the IRET command in the bank switching manager of memory bank 1 returns to the processing program.

In addition, in order to commonly use the bank switching manager for multiple interrupts within the same memory bank, use MOVB instead of JMPO in Figure 2.
X, Y, CALLO, IRET, before moving to the bank switching manager, store the interrupt control program that saves the address of the interrupt processing program in the BX register starting from address
Instead of the command and the CALLY command, the RET command and the CALLBX command may be stored, respectively.

(G) Effects of the Invention According to the present invention, in a system that is equipped with a plurality of memory banks and is restricted from taking a common memory area other than these memory banks, an interrupt occurs during the execution of a processing program in an arbitrary memory puncture. When an interrupt occurs, it becomes possible to process the interrupt using an interrupt processing program stored only in a predetermined memory bank.
The program area for storing the original processing program can be widened, and the desired processing program can be stored in the memory bank.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram for explaining the first embodiment of the present invention,
FIG. 2 is an explanatory diagram for explaining a second embodiment of the present invention,
FIG. 3 is a block diagram showing the hardware configuration for realizing the present invention. (1)...CPU, (2)...Address bus,
(3)...Data bus, (4>...Memory bank L
(5)...Memo IJ bank 2, (6)...Memory bank 3, (8)...Bank register, (10)
... Interrupt controller, (13) ... Interrupt processing program, (14) ... Interrupt control program.

Claims (2)

[Claims] (1) A plurality of memory banks for storing processing programs are provided, a bank switching control program is stored in the same specific address area of the plurality of memory banks, and an interrupt process is performed in a predetermined memory bank of the plurality of memory banks. storing an interrupt control program for storing a program in a memory bank other than the predetermined one, and storing destination bank information indicating the predetermined memory bank and/or the address of the interrupt processing program in a storage means; When an interrupt occurs while executing a processing program in a memory bank other than the predetermined one, the program moves to the bank switching control program after executing the interrupt control program, and in that program,
Saves information indicating its own memory bank as return bank information, switches to the predetermined memory bank, calls and executes the interrupt processing program based on the contents of the storage means, and returns after execution. An interrupt control method characterized by switching bank information to a memory bank and returning to the processing program after switching. (2) A plurality of memory banks for storing processing programs are provided, a bank switching control program is stored in the same specific address area of the plurality of memory banks, and an interrupt process is performed in a predetermined memory bank of the plurality of memory banks. When a program is stored and an interrupt occurs while executing a processing program in a memory bank other than the predetermined one, the program moves to the bank switching control program, and the program transfers information indicating its own memory bank to the return bank. Save the information as information, switch to the predetermined memory bank, call and execute the interrupt processing program after switching, and after execution switch the return bank information to the memory bank, and after switching, the processing program An interrupt control method characterized by a return to .