JPH01297734A - Instruction word fetch system - Google Patents

Abstract

PURPOSE:To improve the performance of the fetch of an instruction word from a local memory by holding the instruction word read out from a memory in a holding means sequentially, performing error correction when an error is found in the instruction word, and writing a corrected instruction word on the above memory. CONSTITUTION:The instruction word is stored directly in the word of an instruction word register 5 shown by a write address 111 from an instruction word write address register 9. When the one-bit error of a data part is detected in read out data 102 from the local memory 1, data error-corrected at an ECC circuit 3 is written on the instruction word register 5 being delayed by one machine cycle by the control of an ECC circuit output selector 4 by a switching control circuit 6, that of the write operation of the instruction word register 5 by a write timing control circuit 7, and a suppressing operation for a parity check circuit 10 by an error suppression circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an instruction word fetching method, and more particularly to an instruction word fetching method for an information processing apparatus having a local memory storing software that controls various processes in a computer main body system.

BACKGROUND TECHNOLOGY Conventionally, this type of information processing apparatus, as shown in FIG.
Local memory 1, local memory read/write data selector (hereinafter referred to as data selector) 2, and E C
C (Error Correcting Codes)
It is configured to include a circuit 3, an instruction word register 5, an instruction word write address register (WA) 9, and a parity check circuit 10, and the data stored in the local memory 1 is An ECC check pit generated in the above is added.

This write data 103 to the local memory 1 is selected by the data selector 2 and input to the ECC circuit 3, and the EC
The output data 105 that has been subjected to error correction processing in the C circuit 3 is written to the local memory 1.

When a command word fetch instruction is issued within the information processing device,
The address 101 of a desired instruction word is applied to the local memory 1, and the corresponding instruction word is read from the local memory 1 after a predetermined memory chip access time.

J sale data 10 from local memory 1
2 is selected by the data selector 2, and the output data 104 from the data selector 2 is E as the power bow sale data 102.
It is passed to the CC circuit 3. The ECC circuit 3 uses the EC added to the output data 104 from the data selector 2.
The normality of the data is checked by the CCC checker.

This ECC circuit 3 is capable of correcting 1-hit errors and detecting errors of 2 bits or more, and the check results are ``normal'', ``2 or more bit errors'', ``1-bit error in the data section'', and rECC check picks. 1
There are four types: 1 pix 1 to error. Among these, only when a "1-bit error in the data section" is detected, the EC
Error correction is performed in the C circuit 3. Since a 1-bit error in the rECC check pick has no effect on the data portion (instruction word), correction of this error is not executed.

Further, in the ECC circuit 3, a correctable error is reported when a 1-bit error is detected, and an uncorrectable error is reported when a 2-bit error or more is detected. When this uncorrectable error is reported, a transition is made to a failure handling operation, and otherwise normal operation is continued.

Output data 105 from ECC circuit 3 is written into the write word of instruction word register 5 indicated by write address 111 from instruction word write address register 9 in response to write instruction signal 120 from the information processing device.

The instruction word register 5 is composed of a register file consisting of four words (#0 to #3), and is capable of prefetching instruction words in the order of addresses in the local memory 1. ECC time rr43 to instruction word register 5
The writing of output data 105 from
0. This is done in 2-word units of #1 or words #2 and #3, and the ECC is applied to the 2 words that store the instruction that has already been executed or the 2 words that store the instruction that is currently being executed. Output data 105 from cycle l\83 is written.

Therefore, an instruction word that can be executed in the future is prefetched and stored in a word that stores an already executed instruction word or a word that stores an instruction word that is currently being executed. Data is updated. This newly fetched instruction word is buffered in the instruction word register 5 until the execution timing arrives. When the execution timing comes, the instruction word data 108 is output from the instruction word register 5.

Incidentally, when the output data 105 from the ECC circuit 3 is written into the instruction word register 5, the parity check time Fi!
In step 110, data parity checking and tucking are performed, and an error detection signal 114 is output.

In such a conventional information processing device, the local memory 1
Irrespective of whether the read data 102 read from the instruction register 5 is normal or not, the ECC circuit 3 always performs error detection and error correction as necessary and fetches it into the instruction register 5.
There is a problem in that the delay time caused by the ECC circuit 3, which has a large amount of hardware, cannot be ignored, and the performance of fetching instruction words from the local memory 1 deteriorates.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the problems of the conventional methods as described above, and an object of the present invention is to provide an instruction word fetching method that can improve the performance of instruction word fetching from local memory.

Structure of the Invention The instruction word fetch method according to the present invention includes a holding means for holding an instruction word read from a memory, and an error correction means for correcting an error in the instruction word using an error correction code added to the instruction word. An instruction word fetching method for an information processing apparatus having: a selection means for selecting one of an instruction word read from the memory and an instruction word error-corrected by the error correction means; The instruction words read from the memory are selected and sequentially written into the holding means, and when a correctable error is detected in the error correction means, the error-corrected instruction word is selected by the selection means, and the instruction word whose error has been corrected is selected. When the correctable error of the holding means is detected by a command word, the command word is rewritten.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, an information processing device according to an embodiment of the present invention includes a local memory 1, a local memory read/write data selector (hereinafter referred to as data cell lid) 2,
ECC circuit 3, ECC circuit output selector 4, instruction word register 5, switching control circuit 6, write timing control circuit 7, error suppression circuit 8, instruction word write address register (WA) 9, parity Eck circuit 10
and an AND gate 11.

In one embodiment of the present invention, basic operations such as read/write operations to the local memory 1, error correction processing operations by the ECC circuit 3, and write operations of prefetched instruction words to the instruction word register 5 are shown in FIG. This is the same as the conventional example, and the same parts are given the same reference numerals.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention. The operation of one embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

Address 101 input by issuing a command word fetch instruction within the information processing device (machine cycle T1 in FIG. 2)
(Fig. 2 machine cycle T1) local memory 1
Read data 102 (machine cycles T1 and T2 in FIG. 2) read from data selectors 2 and E,
The instruction selected by the CC circuit output selector 4 is directly stored in the word of the instruction register 5 indicated by the write address 111 from the instruction write address register 9 (machine cycle T3 in FIG. 2). (See word register fetch timing ■).

On the other hand, read data 1 read from local memory 1
02 is selected by data selector 2,
The output data 104 from the machine is input to the ECC circuit 3 and its normality is checked (Fig.
．． T3. ).

If the check result shows normality, the ECC circuit output selector 4 written in the instruction word register 5
The output data 107 is valid, and this output data 107 is buffer-linked in the instruction word register 5 until the timing of instruction execution arrives.

The check result in ECC circuit 3 is stored in local memory 1.
When the ECC circuit 3 detects an error in the data section itself of the read data 102, the ECC circuit 3 switches the detection signal 106 to the control circuit 6, the write timing control circuit 7, and the error suppression circuit 8. It is notified that a 1-bit error has been detected in the data portion of the read data 102 from the local memory 1.

The switching control circuit 6 receives the detection signal 106 from the ECC circuit 3.
When the detection of a 1-bit error in the data portion of the read data 102 is notified, the control signal 109 is sent to the ECC circuit so that the output data 105 error-corrected by the ECC circuit 3 is selected by the E C,C circuit output selector 4. Output to output selector 4.

When the write timing control circuit 7 is notified of the detection of a 1-bit error in the data portion of the read data 102 by the detection signal 106 from the ECC circuit 3, it outputs a control signal 110 to the instruction word write address register 9 and performs subsequent processing. A control statement is written to delay the generation of the write address 111 in the instruction word write address register 9 by one machine cycle, and the output of the write instruction signal 112 to the instruction word register 5 is delayed by one machine cycle.

The error suppression circuit 8 receives the detection signal 1 from the ECtC circuit 3.
When the detection of a 1-bit error in the data portion of the read data 102 is notified by 06, the inhibit signal 113 is output to the AND gate 11, and the output from the parity check circuit 10 is stopped for one machine cycle in which this notification is received. The output of the error detection signal 114 is suppressed by ANDK-10=-1 to 11. In other words, when the error detection is notified, the instruction word register is The report of the detection result of the parity check of the data stored in 5 is suppressed.

Therefore, reading disk 1 from local memory 1
When a 1-bit 1-error in the data section is detected at 02, the above-mentioned switching control circuit 6 controls the ECC circuit output selector 4, the write timing control circuit 7 controls the write operation of the command register 5, Due to the error suppression circuit 8's suppression operation on the parity check circuit 10, the instruction word register 5 receives the EC with a delay of one machine cycle.
In the C cycle r183, the error-corrected data is written (machine cycle T4 in FIG. 2) (see instruction word register fetch timing 2 shown in FIG. 2).

That is, the data that was written into the word of the instruction word register 5 one machine cycle ago and in which a 1-bit error was detected in the data section is replaced with normal data whose error has been corrected by the ECC circuit 3.

The data thus stored in the instruction register 5 is output from the instruction register 5 as prefetched instruction data 108.

Further, the detection result of the parity check performed by the parity check circuit 10 when normal data is written to the instruction word register 5 is outputted as an error detection signal 115 from the games 1 to 11.

At the timing when data in which a 1-pit error is detected in this data field is written to the instruction word register, the parity check report from the parity check circuit 10 is suppressed under the control of the error suppression circuit 8, and the parity check report from the parity check circuit 10 is suppressed under the control of the error suppression circuit 8. The two words of data that are not fetched into the word register 5 are buffered in the instruction word register 5 until the processing of the other two words of data is completed, so even if there is a one-machine-cycle delay in writing normal data, the operation will continue. has no effect.

Therefore, if a 1-bit error in the data section is not detected in the read data 102 from the local memory 1, this read data 102 is written directly to the instruction word register 5 in parallel with the check processing by the ECC circuit 3, so it is ignored. It is possible to avoid the delay time caused by the ECC circuit 3, which is too large to be possible. That is, when a 1-bit error in the data portion of the promotional data 102 is not detected, the ECC circuit 3 can be bypassed, thereby substantially improving the performance of instruction word fetching.

In this way, read data 10 from local memory 1
Only the data part 2 (instruction words other than those to ECC check pin 1) are stored directly in the instruction word register 5 without going through the ECC circuit 3, and when an error is detected in the read data 102, the ECC is sent to the data part 1. The circuit 3 performs error correction on the read data 102 and reads the subsequent data 102.
By making it possible to replace the data in which an error has been detected with the correct data, 'E'C'C' if the read data 102 is normal. Instruction word register 5 without going through circuit 3
Since the command word can be stored in the local memory 1, the performance of fetching the instruction word from the local memory 1 can be improved by -1.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the instruction words read from the memory are sequentially held in the holding means, and when a correctable error is detected in the instruction word, the error correction added to the instruction word is corrected. By rewriting the instruction word in which the correctable error has been detected in the holding means with the instruction word whose error has been corrected using the code, the performance of fetching the instruction word from the local memory can be improved. .

[Brief explanation of the drawing]

FIG. 1 is a program diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of an embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of a conventional example. . Explanation of symbols of main parts 1...Local memory 3...ECC@path 4...EC'C circuit output selector = 14-5...Instruction word register 6 ...Switching control circuit 7...Write timing control circuit 8...
・Error suppression circuit 9...Instruction word write address register 10...
... Parity check circuit 11 ... AND gate

Claims (1)

[Claims] (1) An instruction word fetching method for an information processing device having a holding means for holding an instruction word read from a memory, and an error correction means for correcting an error in the instruction word using an error correction code added to the instruction word. A selection means is provided for selecting one of the instruction word read from the memory and the instruction word error-corrected by the error correction means, and the selection means selects the instruction word read from the memory. Select and sequentially write into the holding means, and when a correctable error is detected in the error correction means, the selection means selects the error-corrected command word, and the command word causes the correction of the holding means to be corrected. An instruction word fetch method characterized in that an instruction word in which an error has been detected is rewritten.