JPH0130118B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to clock formation for stopwatches. The standard frequency of most oscillators used in recent electronic watches, especially small electronic watches, is 32768 (2 ¹⁵ ) hertz (hereinafter referred to as Hz), and this frequency value can be divided into any integer frequency. Therefore, it cannot be an accurate 100Hz divided signal. Therefore, in the present invention, the frequency divided signal closest to 100Hz is 128Hz (32768Hz÷2 ⁸ ).
The following describes approximately the formation of a 100 Hz stopwatch clock. Before entering into the description of the present invention, the basic blocks of an electronic timepiece will be explained. In Figure 1, 101 is an oscillator such as a crystal, and an oscillation circuit 1 that receives the signal and oscillates and shapes the waveform.
02, frequency divider circuit 103 that divides the source frequency from the oscillation circuit to the required frequency, 1 from the frequency divider circuit
A second counter 104 for a watch that counts up the second signal, a minute counter 105 for a watch that counts up the minutes using a carry signal from the second counter, and a minute counter 105 for a watch that counts up the hours using a carry signal from the minute counter. , a day counter 107 that counts up the day of the week with a carry signal from the hour counter, and a day counter 10 that counts up the day of the day with a carry signal from the hour counter.
8. A month counter 110 that counts up the month using a carry signal from the day counter; a month-end processing circuit 109 that performs month-end processing from the data of the day counter and the month counter; and a minute-end processing circuit 109 that stores minute data at the set time of alarm 1. Counter 111, time counter 1 that also stores time data at the set time of alarm 1
12. A minute counter 113 that stores minute data at the set time of alarm 2, an hour counter 114 that also stores hour data at the set time of alarm 2, and message data for alarm 1 (for what purpose the alarm time is set). , a counter 115 for storing picture code data to be displayed on a dot matrix liquid crystal display according to the purpose, and a counter 11 for storing message data for alarm 2.
6. 117 in this block diagram, which also includes a stopwatch function, is a stopwatch control circuit and frequency divider circuit 1 that controls the operation of the stopwatch.
A stopwatch clock forming circuit 118 generates a 100Hz signal from the 128Hz signal generated from the stopwatch, and a 1/100 that receives the stopwatch clock 100Hz and counts up a 1/100 second signal.
seconds and 1/10 second counter 119, second counter 120 that counts up with a carry signal from the 1/10 second counter, minute counter 121 that counts up with a carry signal from the second counter, carry signal from the minute counter Counter 1 when counting up with
22. A data selector that selects clock time data 150 and alarm time data 151 and detects coincidence of alarm times, and an alarm coincidence detection circuit 123, and a decoder that connects display data for displaying the seven-segment liquid crystal display. 124,
In response to an alarm coincidence signal, the alarm control circuit 125 that controls the operation of stopping the alarm, the electromagnetic or piezoelectric buzzer 126 that generates the alarm sound, the supply voltage to the circuit system during the operation period of the alarm, lamp, etc. Beta up control circuit 12 for preventing the oscillation system from stopping due to the drop
7. A power-on clear circuit 128 that generates a reset signal to reset the system required when the battery is inserted, and a segment driver 12 that drives each electrode of the liquid crystal seven segments.
9. Liquid crystal seven segment group 130, common waveform forming circuit 131 for driving the common display segment of the liquid crystal seven segments, display clock control circuit 132 for controlling the display digits of the liquid crystal seven segments, controlling the display digits of the dot matrix liquid crystal segment. a display scanning circuit 133 for controlling the dot matrix liquid crystal display, a display mode control circuit 134 for controlling the display contents of the dot matrix liquid crystal display section, a display data storage circuit A 135 in which various data for the dot matrix liquid crystal display are stored, and a display data storage circuit B 13.
6, a display data storage circuit C137, a fetch timing signal forming circuit 138 for extracting clock, alarm time data, stopwatch time data, etc. as main data as necessary, and a fetch timing signal forming circuit 138 for displaying dot matrix liquid crystal segments. A dot drive signal forming circuit 139, a dot common waveform forming circuit 140 for driving the common display segment of the dot matrix liquid crystal segment, a dot matrix liquid crystal segment driver 141 for driving each electrode of the dot matrix liquid crystal segment, and a dot matrix liquid crystal segment 142. , switch A for mode selection
143, Switch B144, which is mainly used when selecting various modes in this mode, Switch C145, which is mainly used when setting data in the correction state in this mode, Switch used when lighting the lamp D146, a test terminal 147 used when testing the function of the circuit system, a chattering prevention circuit 148 that prevents chattering from each switch, and a system control signal forming circuit 149 that determines various states from each switch signal. . The present invention relates to the stopwatch clock forming circuit 118 and the stopwatch 1/100 second and 1/10 second counter circuits 119 among the aforementioned blocks. Next, a conventional method of forming a 100Hz clock for a stopwatch will be explained with reference to FIGS. 2 and 3. From FIG. 2, in the initial state all flip-flops (hereinafter referred to as F/F) 201 to 203, 2
Reset signal 2 to 14-217, 227-230
50 is instantaneously given at logic level "0" and a 128 Hz signal 232 from a frequency divider is continuously applied to this circuit. First, F/F201-203, NR gate 20
7. AND gate 208 receives 128Hz divided signal 232
Control circuit, F/F to thin out 28 shots per second from
214 to 217 are 1/100 second digits and are decimal "0" ~
Decimal counter that counts "9", AND gate 21
8, 219, NR gate 220 is a group of gates that detect a certain state (described later) from 1/100 second digit gates, F/Fs 227 to 230 are 1/10 second digit and decimal numbers "0" to "9". The OR gate 231 counts "0" to "2", "4" to "6", and "8" in decimal from the 1/10 second digit count data.
This is a gate that detects "9". Next, the count data of F/Fs 227 to 230 in the 1/10 second digit and the output truth value of the R gate 231 are shown in Table 1 below.

[Table] 〓0〓, 〓1〓 are logic levels. Also, 1/100 second digit F/F, count data from 214 to 217, and decimal numbers from these data are "0", "4", and "7". AND gate 21 that detects
Table 2 shows the output truth values of 8, 219, and NR gate 220, and Table 3 shows the output truth values for detecting "0" and "4" in decimal notation. In other words, table-
The data in Table 2 is when the output 248 of the R gate 231 is at the logic level "1", and the data in Table 3 is at the logic level "0". In addition, data of 10 or more in decimal number is R gate 212, AND gate 211, in 1/100 second digit counter.
In the detection gate group of NR gates 209 and 210, in the 1/10 second digit counter, R gate 225,
It is detected by the detection gate group of AND gate 224, NR gate 222, and 223, respectively, and sent to F/F 214 via R gate 213 or 226.
~217, F/Fs 227~230 are reset and returned to their initial states.

【table】

[Table] Referring to the truth table of Table 2, it will be explained how the 128Hz signal 232 from the frequency divider is thinned out. To make the explanation easier to understand, the initial state of each F/F is to set the outputs 239 to 242 of F/Fs 214 to 217 to logic level "0" and F/F2 to
The outputs 234 and 236 of F/F 203 and 203 are set to logic level "0", and the output 235 of F/F 202 is set to logic level "1". In this state, the first 128Hz signal 232 (when the 232 signal in Figure 3A is 1)
When the signal enters, the output 235 of the F/F 202 changes from logic level "1" to "0" at the rising edge of the signal, and the output 235 of the F/F 202 changes from logic level "1" to "0" at the falling edge of the 128Hz signal 232.
The output 236 of changes from logic level "0" to "1". Output 2 of NR gate 207 at this time
The logic level of No. 37 is "1" because the outputs 234 and 236 of F/F 201 and 203 are both logic levels "0". Therefore, the output 23 of the AND gate
8, even if the 128 Hz signal 232 is inverted via the inverter 204 and input to the AND gate 208, it is forced to the logic level "0". This is the result
This means that one 128Hz signal 232 has been removed. Next, the second shot of 128Hz signal 232 (Fig. 3A)
When the 232 signal is 2) is input, the output 236 of the F/F 203 becomes logic "1" at the first shot, so the output 237 of the NR gate 207 becomes logic level "0" and the 128Hz inverted signal 233 becomes AND
Passing through gate 208, an output signal 238 (when signal 238 in FIG. 3A is 1) synchronized with 128 Hz signal 232 is generated. Sometimes this signal is F/F214
, and at the falling edge, the output 239 changes from logic level "0" to "1" and performs a normal count-up operation. At this time, the output 251 of the NR gate 220 becomes logic level "1", and the next 128
The output is held until the decimation timing of the Hz signal 232 is detected. The operation is clear from the data in Table 2, the outputs 239-2 of F/Fs 214-216.
When all 41 are at logic level "1", F/F21
4-215 outputs 239-240 and F/F2
When all the outputs 242 of 17 are at logic level "0", the output 251 of NR gate 220 becomes logic level "0", and this data is transmitted to F/Fs 201 to 20.
3, it is shifted by the 128Hz signal 232,
When the output 234 of the F/F 201 and the output 236 of the F/F 203 are at logic level "0", the 128 Hz signal 232 is thinned out by one shot. Therefore, from the data in Table 2, it can be seen that 3 out of 13 shots are thinned out in the 128 Hz signal 232, as shown in the timing diagram of FIG. 3A. This is when the output 248 of the R gate 231 is at logic level "1", and from the output data of the 1/10 second digit counter in Table 1 and the output 248 of the R gate 231, 8
Occurs twice. Therefore, in one second, 3 shots x 8 times = 24 shots are thinned out. Similarly, when we look at the method of thinning out the 128Hz signal 232 from the frequency divider with reference to the truth table in Table 3, we find that the 128Hz signal 232 from the frequency divider is 128Hz as shown in the timing diagram in Figure 3B.
It can be seen that 2 out of 12 shots in the 232 Hz signal are thinned out. This is when the output 248 of the R gate 231 is at logic level "0", and 1/
Output data of 10 second digit counter and R gate 2
It occurs twice per second from the output 248 of 31. Therefore, 2 shots x 2 = 4 shots are thinned out in one second.
Combining this with the 24 shot thinning number from earlier, 24 shots + 4
This means that the clock signal 238 for the stopwatch is thinned out by 28 shots in total from the 128 shots per second of the 128Hz signal 232, forming 100 shots per second, that is, a 100Hz signal. Also, 243 is a 10Hz clock signal for the stopwatch, and 249
is a 1Hz signal. From the above, in the circuit for forming a 100Hz stopwatch clock signal using the conventional method, 128Hz
The control circuit for thinning out the signal is complex;
As a result, the circuit configuration has the disadvantages that the operation timing is very difficult to understand, and as is clear from FIG. 3B, the 128 Hz signal is not thinned out at equal intervals. The present invention eliminates such drawbacks, and its purpose is to simplify the configuration of the control circuit for thinning out the 128Hz signal, thereby making the operation easier to understand than before, and thereby reducing the number of transistors used. The idea is to make the signal positions as evenly spaced as possible. The present invention will be described in detail below based on Examples. First, in Fig. 4, inverter 401, N
R gate 402, AND gate 403, and 40
4. Inverter 405 and F/F 406 are control circuits to thin out 28 shots per second from the 128Hz frequency divided signal 432, F/Fs 412 to 415 are 10 in 1/100 second digit
Count the base numbers "0" to "9". A decimal counter, an inverter 416, AND gates 417 and 418, and an NR gate 419 are a group of gates that detect a certain state (described later) from 1/100 second digit data;
F/F426 to 429 are decimal counters that count decimal numbers "0" to "9" in 1/10 second digits, and
The NAND gate 430 outputs "3" and "7" in decimal from the 1/10 second digit count data, and the inverter 431 outputs "0" to "2", "4" to "6", and "8" to This is a gate that detects "9". then 1/1
0 second digit F/F426-429 count data,
The output truth values of NAND gate 430 and inverter 431 are shown in Table 4 below.

[Table] Also, 1/100 second digit count data of F/Fs 412 to 415, and an AND gate 41 that detects "1", "5", and "9" in decimal from these data.
7, 418, and the output truth values of the NR gate 419 are shown in Table 5, and their output truth values for detecting "3" and "7" in decimal notation are shown in Table 6. In other words, table-
5 data is output 447 of NAND gate 430
is at the logic level "1", and the data in Table 6 is at the logic level "0".

【table】

[Table] Referring to the truth table shown in Table 5, it will be explained how the stopwatch 100 Hz signal 435 is generated from the 128 Hz signal 432 from the frequency divider. To make the explanation easier to understand, a logic level "0" potential is instantaneously applied to the counter reset signal 433, and the outputs 438 to 441, 4 of F/Fs 412 to 415 and F/Fs 426 to 429 are
43 to 446 are all at logic level "0". In this state, the first (fifth) 128Hz signal 432
When the 432 signal in Figure A is 1), the outputs 438 to 4 of F/Fs 412 to 415 are input in the initial state.
41 were all at logic level "0", so N
Since the output 451 of the OR gate 419 is at the logic level "1" and the F/F 406 is in the reset state, the output 437 of the inverter 405 is at the logic level "0". Therefore, the output of the AND gate 403 is at logic level "0", but the output of the AND gate 403 is
4 is formed, and an output signal 435 (when the 435 signal in FIG. 5A is 1) synchronized with the 128 Hz signal 432 is generated. Furthermore, this signal is input to F/F412,
At the falling edge, the output 438 changes from logic level "0" to "1" and performs normal count-up operation. Here, the counters of F/Fs 412 to 415 increase by one and reach the count value 1 in Table 5. Next, the second (fifth) 128Hz signal 432
When the 432 signal in Figure A is 2) is input, NR4
Since the output 451 of 19 is logic level "0", the F/F 406 is reset and the 128Hz signal 4
At the falling edge of the second signal of 32, the inverter 405
The output 437 of changes from logic level "0" to "1". (See 437 signal in Figure 5 A) For this reason
The output of AND gate 404 is logic level "0", but AND gate 403 is formed and the 128Hz signal 4
32 third shot (when 432 signal in Figure 5 A is 3)
When the output signal 435 (in Fig. 5A) is input,
435 signal is 2) occurs. Similarly, the counters of F/Fs 412 to 415 increase in count and sequentially move to the counts 2 to 9 in Table 5. As a result, when the output 438 of the F/F 412 is at the logic level "1" and the output 439 of the F/F 413 is at the logic level "0", that is, the output 451 of the NR 419 is at the logic level "0" and the AND gate 4
04 is not formed, one pulse is thinned out from the 128Hz signal 432. Therefore, the fifth
As is clear from the timing diagram in Figure A.
Out of 13 pulses of the 128Hz signal 432, 3 pulses are thinned out to 10 pulses. this is
When the output 447 of the NAND gate 430 is at the logic level "1", the outputs 443, 444 of the F/Fs 426, 427 of the 1/10 second digit counter in Table 4 and the output 447 of the NAND gate 430 generate 8 times per second. Occurs twice. Therefore, in 1 second, 3 shots x
8 times = 24 shots will be thinned out. Similarly, using the truth table in Table 6 as a reference,
A method for thinning out the 128Hz signal 432 will be explained. First, the outputs 438 and 43 of the F/Fs 412 and 413 constitute a 1/100 second digit counter due to the logic level "0" of the output 447 of the NAND gate 430.
AND gate 417 no matter what state 9 is in
is not formed and its output is at logic level 0. When the first 128Hz signal 432 (when the 432 signal in FIG. 5B is 1) is input in this state, F/ Output 438 of F412, 413,
439 are both at the logic level "0", the output 451 of the NR gate 419 becomes the logic level "1", the F/F 406 is reset, and the inverter 40
The output 437 of 5 will be at logic level "0". Therefore, AND gate 403 is not formed and the output becomes logic level "0", but AND gate 404 is formed and output signal 435 is synchronized with 128Hz signal 432.
occurs. (When the 435 signal in Figure 5B is 1) This signal is further input to the F/F 412, and at the falling edge, the output 438 changes from logic level "0" to "1" and performs normal count-up operation. . Here, the count up of the counters of F/Fs 412 to 415 advances by one and reaches the count value 1 in Table 6. This operation is performed by outputs 438 and 4 of F/Fs 412 and 413.
This continues until both 39 and 39 reach logic level "1".
(When the 435 signal in FIG. 5B is 1, 2, or 3) Next, when the outputs 438 and 439 of the F/Fs 412 and 413 become logic level "1", an AND gate 418 is formed, and its output becomes the logic level "1". 1", so the output 451 of the NR 419 becomes a logic level "0". As a result, the output of the AND gate 404 becomes a logic level "0", and one pulse of the 128 Hz signal 432 is thinned out. (For 432 signal 4 in Figure 5B). In other words, when the output 451 reaches the "0" level, subtraction is performed, so the output 451 becomes "0".
The level signal is essentially a subtraction signal. Output 4 of such operation F/F 412, 413
38,439 data, and as a result, 2 out of 12 shots of 128Hz signal 432 as shown in Figure 5B.
The emitted pulses are thinned out to a total of 10 pulses. This is when the output 447 of the NAND gate 430 is at logic level "0", and the outputs 443, 444 of the F/Fs 426, 427 of the 1/10 second digit counter in Table 4,
and from the output 447 of the NAND gate 430 twice per second. Therefore, in one second, 2 shots x 2 = 4 shots are thinned out. Adding this to the 24-shot thinning number from earlier, it becomes 28 shots, and 128 shots - 28 shots = 100 shots per second, forming a 100Hz clock signal for the stopwatch.
In addition, in this embodiment, gates 430, 430,
417, 418, 419, inverter 416, 4
31 is used, and a gate 40 is used as a selection circuit.
2,403,404 are used. In this way, in the present invention, from a 128Hz signal,
The configuration of the control circuit for thinning out 28 pulses has become simpler, the operation of the control circuit has become easier to understand, it has become possible to reduce the number of transistors used, and the position of the pulses to be thinned out from the 128Hz signal has been adjusted as much as possible. I am getting effects such as what I can do at intervals. Furthermore, the present invention is applicable not only to electronic watches but also to electronic game devices having a stopwatch function, electronic cameras, electronic desktop calculators, and the like.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram of an electronic timepiece, and FIG. 2 is a circuit diagram of a conventional stopwatch clock. FIG. 3: Operation timing diagram in a conventional stopwatch clock forming circuit. Fourth
Figure: Formation circuit diagram of a stopwatch clock according to the present invention. FIG. 5: An operation timing diagram in the stopwatch clock forming circuit of the present invention.

Claims (1)

[Claims] 1. Comprising a 1/100 second counter and a 1/10 second counter that counts an output signal of the 1/100 second counter, and having a frequency of 100 Hz based on a reference signal of (100+α) Hz.
In a clock forming circuit for a stopwatch of an electronic watch, which is equipped with a subtraction circuit for forming a signal, the subtraction circuit generates a signal output from a specific output terminal of a flip-flop that constitutes the 1/100 second counter and the 1/10 second counter. a gate circuit that generates a subtraction signal α times per second based on a flip-flop for subtraction which is reset when no subtraction signal is being output; the reference signal, the output of the gate circuit, and the output of the flip-flop for subtraction are input; and when no subtraction signal is output from the gate circuit, the reference signal is is passed through the 1/100 second counter,
When the subtraction signal is output from the gate circuit, the reset of the subtraction flip-flop is released, and the output of the subtraction flip-flop is inverted with the next reference signal, and the reference input to the subtraction flip-flop is changed based on the inverted output. A clock forming circuit for a stopwatch of an electronic timepiece, comprising selection circuits 402, 403, and 404 that pass a reference signal next to the signal to a 1/100 second counter.