JPH0130170B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of configuring a channel processing device that controls a plurality of channel devices.

(b) Background of the Technology Channel processing devices using a common control system have been available for some time, but there has been a problem with the division of work between the common control section and the individual sections corresponding to each channel device. That is, since high-speed processing is required for processing such as command chain processing, data chain processing, page boundary processing, etc. that should normally be handled by each channel device, it has been common for the common control unit to execute the processing. Therefore, when the above-mentioned processing requests are generated simultaneously from multiple channel devices, there are many cases where the above-mentioned processing cannot be done in time and overruns occur. A reconsideration was necessary.

With the recent trend toward higher integration of logic circuits, the increase in hardware due to improved functionality of the individual sections has become less of a problem, and improvements in the functionality of the individual sections have been desired.

(c) Prior art and problems In the common control unit of a conventional channel processing device, as a means to prevent overruns in input/output devices, the common control unit is pipelined so that processing for multiple channel devices can be performed simultaneously. There was a problem that required us to consider a complicated control method.

In addition, there is a recent trend toward diversification of transfer protocols and transfer speeds between channel devices and input/output devices.
Conventional methods, in which a common control unit handles these processes, have found it difficult to cope with this problem.

(d) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a system in which the execution of channel command words, including the aforementioned command chain processing, data chain processing, page boundary processing, etc., are all processed by separate channel devices. By allocating functions in a consistent manner, overruns of input/output devices are prevented, and differences in transfer protocols are absorbed by individual channel devices, and the interface between the common control unit and individual channel devices is made common. The purpose of this invention is to provide an extensible system in which there is no need to be particularly aware of the functions unique to the channel device from the common control unit.

(e) Structure of the Invention According to the present invention, a central control device, a channel processing device having a plurality of channel devices and controlling the channel devices, a memory device,
A data processing system comprising a memory control unit that performs access control of the memory device, the central control unit, and interface control between the memory device and the channel processing device, the channel processing device is controlled by input/output instructions and interrupts. The input/output processing unit consists of a channel path control unit that performs control related to the central control unit, and a block that performs memory access control, and each channel device individually processes all inputs related to the channel command string. A block configured with a channel unit that executes output operations and that controls memory access of the input/output processing device includes a buffer storage for transmitting control information that can be accessed from both the channel path control section and the channel unit. This is achieved by a channel processing device that is provided for each channel device and centralizes and controls the interface between the input/output processing device and the channel unit. This has the advantage of preventing overruns in the equipment.

(f) Examples of the invention Examples of the invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an example of the division of functions between an input/output processing unit (IOP) and a channel unit (CHU), which is the main focus of the present invention. FIG.

In the drawing, 1 is an input/output processing unit 4 (IOP),
2 is a channel unit (CHU), 3 is a main memory (MS), 4 is a memory control unit (MCU), and 5 is a central control unit (CPU).The main memory (MS) 3 includes input/output devices. A subchannel (SCHW) 31 is provided for correspondence.

The present invention is concerned with the division of functions between the input/output processing unit (IOP) 1 and the channel unit (CHU) 2.

In the input/output processing unit (IOP) 1, a channel path controller (CPC) 11 performs analysis of input/output instructions, interrupt processing, queuing of input/output operations, channel path selection, etc. 12
is a memory access control block (hereinafter referred to as bus handler) (BH), and a channel path control unit (hereinafter referred to as channel path controller)
(CPC) 11 or channel unit (CHU)
2 to the main storage device (MS) 3. Also, a channel path controller (CPC) 11 and a channel device (CHE) 23, which will be described later.
Buffer storage for transmitting control information between channels (hereinafter referred to as channel transaction buffer)
(CTB) corresponding to each channel device 23.

The function of the input/output processing device (IOP) 1 mentioned above is to manage the state of the channel device (CHE) 23 and subchannel (SCHW) 31. More specifically, the subchannel (SCHW)
31 is provided on the main memory (MS) 3, and the input/output processing unit (IOP) 1 is used when analyzing instructions received from the central control unit (CPU) 5 or when reading instructions from each channel device (CHE) 23. In accordance with the request, the subchannel (SCHW) is exchanged and analyzed in order to check the subchannel (SCHW) 31.

For example, for an input/output instruction, the channel path controller (CPC) 11 of this input/output processing unit (IOP) 1 reads and analyzes the subchannel (SCHW) 31, and if the input/output operation is involved, the channel path controller (CPC) 11 of the input/output processing unit (IOP) 1 Give execution instructions to (CHE)23.

In addition, the input/output processing unit (IOP) 1 receives the completion of the input/output processing in each channel device (CHE) 23 and the completion status report associated with the completion operation, analyzes the status, and sends the information to the central control unit ( CPU)
Performs interrupt processing for 5.

On the other hand, a channel unit (CHU) 2 is an input/output interface corresponding part in each channel device (CHE) 23, and a channel path adapter (CPA) 21 and a bus handler adapter (BHA) 22 are input/output processing units ( This is an interface adapter between the channel path controller (CPC) 11 and the bus handler (BH) 12 in the IOP) 1. The channel device (CHE) 23 constituting the channel unit (CHU) 2 individually performs the following input/output operations.

Reading of a command address word (CAW) from a channel transaction buffer (CTB) 121 provided in a bus handler (BH) 12 of an input/output processing unit (IOP) 1.

Read and analyze the channel command word (CCW) using the above command address word (CAW),
Execution behavior.

Data transfer via bus handler (BH) 12.

Input/output interface sequence control (initial selection).

Parsing input/output device status.

Executes all processing related to equal channel command strings.

In particular, in block multiplex channel mode (BMC) input/output operation, each channel device (CHE) 23 has one subchannel (SCHW).
It only performs input/output operations for the subchannels (SCHW) 31, and does not perform processing for multiple subchannels (SCHW) 31 at the same time. Therefore, each channel device (CHE) 23 is connected to the same channel device (CHE) 23. There is no need to be aware of subchannels (SCHW) corresponding to other input/output devices,
In each channel device (CHE) 23, only the subchannel information currently being processed exists.

Next, while referring to FIG. 1, the operation of the input/output processing unit (IOP) 1 and channel unit (CHU) 2 during input/output command processing will be outlined using FIG.
The explanation will focus on the division of each function.

First, the channel path controller (CPC) 11 in the input/output processing unit (IOP) 1 connects the main memory (MS) 3 to the memory control unit (MCU).
4, receives an input/output command (SIOF) from the central control unit (CPU) 5, and receives the channel device number,
The subchannel number (corresponding to the input/output device) is known, the subchannel (SCHW) 31 corresponding to the input/output device provided in the main storage device (MS) 3 is read out, and the status of the input/output device is checked.

In this way, the input/output processing device (IOP) 1 returns the condition code (CC) corresponding to the status of the input/output device to the central control unit (CPU) 5 and releases the central control unit (CPU) 5.

If the input/output processing unit (IOP) 1 executes an input/output operation (that is, CC = 0), it reads the command address word (CAW) from the main memory (MS) 3 and sends it to the central control unit (CPU). ) After opening 5,
A channel path controller (CPC) 11 queues input/output operation queues provided within itself. At this time, the command address word (CAW) is temporarily saved in the subchannel (SCHW) 31 in the main memory (MS) 3.

and Channel Path Controller (CPC)
11, when one input/output operation is dequeued from the input/output operation queue, the command address word ( CAW)
and the input/output device number, and gives an instruction to the channel device (CHE) 23 to execute the input/output operation.

In response to the above instruction, the channel device (CHE) 23 sends a command address word (CAW) from the corresponding channel transaction buffer (CTB) 121 of the bus handler (BH) 12 via the bus handler adapter (BHA) 22. ) and the input/output device number.

Subsequently, a channel command word (CCW) is read by the command address word (CAW),
Performs analysis and executes input/output interface control and data transfer control.

When the above input/output operation is completed, the channel device (CHE) 23 receives the channel end and device end from the input/output device, and inputs/outputs it to the channel path controller (CPC) 11 via the channel path adapter (CPA) 21. It sends out an operation completion signal (interrupt signal) and at the same time reports the completion status to the channel transaction buffer (CTB) 121 of the bus handler (BH) 12 via the bus handler adapter (BHA) 22.

and Channel Path Controller (CPC)
11 looks at the channel transaction buffer (CTB) 121 of the bus handler (BH) 12, analyzes the status of the input/output device, codes the interrupt type for the central control unit (CPU) 5, and sends it to the central control unit (CPU) 5. (CPU) Controlled to interrupt 5.

Above, we have explained an example of the division of functions between the input/output processing unit (IOP) 1 and the channel unit (CHU) 2 regarding the processing of the most common input/output commands. In execution, once a channel end is received from the input/output device in the seek execution stage, the channel device (CHE) 23 is released.
When the seek operation is completed in the input/output device, the channel device (CHE) 23 starts operation again when the device end is sent to the channel device (CHE) 23 to receive the next command.
Channel command word (CCW) reading and analysis,
execution, data transfer, input/output interface control,
All status reports etc. from the input/output device are performed by the channel device (CHE) 23, and the transmission and reception of the subchannel (SCHW) corresponding to the input/output device is controlled to be performed by the input/output processing device (IOP) 1. .

It goes without saying that when the channel device (CHE) 23 is released in response to the channel end, the channel device (CHE) 23 can perform input/output operations for another subchannel.

To summarize the above, input/output processing unit (IOP) 1
analyzes input/output commands from the central control unit (CPU) 5, handles interrupts to the central control unit (CPU) 5, accesses the subchannel (SCHW) provided in the main memory (MS) 3, and transfers data. The accompanying access to the main storage device 3, etc. is executed.

The channel unit (CHU) 2 executes command interpretation associated with the execution of channel command strings, input/output interface control, completion report processing from input/output devices, etc.

As described above, input/output processing unit (IOP) 1
The interface between the channel unit (CHU) 2 and the channel unit (CHU) 2 becomes clear, and the control of the interface becomes easy.

In addition, since the main purpose of this explanation is to explain the division of functions between the input/output processing unit (IOP) 1 and the channel unit (CHU) 2, the input/output processing unit (IOP)
1 and the central control unit (CPU) 5 is not mentioned much, but when the central control unit (CPU) 5 itself issues a command, it reads the subchannel (SCHW) 31 and checks the status of the input/output device. There is also a way to look at it.

(g) Effects of the Invention As explained in detail above, according to the present invention, among processes related to input/output operations, execution related to channel command strings is all controlled to be performed by the channel device. This simplifies control in the input/output processing device that performs common control of input/output operations, and allows the channel device to absorb transfer protocols, transfer rate control, etc. related to the type of input/output device, and This has the effect of unifying the interface between the output processing device and the channel device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram illustrating an example of the division of functions between an input/output processing device and a channel unit. In the drawing, 1 is an input/output processing unit (IOP),
2 is a channel unit (CHU), 3 is a main memory (MS), 4 is a memory control unit (MCU), 5 is a central control unit (CPU), 11 is a channel path controller (CPC), and 121 is a channel transaction button. 12 is a bus handler (BH), 23 is a channel device (CHE), 31 is a subchannel (SCHW), and queue is an input/output operation queue.

Claims (1)

[Scope of Claims] 1. A central control device, a channel processing device having a plurality of channel devices and controlling the channel devices,
In a data processing system comprising a memory device, a memory control unit that performs access control of the memory device, the central control unit, and interface control between the memory device and the channel processing device, the channel processing device is controlled by input/output commands. The input/output processing unit consists of a channel path control unit that performs control related to the central control unit, such as control of commands and interrupts, and a block that performs memory access control. A channel unit that executes all input/output operations, and a block that controls memory access of the input/output processing device includes a buffer storage for transmitting control information that can be accessed from both the channel path control unit and the channel unit. is provided for each channel device, and the interface between the input/output processing device and the channel unit is unified and controlled.