JPH0130238B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization signal extraction circuit for easily and reliably extracting a synchronization signal from a reproduced output signal of a digital audio disk.

A digital audio disk is a device in which audio signals, synchronization signals, etc. are digitized and optically recorded at high density on the surface of the disk at a constant linear velocity.The signal format recorded on the disk is, for example, as shown in Figure 1. It is determined as shown. That is, in this system, one frame is made up of a fixed number of bits (for example, 588 bits), and these frames are consecutively recorded on the same disk at a constant linear velocity. The signal format of each frame is divided into a synchronization section A and an information section B, and the synchronization section A is located at the beginning of each frame. As shown in Fig. 1, the synchronization section A consists of 22 bits, and when the first 11 bits are "0" consecutively, the following 11 bits become "1" consecutively, and the first 11 bits are "1" continuously. are consecutively “1”
When , the following 11 bits are set to be "0" continuously.

In this case, the first 11 bits are set to be the opposite of the last bit in the previous frame, and in this way, a predetermined unit bit (11 bits) is set to "0" or “1”
The format in which . . . , . . . That is,
The information section B is configured so that a format consisting of 11-bit units of "0" or "1" does not occur under any circumstances. Also, information department B
In order to prevent conversion to direct current when there is no signal, the signal is always a continuous "1" or "0" signal over 3 bits or more. Therefore, the information part B is 3<B<11 It will be represented as a continuous signal only over a range of bits.

The digital audio disk configured in this manner optically reproduces digital information on the disk at a predetermined linear velocity, and uses the synchronization signal included in this reproduced signal as a reference to reproduce the reproduced signal of the information section B. By extracting and demodulating the signal, a high-fidelity audio signal can be easily obtained.

In this case, the most important thing in demodulating a high-fidelity audio signal is to reliably extract the synchronization signal provided at the beginning of each frame from the disc playback signal, and if this synchronization signal is not extracted by mistake. In this case, it becomes impossible to classify and demodulate information signals.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a synchronization signal extraction circuit which has a simple configuration but can reliably extract a synchronization signal from a reproduced signal of a digital audio disk.

In order to achieve such an object, the present invention provides a first counter that is cleared by the rising edge of the reproduced signal and counts clock pulses, and a second counter that is cleared by the falling edge of the reproduced signal and counts the clock pulses. and the output of the first counter at the falling edge of the reproduced signal and the output of the second counter at the rising edge of the reproduced signal both match the set value corresponding to the unit bit defined in the synchronization section of the disk. Only when this is the case, it is determined that the signal is a synchronization signal and a synchronization detection signal is sent out.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A synchronizing signal extraction circuit for a digital audio disk according to the present invention will be explained in detail below using embodiments shown in the drawings.

FIG. 2 is a circuit diagram showing an embodiment of a synchronization signal extraction circuit for a digital audio disk according to the present invention. In the figure, 1 is the clock pulse CP of, for example, 43218MHz, which corresponds to the bit rate at the time of recording on the digital audio disk.
A clock oscillator that sends out clock pulses that are highly precisely stabilized using a crystal oscillator.
Configured to send out CP. Reference numeral 2 denotes a first differentiating circuit which inputs the reproduced signal A obtained by optically reading the disk and which is supplied to the input terminal 3, and differentiates the rising part of the signal to generate a differentiated pulse _P1 . and resistance 6
This is a generally well-known circuit constructed by the following. 7 is an inverter that inverts the reproduced signal A; 8 is a rising portion of the output sent from the inverter 7;
In other words, it is a second differentiating circuit that differentiates the falling part of the reproduced signal A and generates a differentiated pulse _P2 .
Capacitor 9, diode 10 like the differential circuit
and a resistor 11. 12
is a first counter which sequentially counts and outputs clock pulses CP while being cleared by the differential pulse _P1 outputted from the first differentiating circuit 2.
A second counter 13 sequentially counts and outputs the clock pulses CP while being cleared by the differential pulse _P2 outputted from the second differentiating circuit 8. 14 and 15 are first parts constituting a holding circuit;
The first shift register 14, which is a second shift register, captures and shifts the count output of the first counter ₁₂ when the differential pulse P2 is generated, and outputs it by shifting _it . The count output of the second counter 13 at the current time is taken in, shifted, and outputted. 16 and 17 are first and second decoders, and the first decoder 16 is connected to the first shift register 14.
The second decoder 17 converts the output of the second shift lens star 15 into a decimal number and outputs it. 18 is the first and second decoder 16, 17
This is an AND gate that detects coincidence of signals output from output terminals 0 _{and 11} of and sends out a synchronization detection signal SD.

In the synchronizing signal extraction circuit for a digital audio disk configured as described above, when the reproduced signal A shown in FIG. The portion is differentiated and a differential pulse P ₁ shown in FIG. 3b is outputted at times t ₁ , t ₃ , t ₅ , and t ₇ . On the other hand, since the second differentiating circuit 8 differentiates the rising edge of _the reproduced signal A supplied via the inverter ₇ ,
At t ₆ and t ₈ , a differential pulse P ₂ shown in FIG. 3c is output.

On the other hand, the clock oscillator 1 generates a clock pulse CP that matches the bit rate at the time of writing to the disk, and the first and second counters 1
2 and 13 sequentially count clock pulses CP while being cleared by differential pulses _P1 and _P2 , respectively. Therefore, if the reproduced signal A is read while meeting the predetermined constant linear velocity condition, the first and second counters 12,
The value of 13 is as shown in Figure 3 d and e,
The number of bits between the rising edge and the falling edge of the reproduced signal A shown in FIG. 1 should be accurately counted.

Next, since the first shift register 14 inputs the differential pulse P ₂ generated at the falling edge of the reproduction signal A to the shift input terminal S, the first counter 1
The count value of 2 is fetched and shifted in parallel at the falling edge of the reproduction signal A during the counting operation. Therefore, this first shift register 14
From then, the time t ₂ , which is the falling edge of the reproduced signal A,
At _t6 and _t8 , the output value changes as shown in FIG. 3f, and this first shift register 14
The output value represents the number of clock pulses CP in each "1" period of the reproduced signal A, that is, the number of bits. Also, the second shift register 1
5, the count value of the second counter 13, which starts counting at the falling edge of the reproduced signal A, is taken in by the differential pulse _P2 generated at the rising edge of the reproduced signal A, as shown in FIG. 3g. Because of this shift, the second shift register 15 outputs the clock pulse during the "0" period of the reproduced signal A.
The number of CPs, that is, the number of bits, will be output. In this way, signals representing the number of bits in the "1" and "0" periods of the reproduced signal A output from the first and second shift registers 14 and 15 are sent to the first and second decoders 16 and 17, respectively. It is converted to a decimal number and output. In this case, the above first
In the signal format explained in the figure, special conditions are given only to the synchronization section A. In other words, the synchronization signal part consists of 22 bits, and the first and second 11 bits are consecutively different signals (“0” and “1”), and these 11 bits are continuous. The part where signals of the same type are continuous is specified only in this part. Therefore, synchronization can be detected by extracting a portion where 11 bits of "0" and 11 bits of "1" are consecutive. Here, the first and second
The third block shows the output contents of the shift registers 14 and 15.
Looking at figures f and g, the “1” period t ₃ of the reproduced signal A ~
At t ₄ , t ₅ to _{t 6} , and t ₇ to _{t 8} , a signal representing the count number (bit number) of the “1” period of the reproduced signal A and a count number (bit number) of the “0” period following the “1” period are detected. The signals representing the numbers) are outputted temporally overlapping each other. Therefore, both signals representing the decimal number "11" outputted from the output terminals 0 _{to 11} of the first and second decoders 16 and 17 that decode the outputs of the first and second shift registers 14 and 15 into decimal numbers. By finding the match in AND gate 18, 11
At the part where bit "0" and 11 bit "1" are consecutive, that is, the synchronization signal is detected and the count value "11" shown in Fig. 3 f and g overlaps (t ₃ - _{t 4} ). The synchronization detection signal SD is then output.
Therefore, the first and second shift registers 16, 17 and the AND gate 18 constitute a synchronization signal discrimination circuit.

In the above embodiment, the synchronization signal discrimination circuit is configured by a combination of the first and second decoders 16, 17 and the AND gate 18.
The decoders 16 and 17 may be constructed from magnitude comparators, and may be constructed so that outputs matching the reference value (11) are supplied to the AND gate 18, respectively. Further, the clock pulse CP does not need to match the bit rate at the time of recording on the disc, but only needs to have a correspondence relationship such as an integer multiple, and in this case, the first and second decoders 16, 16, Needless to say, it is necessary to change the output extraction position of No. 17 and the reference value of the magnitude comparator.

As explained above, the digital audio disk synchronization signal extraction circuit according to the present invention includes a first counter that is cleared by the rising edge of the reproduced signal and counts clock pulses, and a first counter that is cleared by the falling edge of the reproduced signal. A second counter for counting clock pulses is provided, and the output of the first counter at the falling edge of the reproduced signal and the output of the second counter at the rising edge of the reproduced signal are both unit bits determined in the synchronization section of the disk. Since the synchronization detection signal is determined to be a synchronization signal only when the synchronization signal matches a set value corresponding to the number, a synchronization detection signal is sent out even though it has a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a signal format in a digital audio disk, FIG. 2 is a circuit diagram showing an embodiment of a synchronization signal extraction circuit for a digital audio disk according to the present invention, and FIGS. 3 a to g 2 is an operational waveform diagram of each part of the circuit shown in FIG. 2. FIG. 1... Clock oscillator, 2, 3... First and second differentiating circuits, 12, 13... First and second counters, 14,
15...first and second shift registers, 16, 17...
First and second decoders, 18...AND gate.

Claims (1)

[Claims] 1. A first differentiating circuit that sends out a differentiated output of the rising portion of the reproduced signal of the digital audio disk, a second differentiating circuit that sends out the differential output of the falling portion of the reproduced signal, and the first differentiating circuit. a first counter that is cleared by the differential output to count clock pulses; a second counter that is cleared by the differential output of the second differential circuit to count clock pulses; and when the differential output of the second differential circuit is generated; a first holding circuit that holds the counted value of the first counter; a second holding circuit that holds the counted value of the second counter when the differential output of the first differentiating circuit is generated; The present invention includes a synchronization signal discriminating circuit that determines the signal as a synchronization signal and sends out a synchronization detection signal only when the output values of the holding circuit both match set values corresponding to unit bits defined in the synchronization section of the disk. Features a synchronization signal extraction circuit for digital audio disks.