JPH01303695A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten time for the initializing of memory cell data by making plural column decoder outputs on and writing the memory cell data at once. CONSTITUTION:Many OR circuits 30 are provided at a column decoder 31 and the respective outputs are made digital selecting lines. Then, the respective OR circuits 30 are added to the output of the normal column decoder, and when a cycle signal 21 selects (that is, a flash light), all outputs become a selecting condition. Consequently, by inputting the input of a flash light selecting signal phi at a high level and making all the output of the column decoder 31 high, the column decoder outputs (YSW) are made on at once and to one word, data can be written to a memory cell at one cycle. Thus, time for initializing memory data can be shortened.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and in particular a function that allows writing in word units (flash write) b.
This invention relates to a semiconductor memory circuit with four functions.

[Conventional technology]

In the conventional technique, writing is performed in individual memory cells selected by a row decoder and a column decoder.

[Problem to be solved by the invention]

In the conventional circuit configuration, writing is performed in units of bits, so a time of (memory cycle time x number of bits) is required to initialize memory data of all pitches. For example, it takes 20 hours to store memory cells at one time.
If it is 0ns to 300ns (1 billionth of a second), it takes 0 to fill all the data into a 1M bit memory cell.
．． It has the disadvantage that it requires a time of 2 to 3 seconds. That is,
In conventional semiconductor memory circuits, one word (WORD
) is selected, column decoder output (YSW)'
Data was written into all cells by turning on t one by one.

The object of the present invention is to solve the above-mentioned drawbacks and to
Turn it ON, write 4F into memory cell data' to -i,
An object of the present invention is to provide a 1-bit semiconductor memory device so as to shorten the time required to initialize memory cell data.

[Means for solving problems]

The structure of the semiconductor memory device of the present invention includes means for selecting a plurality of column decoders all at once, and means for activating a sense amplifier provided in each digit line after the plurality of column decoders are selected. It is characterized by:

〔Example〕

Next, the present invention f will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention. In the figure, the semiconductor memory device of this embodiment includes a word line l forming a large number of columns, a dummy word line i1 provided corresponding to the word line 1, and a first word line forming a large number of rows. Digit line 4 and this digit R4
a second digit line 4' having a logic level opposite to that of;
The first data bus line (Ilo) 7, the second data bus line 7' of the opposite logic level, the digit selection l@2 connected to the output of the column decoder, the word line l and the first data bus line 7'. MOS installed at each intersection with digit line 4
A memory cell 5 consisting of a transistor and a capacitor,
The memory cells 5 provided at the intersections of the dummy word line l' and the second digit 54', the digit selection line 2 and the first . the second digit lines 4, 4' and the first digit line 4,4'; MO8+ interposed between the second data bus line 7 and the second data bus line 71, respectively.
- a transistor; It is configured to include a sense amplifier 3 whose inputs are digit lines 4 and 4' of X2, and a sense amplifier activation signal (SE) line 6.

In the conventional circuit, as shown in FIG. 2, the word line selection signal 10→sense amplifier activation signal 11→digit selection signal 12 is output with a further delay.

On the other hand, in the flash write function of this embodiment, as shown in FIG. n) 12), data bus line 7.7
+ information is transferred to all digit lines 4.4+, and then the signal (SE) 1 of the sense amplifier activation signal line 6 is transferred.
1, the sense amplifiers 3 are all activated and data is written into the memory cells 5 on the selected word.

4 shows an example of a circuit for realizing the flashlight of this embodiment. In the figure, signal 20 is a word line decoder activation signal, signal 21 is a signal indicating that the actual row cycle is a flash write cycle, and is also used to select all column decoders. A delay circuit 23 inputting the activation signal 20 and a cycle signal 2
1 as input, a delay (b) path 24, and an AND circuit 2
5, three NAND circuits 26, and an inverter 27, and a word line decoder 28 is also input.

In the configuration shown in FIG. 4, at the time of flash writing, the signal 21 indicating a flash cycle becomes 'High' level, and all column decoders will be selected.The output signal 22 takes the logic of signals 20 and 21, and further Since the output can be completed after a certain time delay, the column lever -
The sequence of activating the sense amplifier by SE after selecting the data is guaranteed.

FIG. 5 shows that the column decoder is activated by the cycle signal 21.
A circuit example of this embodiment in which all are selected is shown. In the figure, a column decoder 31 is provided with a large number of OR circuits 30, each having an output connected to a digital selection line 2. In the figure, an OR circuit 30 is attached to each output of a normal column decoder, and when the cycle signal 21 is selected (j, ie, flashlight), all outputs are in the selected state.

FIG. 6 is a circuit diagram showing a column decoder circuit of a semiconductor memory device according to another embodiment of the present invention. In the figure, an example of all column decoder selection is shown. The two-person column decoder circuit diagram consists of P-channel MOS transistors 40, 41, 42, 43, and N-channel MOS transistors.
The transistors 44, 45, 45, 47 are included. Here, the circuit from which the MOS transistors 43 and 47 are removed is a NAND circuit that uses φ2 as an input.

When the lock 50 shown in FIG. 7 is input to the third input φ (flash light x selection signal) shown in FIG. Second
Regardless of the state of the input φl, the right input signal, the output (
OUT) becomes a high level (9), all column decoders become selected. Also, the third input (7
By decoding 1 with the address signal, it is also possible to flash write to partial cells on the word line.

As described above, this embodiment has a circuit that allows writing to a plurality of memory cells connected to one word. With this configuration, for example, when all column decoders are selected simultaneously, the time required to write all data into memory cells can be shortened to 1/the number of column decoders compared to the conventional time. In order to realize this function, means for selecting all column decoders at the same time, and further means for transferring write data to the digit line after selecting the column decoders and then activating all sense amplifiers are required.

〔Effect of the invention〕

As explained above, in the present invention, in particular, by inputting the flash light selection signal φ at a high level and setting the outputs of the color and mu decoders to high level, the YSW
t-ON at once, data can be written to the memory cell for one WORDK in one cycle. This allows for high-speed writing on a display or computer graphics, and without having to make any changes to the array section. The effect is that there is no need for it.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention;
Fig. 2 is a waveform diagram showing the operation of a conventional storage device, Fig. 3 is a waveform diagram showing one operation of Fig. 1, Fig. 4 is a circuit diagram realizing the flash light state of Fig. 1, and Fig. 5 is a waveform diagram showing the operation of a conventional storage device. is a circuit diagram for selecting the column decoder of the embodiment of FIG. 1, FIG. 6 is a column decoder circuit of another embodiment of the present invention, and FIG. 7 is a waveform diagram of the signal input to the circuit of FIG. 6. be. l...word line, lI...dummy word line, 2...°digit selection line, 3...-
・Sense amplifier, 4.4+...I/IT line, 5...Memory cell, 6...Sense amplifier activation signal line, 10.11.12.50 .51゜52
--- Signal, 20 --- Sense amplifier activation signal, 21 --- Flash write cycle signal, 22 --- Output signal, 23.24 ---・
・Delay circuit, 25...--AND circuit, 26・
-... NAND circuit, 27... Inverter,
28...Word line decoder, 30...-
OR circuit, 31... Column decoder, 40.4
1゜42.43...P channel MO3) transistor, 44,45.46.47...N channel MO3) transistor. ￥ 2 times Tazuzu ni ρ Mine 71 yen]

Claims (1)

[Claims] 1. A semiconductor memory device comprising: means for selecting a plurality of column decoders all at once; and means for activating a sense amplifier provided in each digit line after the plurality of column decoders are selected.