JPH0130390B2 - - Google Patents

Info

Publication number
JPH0130390B2
JPH0130390B2 JP14619682A JP14619682A JPH0130390B2 JP H0130390 B2 JPH0130390 B2 JP H0130390B2 JP 14619682 A JP14619682 A JP 14619682A JP 14619682 A JP14619682 A JP 14619682A JP H0130390 B2 JPH0130390 B2 JP H0130390B2
Authority
JP
Japan
Prior art keywords
circuit
current
thyristor
pulse
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14619682A
Other languages
Japanese (ja)
Other versions
JPS5937885A (en
Inventor
Teruyoshi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP14619682A priority Critical patent/JPS5937885A/en
Publication of JPS5937885A publication Critical patent/JPS5937885A/en
Publication of JPH0130390B2 publication Critical patent/JPH0130390B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/145Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/155Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)
  • Power Conversion In General (AREA)

Description

【発明の詳細な説明】 a 技術分野 本発明は、誘導性負荷を励磁する電流制御装置
に関する。
Detailed Description of the Invention a. Technical Field The present invention relates to a current control device for exciting an inductive load.

b 技術的背景とその問題点 誘導性負荷を励磁する従来の電流制御装置を第
1図の制御ブロツク図に示す。
b. Technical Background and Problems The conventional current control device for exciting an inductive load is shown in the control block diagram of FIG.

1は交流電源、2は交流電圧を直流電圧に変換
するサイリスタ2Aにて構成された制御整流回
路、3は制御整流回路2にて励磁される誘導性負
荷、4は誘導性負荷3に流す電流の目標を設定す
る電流基準回路、5は誘導性負荷3に流れる電流
を検出する電流検出回路、6は電流基準回路4の
出力信号と、電流検出回路5の出力信号とを差動
的に入力し、偏差信号を比例績分演算する電流制
御演算回路、7は電流制御演算回路6の出力信号
により、制御整流回路2のサイリスタの点弧タイ
ミングを決める位相制御回路、8は位相制御回路
7の出力により、制御整流回路2のサイリスタの
ゲートに連続ゲートパルスを与える連続ゲートパ
ルス発生回路、9は位相制御回路7が連続ゲート
パルスをβリミツトへ位相シフトする為に、位相
制御回路7にシフト指令を与える位相しぼり回
路、10,11,12,13はサイリスタの両端
に発生するサージ電圧を吸収する為にサイリスタ
の両端に接続された、抵抗とコンデンサにより構
成されるスナバ回路、14はサイリスタがゲート
に連続ゲートパルスを与えられた時ラツチしやす
くする為に制御整流回路2の出力側に接続された
ダミー抵抗である。
1 is an AC power supply, 2 is a controlled rectifier circuit composed of a thyristor 2A that converts AC voltage to DC voltage, 3 is an inductive load excited by the controlled rectifier circuit 2, and 4 is a current flowing through the inductive load 3. 5 is a current detection circuit that detects the current flowing through the inductive load 3; 6 is a current reference circuit that differentially inputs the output signal of the current reference circuit 4 and the output signal of the current detection circuit 5; 7 is a phase control circuit that determines the firing timing of the thyristor of the control rectifier circuit 2 based on the output signal of the current control calculation circuit 6; 8 is a phase control circuit of the phase control circuit 7; A continuous gate pulse generation circuit provides a continuous gate pulse to the gate of the thyristor of the control rectifier circuit 2 by output, and 9 provides a shift command to the phase control circuit 7 in order for the phase control circuit 7 to phase shift the continuous gate pulse to the β limit. 10, 11, 12, 13 are snubber circuits that are connected to both ends of the thyristor and are made up of a resistor and a capacitor to absorb the surge voltage generated across the thyristor. This is a dummy resistor connected to the output side of the control rectifier circuit 2 to facilitate latching when continuous gate pulses are applied to the circuit.

以上により構成される従来の電流制御装置は、
位相しぼり回路9がシフト指令を解除すると位相
制御回路7は電流制御演算回路6の出力信号に従
がつた位相よりトリガパルスを発生し、連続ゲー
トパルス発生回路8を介して第2図b,cに示す
様な連続ゲートパルスを出力し、制御整流回路2
のサイリスタ2Aのゲートに印加して誘導性負荷
3に流れる電流が、電流基準回路4の設定信号に
従がうように電流制御を行なう。
The conventional current control device configured as above is
When the phase throttling circuit 9 cancels the shift command, the phase control circuit 7 generates a trigger pulse from the phase that follows the output signal of the current control calculation circuit 6, and generates a trigger pulse via the continuous gate pulse generation circuit 8 as shown in FIGS. 2b and 2c. The control rectifier circuit 2 outputs continuous gate pulses as shown in
Current control is performed so that the current applied to the gate of the thyristor 2A and flowing to the inductive load 3 follows the setting signal of the current reference circuit 4.

この場合、負荷電流が零の状態から起動すると
き、場合によつては起動できないと云う問題が発
生するが、第2図を用いて以下に説明する。
In this case, when starting from a state where the load current is zero, a problem arises in that starting may not be possible in some cases, but this will be explained below with reference to FIG.

第2図aは、交流電源の電圧波形、第2図b,
cはサイリスタ2Aのゲートに印加される連続ゲ
ートパルス、PAで示す一発目の立ち上がりは、
位相制御回路7で演算されたサイリスタ点弧タイ
ミングである。PA以後のパルスPBは、PAのパル
ス発生後第2図aのb点に示すβリミツト以後数
パルス迄連続ゲートパルス発生回路8により連続
的に発生される。
Figure 2a shows the voltage waveform of the AC power supply, Figure 2b,
c is a continuous gate pulse applied to the gate of thyristor 2A, and the first rise indicated by P A is:
This is the thyristor firing timing calculated by the phase control circuit 7. The pulses P B after P A are continuously generated by the continuous gate pulse generating circuit 8 until several pulses after the β limit shown at point b in FIG. 2 a after the pulse P A is generated.

従来狭幅のゲートパルスを用いて誘導性負荷3
に電流を流がすとき、ダミー抵抗14の抵抗値は
サイリスタのラツチ電流を充分に流す値に選定さ
れていたが運転中の電力損失が大きくなる欠点が
ある。そこで第2図b,cに示す様に連続した狭
幅のゲートパルスとしダミー抵抗14の抵抗値を
大きく選定して電力損失が少くなる様に考慮して
いる。
Inductive load 3 using conventional narrow gate pulse
The resistance value of the dummy resistor 14 is selected to be a value that allows a sufficient latch current to flow through the thyristor when a current is caused to flow through the thyristor, but this has the drawback of increasing power loss during operation. Therefore, as shown in FIGS. 2b and 2c, continuous narrow gate pulses are used, and the resistance value of the dummy resistor 14 is selected to be large in order to reduce power loss.

第2図dは負荷電流が零の状態からゲートパル
スが与えられたときの負荷電流の通電初期の状態
を示した電流波形である。
FIG. 2d is a current waveform showing the initial state of the load current when a gate pulse is applied from a state where the load current is zero.

時刻t1に於てゲートパルス第2図bが与えられ
ると、最初のパルスPAによりサイリスタ2Aが
ターンオンして負荷電流が流れ始める。このとき
の負荷電流の立上りは電源と負荷を含む主回路イ
ンピーダンスの時定数に対応して増加し、パルス
PAの期間中には僅かの電流しか増加せずサイリ
スタ2Aに流れる電流がラツチ電流まで達しな
い。このため、ゲートパルスPAが消滅するとサ
イリスタ2Aが半導通状態となつて誘導性負荷の
放電回路を形成し増加した負荷電流を一担保持す
る様に動作する。その後、パルスPBが与えられ
ると半導通状態のサイリスタ2Aは完全導通状態
となり再び負荷電流は増加し始め、パルスPB
期間中にラツチ電流に達しなければパルスPB
消滅したとき再びサイリスタ2Aは半導通状態と
なる。以後、パルスPBが与えられる度に同様の
動作を繰り返しながら少しずつ負荷電流が増加す
る。
When the gate pulse (FIG. 2b) is applied at time t1 , the first pulse P A turns on the thyristor 2A and the load current begins to flow. At this time, the rise of the load current increases in accordance with the time constant of the main circuit impedance including the power supply and load, and the pulse
During the P A period, the current increases only slightly and the current flowing through the thyristor 2A does not reach the latch current. Therefore, when the gate pulse P A disappears, the thyristor 2A becomes semi-conductive, forms an inductive load discharge circuit, and operates to hold the increased load current. After that, when the pulse P B is applied, the thyristor 2A, which is in a semi-conducting state, becomes fully conductive and the load current starts to increase again.If the latch current is not reached during the period of the pulse P B , the thyristor 2A is turned off again when the pulse P B disappears. 2A becomes semi-conductive. Thereafter, the load current increases little by little while repeating the same operation every time the pulse P B is applied.

その後、時刻t2に於て負荷電流I0の値まで増加
したとき、サイリスタ2Aの電流がラツチ電流に
到達し以後はパルスが消滅しても負荷電流は増加
して流れ続け連続電流に於る通常の転流動作に入
る。
After that, when the load current increases to the value of I0 at time t2 , the current of thyristor 2A reaches the latch current, and from then on, even if the pulse disappears, the load current increases and continues to flow as a continuous current. Enters normal commutation operation.

以上は正常に起動できた場合について説明した
が、ゲートパルスのパルス幅の異常、ダミー抵抗
14の断線、その他の原因によりサイリスタ2A
の電流がラツチ電流まで到達しない場合がある。
この場合サイリスタ2Aには連続してゲートパル
スが与えられているにもかゝわらず目標の負荷電
流を流すことができず起動できない状態となる。
更に、この状態のまヽ放置しておくとスナバー回
路10〜13のコンデンサの充放電により同回路
の抵抗を焼損する危険、欠点がある。
The above explanation is based on the case where the thyristor 2A can be started normally, but due to an abnormality in the pulse width of the gate pulse, disconnection of the dummy resistor 14, or other causes, the thyristor 2A
The current may not reach the latch current.
In this case, even though gate pulses are continuously applied to the thyristor 2A, the target load current cannot flow, and the thyristor 2A cannot be started.
Furthermore, if this state is left as it is, there is a risk and disadvantage that the resistors of the snubber circuits 10 to 13 will be burned out due to charging and discharging of the capacitors.

c 発明の目的 本発明の目的は、前述従来の欠点を除去する為
に、サイリスタがラツチできないのを検出するラ
ツチ不能検出回路を設けることによりスナバ回路
の抵抗の焼損を防止できる保護機能を備えた高信
頼性の電流制御装置を提供することにある。
c. Object of the Invention In order to eliminate the above-mentioned drawbacks of the conventional art, the object of the present invention is to provide a protection function that can prevent burnout of the resistor of the snubber circuit by providing an unlatching detection circuit that detects the failure of the thyristor to latch. The object of the present invention is to provide a highly reliable current control device.

d 発明の概要 本発明は、誘導性負荷に電力を供給するサイリ
スタを用いた電力変換回路と、前記サイリスタの
点弧パルスを連続した複数のパルスで与えるゲー
トパルス発生回路を具備した電流制御装置に於
て、負荷電流が所定の値以上になると第1の論理
信号を出力する電流レベル検出回路と、前記電流
制御装置の制御開始のタイミングから所定の時間
後に第2の論理信号を出力するタイマー回路と、
前記第1の論理信号と前記第2の論理信号から前
記点弧パルスの点弧位相を遅れ側に制御するシフ
ト信号を出力する論理回路を設けスナバー回路の
焼損を防止できる様にしたことを特徴とする電流
制御装置である。
d.Summary of the Invention The present invention provides a current control device that includes a power conversion circuit using a thyristor that supplies power to an inductive load, and a gate pulse generation circuit that provides firing pulses of the thyristor with a plurality of consecutive pulses. a current level detection circuit that outputs a first logic signal when the load current exceeds a predetermined value; and a timer circuit that outputs a second logic signal after a predetermined time from the timing of starting control of the current control device. and,
A logic circuit is provided for outputting a shift signal for controlling the firing phase of the firing pulse to the delayed side from the first logic signal and the second logic signal, thereby making it possible to prevent burnout of the snubber circuit. This is a current control device.

e 発明の実施例 第3図は、本発明による電流制御装置の一実施
例である。尚第1図の従来回路と同機能の回路
は、同符号を付して説明は省略する。15〜18
が本発明で新に設けたスナバ回路の抵抗の焼損を
防止する為のラツチ不能検出回路の構成である。
15は電流検出回路5の出力信号を入力し、誘導
性負荷3に流れる電流がサイリスタのラツチ電流
以上になつたかどうかを検出する電流レベル検出
回路、16は位相しぼり回路9からのシフト指令
の解除後、すなわち電流制御の開始後所定の時間
遅れを持つて“1”となる論理信号を出力するタ
イマー回路、17はAND回路、18はOR回路で
ある。
e Embodiment of the Invention FIG. 3 shows an embodiment of the current control device according to the present invention. It should be noted that circuits having the same functions as the conventional circuit shown in FIG. 1 are given the same reference numerals and explanations thereof will be omitted. 15-18
This is the configuration of the unlatching detection circuit newly provided in the present invention to prevent burnout of the resistor of the snubber circuit.
15 is a current level detection circuit which inputs the output signal of the current detection circuit 5 and detects whether the current flowing through the inductive load 3 exceeds the thyristor latch current; 16 is a cancellation of the shift command from the phase throttle circuit 9; 17 is an AND circuit, and 18 is an OR circuit.

上記の様に構成した電流制御装置に於て、位相
しぼり回路9からのシフト指令が解除されると通
常の電流制御が開始される。その後順調に起動し
て正常運転に入れば所定の時間後にサイリスタの
ラツチ電流以上の負荷電流が流れ電流レベル検出
回路15の出力には“0”の論理信号が検出され
る。タイマー回路16の出力はシフト指令の解除
後に時限を持つて“1”の論理信号を出力するが
この時限を充分大きく選定すれば正常に起動して
運転に入つたときにはAND回路17の出力には
“1”の論理信号が現われない。
In the current control device configured as described above, normal current control is started when the shift command from the phase throttle circuit 9 is released. After that, if the device starts up smoothly and enters normal operation, a load current greater than the latch current of the thyristor flows after a predetermined period of time, and a logic signal of “0” is detected at the output of the current level detection circuit 15. The output of the timer circuit 16 has a time limit after the shift command is released, and outputs a logic signal of "1". If this time limit is selected to be sufficiently large, the output of the AND circuit 17 will be A logic signal of “1” does not appear.

しかし、前述した様に何等かの原因によりタイ
マー回路16の時限が経過してもラツチ電流に達
しないとき電流レベル検出回路15の出力は
“1”の状態のまヽとなりタイマー回路16の出
力が“1”となつたタイミングAND回路17の
出力が“1”となりこの信号がOR回路18を介
して位相制御回路7にシフト指令として入力され
る。この作用によりラツチ電流に達しない起動不
能の状態を放置してもサイリスタのオン、オフに
よるスナバー回路10〜13のコンデンサの充放
電による電力損失を減少させスナバー回路10〜
13の抵抗の焼損を防止することができる。
However, as mentioned above, if the latch current is not reached even after the time limit of the timer circuit 16 has elapsed due to some reason, the output of the current level detection circuit 15 remains in the "1" state, and the output of the timer circuit 16 remains in the "1" state. When the output of the AND circuit 17 becomes "1", the output becomes "1" and this signal is input to the phase control circuit 7 via the OR circuit 18 as a shift command. This action reduces power loss due to charging and discharging of the capacitors in the snubber circuits 10 to 13 due to turning on and off of the thyristors even if the state where the latch current is not reached and the startup is not possible is left.
It is possible to prevent the No. 13 resistor from burning out.

f 発明の効果 以上説明した様に、本発明によれば、誘導性負
荷を励磁する連続ゲートパルス方式の電流制御装
置に於て、何等かの原因によりサイリスタがラツ
チできず起動不能の状態となつたとき、この状態
で放置されても所定の時間後に自動的にシフト指
令を出すことにより連続ゲートパルスによるサイ
リスタのオン、オフの繰り返しによるスナバー回
路のコンデンサの充放電の繰り返しでスナバー回
路の抵抗に消費される電力損失を減少させ焼損か
ら防止できる電流制御装置を提供することができ
る。
f. Effects of the Invention As explained above, according to the present invention, in a continuous gate pulse type current control device that excites an inductive load, the thyristor cannot latch due to some reason and becomes unable to start. Even if left in this state, a shift command is automatically issued after a predetermined period of time, and the resistance of the snubber circuit is reduced by repeatedly charging and discharging the snubber circuit capacitor by repeatedly turning the thyristor on and off using continuous gate pulses. A current control device that can reduce power loss and prevent burnout can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来の電流制御装置を示すブロツク
図、第2図aは、交流電源の電圧波形図、第2図
b,cはサイリスタのゲートに印加する連続ゲー
トパルス、第2図dは負荷電流の立ち上がりを示
す波形図、第3図は、本発明による電流制御装置
の一実施例を示すブロツク図である。 1……交流電源、2……制御整流回路、3……
誘導性負荷、4……電流基準回路、5……電流検
出回路、6……電流制御演算回路、7……位相制
御回路、8……連続ゲートパルス発生回路、9…
…位相しぼり回路、10,11,12,13……
スナバー回路、14……ダミー抵抗、15……電
流レベル検出回路、16……タイマー回路、17
……AND回路、18……OR回路。
Figure 1 is a block diagram showing a conventional current control device, Figure 2a is a voltage waveform diagram of an AC power supply, Figures 2b and c are continuous gate pulses applied to the gate of the thyristor, and Figure 2d is FIG. 3, a waveform diagram showing the rise of the load current, is a block diagram showing an embodiment of the current control device according to the present invention. 1... AC power supply, 2... Control rectifier circuit, 3...
Inductive load, 4... Current reference circuit, 5... Current detection circuit, 6... Current control calculation circuit, 7... Phase control circuit, 8... Continuous gate pulse generation circuit, 9...
...Phase throttling circuit, 10, 11, 12, 13...
Snubber circuit, 14...Dummy resistor, 15...Current level detection circuit, 16...Timer circuit, 17
...AND circuit, 18...OR circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 誘導性負荷に電力を供給するサイリスタを用
いた電力変換回路と、前記サイリスタの点弧パル
スを連続した複数のパルスで与えるゲートパルス
発生回路を具備した電流制御装置に於て、負荷電
流が所定の値以上になると第1の論理信号を出力
する電流レベル検出回路と、前記電流制御装置の
制御開始のタイミングから所定の時間後に第2の
論理信号を出力するタイマー回路と、前記第1の
論理信号と前記第2の論理信号から前記点弧パル
スの点弧位相を遅れ側に制御するシフト信号を出
力する論理回路を設けたことを特徴とする電流制
御装置。
1. In a current control device equipped with a power conversion circuit using a thyristor that supplies power to an inductive load, and a gate pulse generation circuit that gives the firing pulse of the thyristor as a plurality of consecutive pulses, the load current is controlled to a predetermined level. a current level detection circuit that outputs a first logic signal when the current level reaches a value greater than or equal to a value of A current control device comprising: a logic circuit that outputs a shift signal for controlling the firing phase of the firing pulse to a delayed side based on the signal and the second logic signal.
JP14619682A 1982-08-25 1982-08-25 Current controller Granted JPS5937885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14619682A JPS5937885A (en) 1982-08-25 1982-08-25 Current controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14619682A JPS5937885A (en) 1982-08-25 1982-08-25 Current controller

Publications (2)

Publication Number Publication Date
JPS5937885A JPS5937885A (en) 1984-03-01
JPH0130390B2 true JPH0130390B2 (en) 1989-06-19

Family

ID=15402296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14619682A Granted JPS5937885A (en) 1982-08-25 1982-08-25 Current controller

Country Status (1)

Country Link
JP (1) JPS5937885A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08511827A (en) * 1993-06-25 1996-12-10 ザ、プロクター、エンド、ギャンブル、カンパニー Granular detergent composition containing optimal proportions of certain builders

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08511827A (en) * 1993-06-25 1996-12-10 ザ、プロクター、エンド、ギャンブル、カンパニー Granular detergent composition containing optimal proportions of certain builders

Also Published As

Publication number Publication date
JPS5937885A (en) 1984-03-01

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