JPH01307246A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device having two or more layers of A-crossing lines, etc.

(Prior Art) In a conventional method for manufacturing a semiconductor device having a multilayer wiring structure, as shown in FIG. 2, an insulating film 2 is formed on a silicon substrate 1, and a first A cross line layer is formed on this. After forming the film, the 0th order interlayer insulating film 4, which will form the 1st A vertical wiring 3, is formed using the usual CVD method, sputtering method, spin code method, etc. through the usual 7 etching steps, and is placed in a predetermined position. After resist patterning, a contact hole 5 with the second AU wiring in the upper layer is opened by RIE or the like.

Thereafter, a second A hybrid line layer is formed, a second kl wiring 6 is formed by a normal photorin process, and sintering is performed to establish electrical connection with the first AI wiring.

(Problem to be Solved by the Invention) However, in the above conventional example, after forming the first AIL wiring 3, in the step of forming the interlayer insulating film 4,
Heat treatment above ℃ or equivalent heat process is required.

Therefore, as shown in FIG. 3, the growth of hillocks 81 on the surface of the first AI wiring 3 creates protrusions exceeding 5,000 on the surface of the interlayer insulation IgI 4. In such a surface state, the second Al When attempting to open a contact hole 5 with the wiring, the thickness of the resist at the convex portion becomes significantly thinner than that at the flat portion during resist patterning. Because the selectivity ratio between the resist and the resist may not be large enough, the resist on the convex portion is
As the etching progresses, it disappears and the living room insulating film 4
This may cause it to be etched.

For this reason, there is a problem in that the first All wiring layer 3 and the second Al wiring layer 6 are re-shorted and the withstand voltage is lowered.

(Means for Solving the Problem) According to the present invention, the formation of the interlayer insulating film and the opening of the contact hole are divided into two steps, and the first living room insulating film is formed and then the first living room insulating film is formed.
By opening a contact hole, forming an interlayer insulating film in Section 2, and opening a second contact hole at the same position as the first contact hole, the insulating film in the living room due to hillocks of the first AI wiring can be removed. A decrease in breakdown voltage or a short circuit between the first AI wiring and the second All wiring can be prevented.

(Example) FIGS. 1(Jl) to (f) show an example of the method for manufacturing a semiconductor device according to the present invention.

As shown in FIG. 1(a), after an insulator lI2 is formed on a silicon substrate l, an An or A
A film of 6,000 to 10,000 Atm alloy (hereinafter referred to as A!L) is applied to the entire surface, and after resist patterning, a predetermined 1st A wiring layer 3 is formed by a normal dry etching method.
form.

Next, use P-CvD to increase PSGIgI from 2000 to 600
A first interlayer insulation WJ41 is formed as shown in FIG. 1(b). At this time, since heat of 300° C. or more is applied to the substrate 1, hillocks 81 grow on the surface of the first Ai wiring 3, and convex portions 82 are formed on the surface of the first living room insulating film 41.
will be created.

After this, as shown in Figure 1(C), change the register to 1#L.
Coat to a thickness of m x 1.5#Lm, and perform exposure and development using a predetermined mask.

At this time, the thick resist film on the convex portion 82 of the interlayer insulation 1141 is thinner than the film thickness on the flat portion.

Next, as shown in FIG. 1(d), 02F.

A first contact hole 51 is opened by etching a predetermined portion of the living room insulating film 41 on which the resist pattern has been applied by dry etching using CHF3. Under the dry etching conditions at this time, the etching selectivity between the interlayer insulating film (PSG film) 41 and the resist is 5 to 10:l, so depending on the height of the protrusion 82, the protrusion 82 may be removed during etching.
The resist on 2 disappears, and the interlayer insulating film 41 in this area is etched (concave portion 82°).
As shown in e), the second interlayer insulating film 42 is a normal pressure CV film.
After depositing 3000-5000 PSG by D,
A second contact hole 52 is opened at the same position as the contact hole 51 in the same manner as described above. The amount of etching due to dry etching at this time is ff12 interlayer insulating film 4
You only have to do it as many times as necessary to remove 2.

Further, the size of the second contact hole 52 may be the same as or different from the first contact hole 51, and the size of the second contact hole 52 may be the same as or different from the first contact hole 51. Select an appropriate value depending on the balance of the second interlayer film 42, the film formation method, etc. For example, the first interlayer 1li41 requires 4000 people (PCVD-PSG), and the second interlayer film 42 requires 3000 people (normal pressure CVD-PSG). ), the first contact hole 52 is made to be 2 pm oversized than the second contact hole 51 (the center of the contact hole is at the same position).

A contact hole between the first A sample wiring 3 and the second All wiring 6 can be formed.

Finally, the 2nd A sight line film was sputtered using a film thickness of 600 mm.
0-12000 people deposited, RI after resist patterning
A second Al wiring 6 is formed at a predetermined position using E. (
Although the embodiments shown in FIG. 1(f) and 1 below are for the case where there are two metal wiring layers, the present invention can also be applied to the case of manufacturing a semiconductor device having three or more metal wiring layers. That is, by performing the same steps as in the above embodiment when forming each interlayer insulating film, a similarly good semiconductor device can be manufactured.

(Effects of the Invention) As explained above, by performing the step of forming the interlayer insulating film of the multilayer wiring and the step of opening the contact hole in two steps, the first contact hole 51, the second contact hole 52 (the second contact hole 52) The patterning process can be divided into two steps (see Figure 1(e)), and each etching time is divided by about half (divided in proportion to the thickness of each of the first and second interlayer insulating films) compared to the conventional method. ) can be suppressed.

Therefore, the hillock 81 on the surface of the lower layer AJl wiring (Fig.
Even if the resist formed on the convex portion 82 of the interlayer insulating film 41 becomes thinner due to the method (see c)), it is possible to prevent the resist from disappearing.

Furthermore, even if the resistor disappears and the living room insulating film on the hillock is etched and the hillock 81 is exposed, the second
Since it is covered with an interlayer insulating film, short circuits between wirings will not occur.

Etching of the second contact hole has the same effect as above, and if the first interlayer insulating film above the hillock is etched, the height of the convex part due to the hillock will be flattened by the etched amount. 2nd
The conditions are more favorable for contact hole etching. Furthermore, since the contact holes are opened in two steps, the thickness of the insulation film used to pattern each contact hole can be made thinner.

Therefore, alignment accuracy and minimum contact hole size can be made more accurate and finer. Furthermore, by determining the size of one of the first and second contact holes and increasing the size of the other, it is possible to easily fill the second Al wiring layer into the contact hole. You can also do it.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(f) are cross-sectional views showing steps in an embodiment of the method for manufacturing a semiconductor device according to the present invention. FIG. 2 is a cross-sectional view of a semiconductor device having a conventional A pattern multilayer wiring. FIG. 3 is a cross-sectional view showing the generated hillock and resist layer. 1, silicon substrate 2, insulating film 3, first Ai interconnect 4, interlayer insulating film 5, contact hole 6, second All interconnect 7, resist 41, first interlayer insulating film 42, second P! ! Intermediate insulating film 51, first contact hole 52, second contact hole 81, hillock 82, convex portion 82° of living room insulating film due to hillock, recessed part of living room insulating film

Claims (1)

[Claims] A method for manufacturing a semiconductor device in which two or more metal wiring layers are provided on a semiconductor substrate with interlayer insulating films interposed therebetween, comprising: forming each interlayer insulating film in two steps; First, a first interlayer insulating film is formed, a first contact hole is opened in the insulating film, and then a second interlayer insulating film is formed,
A method for manufacturing a semiconductor device, comprising: opening a second contact hole in the insulating film at a position corresponding to the first contact hole.